4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_DEVMEM_IS_ALLOWED
6 select ARCH_HAS_ELF_RANDOMIZE
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_HAVE_CUSTOM_GPIO_H
9 select ARCH_HAS_GCOV_PROFILE_ALL
10 select ARCH_MIGHT_HAVE_PC_PARPORT
11 select ARCH_SUPPORTS_ATOMIC_RMW
12 select ARCH_USE_BUILTIN_BSWAP
13 select ARCH_USE_CMPXCHG_LOCKREF
14 select ARCH_WANT_IPC_PARSE_VERSION
15 select BUILDTIME_EXTABLE_SORT if MMU
16 select CLONE_BACKWARDS
17 select CPU_PM if (SUSPEND || CPU_IDLE)
18 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
20 select EDAC_ATOMIC_SCRUB
21 select GENERIC_ALLOCATOR
22 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
23 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
24 select GENERIC_EARLY_IOREMAP
25 select GENERIC_IDLE_POLL_SETUP
26 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW
28 select GENERIC_IRQ_SHOW_LEVEL
29 select GENERIC_PCI_IOMAP
30 select GENERIC_SCHED_CLOCK
31 select GENERIC_SMP_IDLE_THREAD
32 select GENERIC_STRNCPY_FROM_USER
33 select GENERIC_STRNLEN_USER
34 select HANDLE_DOMAIN_IRQ
35 select HARDIRQS_SW_RESEND
36 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
37 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
38 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
39 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
40 select HAVE_ARCH_MMAP_RND_BITS if MMU
41 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
42 select HAVE_ARCH_TRACEHOOK
43 select HAVE_ARM_SMCCC if CPU_V7
45 select HAVE_CC_STACKPROTECTOR
46 select HAVE_CONTEXT_TRACKING
47 select HAVE_C_RECORDMCOUNT
48 select HAVE_DEBUG_KMEMLEAK
49 select HAVE_DMA_API_DEBUG
50 select HAVE_DMA_CONTIGUOUS if MMU
51 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
52 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
53 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
54 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
55 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
56 select HAVE_GENERIC_DMA_COHERENT
57 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
58 select HAVE_IDE if PCI || ISA || PCMCIA
59 select HAVE_IRQ_TIME_ACCOUNTING
60 select HAVE_KERNEL_GZIP
61 select HAVE_KERNEL_LZ4
62 select HAVE_KERNEL_LZMA
63 select HAVE_KERNEL_LZO
65 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
66 select HAVE_KRETPROBES if (HAVE_KPROBES)
68 select HAVE_MOD_ARCH_SPECIFIC
69 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
70 select HAVE_OPTPROBES if !THUMB2_KERNEL
71 select HAVE_PERF_EVENTS
73 select HAVE_PERF_USER_STACK_DUMP
74 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
75 select HAVE_REGS_AND_STACK_ACCESS_API
76 select HAVE_SYSCALL_TRACEPOINTS
78 select HAVE_VIRT_CPU_ACCOUNTING_GEN
79 select IRQ_FORCED_THREADING
80 select MODULES_USE_ELF_REL
82 select OF_EARLY_FLATTREE if OF
83 select OF_RESERVED_MEM if OF
85 select OLD_SIGSUSPEND3
86 select PERF_USE_VMALLOC
88 select SYS_SUPPORTS_APM_EMULATION
89 # Above selects are sorted alphabetically; please add new ones
90 # according to that. Thanks.
92 The ARM series is a line of low-power-consumption RISC chip designs
93 licensed by ARM Ltd and targeted at embedded applications and
94 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
95 manufactured, but legacy ARM-based PC hardware remains popular in
96 Europe. There is an ARM Linux project with a web page at
97 <http://www.arm.linux.org.uk/>.
99 config ARM_HAS_SG_CHAIN
100 select ARCH_HAS_SG_CHAIN
103 config NEED_SG_DMA_LENGTH
106 config ARM_DMA_USE_IOMMU
108 select ARM_HAS_SG_CHAIN
109 select NEED_SG_DMA_LENGTH
113 config ARM_DMA_IOMMU_ALIGNMENT
114 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
118 DMA mapping framework by default aligns all buffers to the smallest
119 PAGE_SIZE order which is greater than or equal to the requested buffer
120 size. This works well for buffers up to a few hundreds kilobytes, but
121 for larger buffers it just a waste of address space. Drivers which has
122 relatively small addressing window (like 64Mib) might run out of
123 virtual space with just a few allocations.
125 With this parameter you can specify the maximum PAGE_SIZE order for
126 DMA IOMMU buffers. Larger buffers will be aligned only to this
127 specified order. The order is expressed as a power of two multiplied
132 config MIGHT_HAVE_PCI
135 config SYS_SUPPORTS_APM_EMULATION
140 select GENERIC_ALLOCATOR
151 The Extended Industry Standard Architecture (EISA) bus was
152 developed as an open alternative to the IBM MicroChannel bus.
154 The EISA bus provided some of the features of the IBM MicroChannel
155 bus while maintaining backward compatibility with cards made for
156 the older ISA bus. The EISA bus saw limited use between 1988 and
157 1995 when it was made obsolete by the PCI bus.
159 Say Y here if you are building a kernel for an EISA-based machine.
166 config STACKTRACE_SUPPORT
170 config LOCKDEP_SUPPORT
174 config TRACE_IRQFLAGS_SUPPORT
178 config RWSEM_XCHGADD_ALGORITHM
182 config ARCH_HAS_ILOG2_U32
185 config ARCH_HAS_ILOG2_U64
188 config ARCH_HAS_BANDGAP
191 config FIX_EARLYCON_MEM
194 config GENERIC_HWEIGHT
198 config GENERIC_CALIBRATE_DELAY
202 config ARCH_MAY_HAVE_PC_FDC
208 config NEED_DMA_MAP_STATE
211 config ARCH_SUPPORTS_UPROBES
214 config ARCH_HAS_DMA_SET_COHERENT_MASK
217 config GENERIC_ISA_DMA
223 config NEED_RET_TO_USER
231 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
232 default DRAM_BASE if REMAP_VECTORS_TO_RAM
235 The base address of exception vectors. This must be two pages
238 config ARM_PATCH_PHYS_VIRT
239 bool "Patch physical to virtual translations at runtime" if EMBEDDED
241 depends on !XIP_KERNEL && MMU
243 Patch phys-to-virt and virt-to-phys translation functions at
244 boot and module load time according to the position of the
245 kernel in system memory.
247 This can only be used with non-XIP MMU kernels where the base
248 of physical memory is at a 16MB boundary.
250 Only disable this option if you know that you do not require
251 this feature (eg, building a kernel for a single machine) and
252 you need to shrink the kernel to the minimal size.
254 config NEED_MACH_IO_H
257 Select this when mach/io.h is required to provide special
258 definitions for this platform. The need for mach/io.h should
259 be avoided when possible.
261 config NEED_MACH_MEMORY_H
264 Select this when mach/memory.h is required to provide special
265 definitions for this platform. The need for mach/memory.h should
266 be avoided when possible.
269 hex "Physical address of main memory" if MMU
270 depends on !ARM_PATCH_PHYS_VIRT
271 default DRAM_BASE if !MMU
272 default 0x00000000 if ARCH_EBSA110 || \
277 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
278 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
279 default 0x20000000 if ARCH_S5PV210
280 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
281 default 0xc0000000 if ARCH_SA1100
283 Please provide the physical address corresponding to the
284 location of main memory in your system.
290 config PGTABLE_LEVELS
292 default 3 if ARM_LPAE
295 source "init/Kconfig"
297 source "kernel/Kconfig.freezer"
302 bool "MMU-based Paged Memory Management Support"
305 Select if you want MMU-based virtualised addressing space
306 support by paged memory management. If unsure, say 'Y'.
308 config ARCH_MMAP_RND_BITS_MIN
311 config ARCH_MMAP_RND_BITS_MAX
312 default 14 if PAGE_OFFSET=0x40000000
313 default 15 if PAGE_OFFSET=0x80000000
317 # The "ARM system type" choice list is ordered alphabetically by option
318 # text. Please add new entries in the option alphabetic order.
321 prompt "ARM system type"
322 default ARM_SINGLE_ARMV7M if !MMU
323 default ARCH_MULTIPLATFORM if MMU
325 config ARCH_MULTIPLATFORM
326 bool "Allow multiple platforms to be selected"
328 select ARCH_WANT_OPTIONAL_GPIOLIB
329 select ARM_HAS_SG_CHAIN
330 select ARM_PATCH_PHYS_VIRT
334 select GENERIC_CLOCKEVENTS
335 select MIGHT_HAVE_PCI
336 select MULTI_IRQ_HANDLER
340 config ARM_SINGLE_ARMV7M
341 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
343 select ARCH_WANT_OPTIONAL_GPIOLIB
349 select GENERIC_CLOCKEVENTS
356 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
357 select ARCH_REQUIRE_GPIOLIB
362 select GENERIC_CLOCKEVENTS
366 Support for Cirrus Logic 711x/721x/731x based boards.
369 bool "Cortina Systems Gemini"
370 select ARCH_REQUIRE_GPIOLIB
373 select GENERIC_CLOCKEVENTS
375 Support for the Cortina Systems Gemini family SoCs
379 select ARCH_USES_GETTIMEOFFSET
382 select NEED_MACH_IO_H
383 select NEED_MACH_MEMORY_H
386 This is an evaluation board for the StrongARM processor available
387 from Digital. It has limited hardware on-board, including an
388 Ethernet interface, two PCMCIA sockets, two serial ports and a
393 select ARCH_HAS_HOLES_MEMORYMODEL
394 select ARCH_REQUIRE_GPIOLIB
396 select ARM_PATCH_PHYS_VIRT
402 select GENERIC_CLOCKEVENTS
404 This enables support for the Cirrus EP93xx series of CPUs.
406 config ARCH_FOOTBRIDGE
410 select GENERIC_CLOCKEVENTS
412 select NEED_MACH_IO_H if !MMU
413 select NEED_MACH_MEMORY_H
415 Support for systems based on the DC21285 companion chip
416 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
419 bool "Hilscher NetX based"
423 select GENERIC_CLOCKEVENTS
425 This enables support for systems based on the Hilscher NetX Soc
431 select NEED_MACH_MEMORY_H
432 select NEED_RET_TO_USER
438 Support for Intel's IOP13XX (XScale) family of processors.
443 select ARCH_REQUIRE_GPIOLIB
446 select NEED_RET_TO_USER
450 Support for Intel's 80219 and IOP32X (XScale) family of
456 select ARCH_REQUIRE_GPIOLIB
459 select NEED_RET_TO_USER
463 Support for Intel's IOP33X (XScale) family of processors.
468 select ARCH_HAS_DMA_SET_COHERENT_MASK
469 select ARCH_REQUIRE_GPIOLIB
470 select ARCH_SUPPORTS_BIG_ENDIAN
473 select DMABOUNCE if PCI
474 select GENERIC_CLOCKEVENTS
475 select MIGHT_HAVE_PCI
476 select NEED_MACH_IO_H
477 select USB_EHCI_BIG_ENDIAN_DESC
478 select USB_EHCI_BIG_ENDIAN_MMIO
480 Support for Intel's IXP4XX (XScale) family of processors.
484 select ARCH_REQUIRE_GPIOLIB
486 select GENERIC_CLOCKEVENTS
487 select MIGHT_HAVE_PCI
488 select MULTI_IRQ_HANDLER
492 select PLAT_ORION_LEGACY
494 select PM_GENERIC_DOMAINS if PM
496 Support for the Marvell Dove SoC 88AP510
499 bool "Micrel/Kendin KS8695"
500 select ARCH_REQUIRE_GPIOLIB
503 select GENERIC_CLOCKEVENTS
504 select NEED_MACH_MEMORY_H
506 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
507 System-on-Chip devices.
510 bool "Nuvoton W90X900 CPU"
511 select ARCH_REQUIRE_GPIOLIB
515 select GENERIC_CLOCKEVENTS
517 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
518 At present, the w90x900 has been renamed nuc900, regarding
519 the ARM series product line, you can login the following
520 link address to know more.
522 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
523 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
527 select ARCH_REQUIRE_GPIOLIB
532 select GENERIC_CLOCKEVENTS
536 Support for the NXP LPC32XX family of processors
539 bool "PXA2xx/PXA3xx-based"
542 select ARCH_REQUIRE_GPIOLIB
543 select ARM_CPU_SUSPEND if PM
550 select GENERIC_CLOCKEVENTS
554 select MULTI_IRQ_HANDLER
558 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
564 select ARCH_MAY_HAVE_PC_FDC
565 select ARCH_SPARSEMEM_ENABLE
566 select ARCH_USES_GETTIMEOFFSET
570 select HAVE_PATA_PLATFORM
572 select NEED_MACH_IO_H
573 select NEED_MACH_MEMORY_H
576 On the Acorn Risc-PC, Linux can support the internal IDE disk and
577 CD-ROM interface, serial and parallel port, and the floppy drive.
582 select ARCH_REQUIRE_GPIOLIB
583 select ARCH_SPARSEMEM_ENABLE
587 select CLKSRC_OF if OF
590 select GENERIC_CLOCKEVENTS
594 select MULTI_IRQ_HANDLER
595 select NEED_MACH_MEMORY_H
598 Support for StrongARM 11x0 based boards.
601 bool "Samsung S3C24XX SoCs"
602 select ARCH_REQUIRE_GPIOLIB
605 select CLKSRC_SAMSUNG_PWM
606 select GENERIC_CLOCKEVENTS
608 select HAVE_S3C2410_I2C if I2C
609 select HAVE_S3C2410_WATCHDOG if WATCHDOG
610 select HAVE_S3C_RTC if RTC_CLASS
611 select MULTI_IRQ_HANDLER
612 select NEED_MACH_IO_H
615 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
616 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
617 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
618 Samsung SMDK2410 development board (and derivatives).
622 select ARCH_HAS_HOLES_MEMORYMODEL
623 select ARCH_REQUIRE_GPIOLIB
625 select GENERIC_ALLOCATOR
626 select GENERIC_CLOCKEVENTS
627 select GENERIC_IRQ_CHIP
632 Support for TI's DaVinci platform.
637 select ARCH_HAS_HOLES_MEMORYMODEL
639 select ARCH_REQUIRE_GPIOLIB
642 select GENERIC_CLOCKEVENTS
643 select GENERIC_IRQ_CHIP
646 select MULTI_IRQ_HANDLER
647 select NEED_MACH_IO_H if PCCARD
648 select NEED_MACH_MEMORY_H
651 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
655 menu "Multiple platform selection"
656 depends on ARCH_MULTIPLATFORM
658 comment "CPU Core family selection"
661 bool "ARMv4 based platforms (FA526)"
662 depends on !ARCH_MULTI_V6_V7
663 select ARCH_MULTI_V4_V5
666 config ARCH_MULTI_V4T
667 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
668 depends on !ARCH_MULTI_V6_V7
669 select ARCH_MULTI_V4_V5
670 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
671 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
672 CPU_ARM925T || CPU_ARM940T)
675 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
676 depends on !ARCH_MULTI_V6_V7
677 select ARCH_MULTI_V4_V5
678 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
679 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
680 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
682 config ARCH_MULTI_V4_V5
686 bool "ARMv6 based platforms (ARM11)"
687 select ARCH_MULTI_V6_V7
691 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
693 select ARCH_MULTI_V6_V7
697 config ARCH_MULTI_V6_V7
699 select MIGHT_HAVE_CACHE_L2X0
701 config ARCH_MULTI_CPU_AUTO
702 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
708 bool "Dummy Virtual Machine"
709 depends on ARCH_MULTI_V7
712 select ARM_GIC_V2M if PCI_MSI
715 select HAVE_ARM_ARCH_TIMER
718 # This is sorted alphabetically by mach-* pathname. However, plat-*
719 # Kconfigs may be included either alphabetically (according to the
720 # plat- suffix) or along side the corresponding mach-* source.
722 source "arch/arm/mach-mvebu/Kconfig"
724 source "arch/arm/mach-alpine/Kconfig"
726 source "arch/arm/mach-asm9260/Kconfig"
728 source "arch/arm/mach-at91/Kconfig"
730 source "arch/arm/mach-axxia/Kconfig"
732 source "arch/arm/mach-bcm/Kconfig"
734 source "arch/arm/mach-berlin/Kconfig"
736 source "arch/arm/mach-clps711x/Kconfig"
738 source "arch/arm/mach-cns3xxx/Kconfig"
740 source "arch/arm/mach-davinci/Kconfig"
742 source "arch/arm/mach-digicolor/Kconfig"
744 source "arch/arm/mach-dove/Kconfig"
746 source "arch/arm/mach-ep93xx/Kconfig"
748 source "arch/arm/mach-footbridge/Kconfig"
750 source "arch/arm/mach-gemini/Kconfig"
752 source "arch/arm/mach-highbank/Kconfig"
754 source "arch/arm/mach-hisi/Kconfig"
756 source "arch/arm/mach-integrator/Kconfig"
758 source "arch/arm/mach-iop32x/Kconfig"
760 source "arch/arm/mach-iop33x/Kconfig"
762 source "arch/arm/mach-iop13xx/Kconfig"
764 source "arch/arm/mach-ixp4xx/Kconfig"
766 source "arch/arm/mach-keystone/Kconfig"
768 source "arch/arm/mach-ks8695/Kconfig"
770 source "arch/arm/mach-meson/Kconfig"
772 source "arch/arm/mach-moxart/Kconfig"
774 source "arch/arm/mach-mv78xx0/Kconfig"
776 source "arch/arm/mach-imx/Kconfig"
778 source "arch/arm/mach-mediatek/Kconfig"
780 source "arch/arm/mach-mxs/Kconfig"
782 source "arch/arm/mach-netx/Kconfig"
784 source "arch/arm/mach-nomadik/Kconfig"
786 source "arch/arm/mach-nspire/Kconfig"
788 source "arch/arm/plat-omap/Kconfig"
790 source "arch/arm/mach-omap1/Kconfig"
792 source "arch/arm/mach-omap2/Kconfig"
794 source "arch/arm/mach-orion5x/Kconfig"
796 source "arch/arm/mach-picoxcell/Kconfig"
798 source "arch/arm/mach-pxa/Kconfig"
799 source "arch/arm/plat-pxa/Kconfig"
801 source "arch/arm/mach-mmp/Kconfig"
803 source "arch/arm/mach-qcom/Kconfig"
805 source "arch/arm/mach-realview/Kconfig"
807 source "arch/arm/mach-rockchip/Kconfig"
809 source "arch/arm/mach-sa1100/Kconfig"
811 source "arch/arm/mach-socfpga/Kconfig"
813 source "arch/arm/mach-spear/Kconfig"
815 source "arch/arm/mach-sti/Kconfig"
817 source "arch/arm/mach-s3c24xx/Kconfig"
819 source "arch/arm/mach-s3c64xx/Kconfig"
821 source "arch/arm/mach-s5pv210/Kconfig"
823 source "arch/arm/mach-exynos/Kconfig"
824 source "arch/arm/plat-samsung/Kconfig"
826 source "arch/arm/mach-shmobile/Kconfig"
828 source "arch/arm/mach-sunxi/Kconfig"
830 source "arch/arm/mach-prima2/Kconfig"
832 source "arch/arm/mach-tango/Kconfig"
834 source "arch/arm/mach-tegra/Kconfig"
836 source "arch/arm/mach-u300/Kconfig"
838 source "arch/arm/mach-uniphier/Kconfig"
840 source "arch/arm/mach-ux500/Kconfig"
842 source "arch/arm/mach-versatile/Kconfig"
844 source "arch/arm/mach-vexpress/Kconfig"
845 source "arch/arm/plat-versatile/Kconfig"
847 source "arch/arm/mach-vt8500/Kconfig"
849 source "arch/arm/mach-w90x900/Kconfig"
851 source "arch/arm/mach-zx/Kconfig"
853 source "arch/arm/mach-zynq/Kconfig"
855 # ARMv7-M architecture
857 bool "Energy Micro efm32"
858 depends on ARM_SINGLE_ARMV7M
859 select ARCH_REQUIRE_GPIOLIB
861 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
865 bool "NXP LPC18xx/LPC43xx"
866 depends on ARM_SINGLE_ARMV7M
867 select ARCH_HAS_RESET_CONTROLLER
869 select CLKSRC_LPC32XX
872 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
873 high performance microcontrollers.
876 bool "STMicrolectronics STM32"
877 depends on ARM_SINGLE_ARMV7M
878 select ARCH_HAS_RESET_CONTROLLER
879 select ARMV7M_SYSTICK
881 select RESET_CONTROLLER
883 Support for STMicroelectronics STM32 processors.
885 # Definitions to make life easier
891 select GENERIC_CLOCKEVENTS
897 select GENERIC_IRQ_CHIP
900 config PLAT_ORION_LEGACY
907 config PLAT_VERSATILE
910 source "arch/arm/firmware/Kconfig"
912 source arch/arm/mm/Kconfig
915 bool "Enable iWMMXt support"
916 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
917 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
919 Enable support for iWMMXt context switching at run time if
920 running on a CPU that supports it.
922 config MULTI_IRQ_HANDLER
925 Allow each machine to specify it's own IRQ handler at run time.
928 source "arch/arm/Kconfig-nommu"
931 config PJ4B_ERRATA_4742
932 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
933 depends on CPU_PJ4B && MACH_ARMADA_370
936 When coming out of either a Wait for Interrupt (WFI) or a Wait for
937 Event (WFE) IDLE states, a specific timing sensitivity exists between
938 the retiring WFI/WFE instructions and the newly issued subsequent
939 instructions. This sensitivity can result in a CPU hang scenario.
941 The software must insert either a Data Synchronization Barrier (DSB)
942 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
945 config ARM_ERRATA_326103
946 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
949 Executing a SWP instruction to read-only memory does not set bit 11
950 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
951 treat the access as a read, preventing a COW from occurring and
952 causing the faulting task to livelock.
954 config ARM_ERRATA_411920
955 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
956 depends on CPU_V6 || CPU_V6K
958 Invalidation of the Instruction Cache operation can
959 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
960 It does not affect the MPCore. This option enables the ARM Ltd.
961 recommended workaround.
963 config ARM_ERRATA_430973
964 bool "ARM errata: Stale prediction on replaced interworking branch"
967 This option enables the workaround for the 430973 Cortex-A8
968 r1p* erratum. If a code sequence containing an ARM/Thumb
969 interworking branch is replaced with another code sequence at the
970 same virtual address, whether due to self-modifying code or virtual
971 to physical address re-mapping, Cortex-A8 does not recover from the
972 stale interworking branch prediction. This results in Cortex-A8
973 executing the new code sequence in the incorrect ARM or Thumb state.
974 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
975 and also flushes the branch target cache at every context switch.
976 Note that setting specific bits in the ACTLR register may not be
977 available in non-secure mode.
979 config ARM_ERRATA_458693
980 bool "ARM errata: Processor deadlock when a false hazard is created"
982 depends on !ARCH_MULTIPLATFORM
984 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
985 erratum. For very specific sequences of memory operations, it is
986 possible for a hazard condition intended for a cache line to instead
987 be incorrectly associated with a different cache line. This false
988 hazard might then cause a processor deadlock. The workaround enables
989 the L1 caching of the NEON accesses and disables the PLD instruction
990 in the ACTLR register. Note that setting specific bits in the ACTLR
991 register may not be available in non-secure mode.
993 config ARM_ERRATA_460075
994 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
996 depends on !ARCH_MULTIPLATFORM
998 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
999 erratum. Any asynchronous access to the L2 cache may encounter a
1000 situation in which recent store transactions to the L2 cache are lost
1001 and overwritten with stale memory contents from external memory. The
1002 workaround disables the write-allocate mode for the L2 cache via the
1003 ACTLR register. Note that setting specific bits in the ACTLR register
1004 may not be available in non-secure mode.
1006 config ARM_ERRATA_742230
1007 bool "ARM errata: DMB operation may be faulty"
1008 depends on CPU_V7 && SMP
1009 depends on !ARCH_MULTIPLATFORM
1011 This option enables the workaround for the 742230 Cortex-A9
1012 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1013 between two write operations may not ensure the correct visibility
1014 ordering of the two writes. This workaround sets a specific bit in
1015 the diagnostic register of the Cortex-A9 which causes the DMB
1016 instruction to behave as a DSB, ensuring the correct behaviour of
1019 config ARM_ERRATA_742231
1020 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1021 depends on CPU_V7 && SMP
1022 depends on !ARCH_MULTIPLATFORM
1024 This option enables the workaround for the 742231 Cortex-A9
1025 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1026 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1027 accessing some data located in the same cache line, may get corrupted
1028 data due to bad handling of the address hazard when the line gets
1029 replaced from one of the CPUs at the same time as another CPU is
1030 accessing it. This workaround sets specific bits in the diagnostic
1031 register of the Cortex-A9 which reduces the linefill issuing
1032 capabilities of the processor.
1034 config ARM_ERRATA_643719
1035 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1036 depends on CPU_V7 && SMP
1039 This option enables the workaround for the 643719 Cortex-A9 (prior to
1040 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1041 register returns zero when it should return one. The workaround
1042 corrects this value, ensuring cache maintenance operations which use
1043 it behave as intended and avoiding data corruption.
1045 config ARM_ERRATA_720789
1046 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1049 This option enables the workaround for the 720789 Cortex-A9 (prior to
1050 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1051 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1052 As a consequence of this erratum, some TLB entries which should be
1053 invalidated are not, resulting in an incoherency in the system page
1054 tables. The workaround changes the TLB flushing routines to invalidate
1055 entries regardless of the ASID.
1057 config ARM_ERRATA_743622
1058 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1060 depends on !ARCH_MULTIPLATFORM
1062 This option enables the workaround for the 743622 Cortex-A9
1063 (r2p*) erratum. Under very rare conditions, a faulty
1064 optimisation in the Cortex-A9 Store Buffer may lead to data
1065 corruption. This workaround sets a specific bit in the diagnostic
1066 register of the Cortex-A9 which disables the Store Buffer
1067 optimisation, preventing the defect from occurring. This has no
1068 visible impact on the overall performance or power consumption of the
1071 config ARM_ERRATA_751472
1072 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1074 depends on !ARCH_MULTIPLATFORM
1076 This option enables the workaround for the 751472 Cortex-A9 (prior
1077 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1078 completion of a following broadcasted operation if the second
1079 operation is received by a CPU before the ICIALLUIS has completed,
1080 potentially leading to corrupted entries in the cache or TLB.
1082 config ARM_ERRATA_754322
1083 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1086 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1087 r3p*) erratum. A speculative memory access may cause a page table walk
1088 which starts prior to an ASID switch but completes afterwards. This
1089 can populate the micro-TLB with a stale entry which may be hit with
1090 the new ASID. This workaround places two dsb instructions in the mm
1091 switching code so that no page table walks can cross the ASID switch.
1093 config ARM_ERRATA_754327
1094 bool "ARM errata: no automatic Store Buffer drain"
1095 depends on CPU_V7 && SMP
1097 This option enables the workaround for the 754327 Cortex-A9 (prior to
1098 r2p0) erratum. The Store Buffer does not have any automatic draining
1099 mechanism and therefore a livelock may occur if an external agent
1100 continuously polls a memory location waiting to observe an update.
1101 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1102 written polling loops from denying visibility of updates to memory.
1104 config ARM_ERRATA_364296
1105 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1108 This options enables the workaround for the 364296 ARM1136
1109 r0p2 erratum (possible cache data corruption with
1110 hit-under-miss enabled). It sets the undocumented bit 31 in
1111 the auxiliary control register and the FI bit in the control
1112 register, thus disabling hit-under-miss without putting the
1113 processor into full low interrupt latency mode. ARM11MPCore
1116 config ARM_ERRATA_764369
1117 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1118 depends on CPU_V7 && SMP
1120 This option enables the workaround for erratum 764369
1121 affecting Cortex-A9 MPCore with two or more processors (all
1122 current revisions). Under certain timing circumstances, a data
1123 cache line maintenance operation by MVA targeting an Inner
1124 Shareable memory region may fail to proceed up to either the
1125 Point of Coherency or to the Point of Unification of the
1126 system. This workaround adds a DSB instruction before the
1127 relevant cache maintenance functions and sets a specific bit
1128 in the diagnostic control register of the SCU.
1130 config ARM_ERRATA_775420
1131 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1134 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1135 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1136 operation aborts with MMU exception, it might cause the processor
1137 to deadlock. This workaround puts DSB before executing ISB if
1138 an abort may occur on cache maintenance.
1140 config ARM_ERRATA_798181
1141 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1142 depends on CPU_V7 && SMP
1144 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1145 adequately shooting down all use of the old entries. This
1146 option enables the Linux kernel workaround for this erratum
1147 which sends an IPI to the CPUs that are running the same ASID
1148 as the one being invalidated.
1150 config ARM_ERRATA_773022
1151 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1154 This option enables the workaround for the 773022 Cortex-A15
1155 (up to r0p4) erratum. In certain rare sequences of code, the
1156 loop buffer may deliver incorrect instructions. This
1157 workaround disables the loop buffer to avoid the erratum.
1161 source "arch/arm/common/Kconfig"
1168 Find out whether you have ISA slots on your motherboard. ISA is the
1169 name of a bus system, i.e. the way the CPU talks to the other stuff
1170 inside your box. Other bus systems are PCI, EISA, MicroChannel
1171 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1172 newer boards don't support it. If you have ISA, say Y, otherwise N.
1174 # Select ISA DMA controller support
1179 # Select ISA DMA interface
1184 bool "PCI support" if MIGHT_HAVE_PCI
1186 Find out whether you have a PCI motherboard. PCI is the name of a
1187 bus system, i.e. the way the CPU talks to the other stuff inside
1188 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1189 VESA. If you have PCI, say Y, otherwise N.
1195 config PCI_DOMAINS_GENERIC
1196 def_bool PCI_DOMAINS
1198 config PCI_NANOENGINE
1199 bool "BSE nanoEngine PCI support"
1200 depends on SA1100_NANOENGINE
1202 Enable PCI on the BSE nanoEngine board.
1207 config PCI_HOST_ITE8152
1209 depends on PCI && MACH_ARMCORE
1213 source "drivers/pci/Kconfig"
1215 source "drivers/pcmcia/Kconfig"
1219 menu "Kernel Features"
1224 This option should be selected by machines which have an SMP-
1227 The only effect of this option is to make the SMP-related
1228 options available to the user for configuration.
1231 bool "Symmetric Multi-Processing"
1232 depends on CPU_V6K || CPU_V7
1233 depends on GENERIC_CLOCKEVENTS
1235 depends on MMU || ARM_MPU
1238 This enables support for systems with more than one CPU. If you have
1239 a system with only one CPU, say N. If you have a system with more
1240 than one CPU, say Y.
1242 If you say N here, the kernel will run on uni- and multiprocessor
1243 machines, but will use only one CPU of a multiprocessor machine. If
1244 you say Y here, the kernel will run on many, but not all,
1245 uniprocessor machines. On a uniprocessor machine, the kernel
1246 will run faster if you say N here.
1248 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1249 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1250 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1252 If you don't know what to do here, say N.
1255 bool "Allow booting SMP kernel on uniprocessor systems"
1256 depends on SMP && !XIP_KERNEL && MMU
1259 SMP kernels contain instructions which fail on non-SMP processors.
1260 Enabling this option allows the kernel to modify itself to make
1261 these instructions safe. Disabling it allows about 1K of space
1264 If you don't know what to do here, say Y.
1266 config ARM_CPU_TOPOLOGY
1267 bool "Support cpu topology definition"
1268 depends on SMP && CPU_V7
1271 Support ARM cpu topology definition. The MPIDR register defines
1272 affinity between processors which is then used to describe the cpu
1273 topology of an ARM System.
1276 bool "Multi-core scheduler support"
1277 depends on ARM_CPU_TOPOLOGY
1279 Multi-core scheduler support improves the CPU scheduler's decision
1280 making when dealing with multi-core CPU chips at a cost of slightly
1281 increased overhead in some places. If unsure say N here.
1284 bool "SMT scheduler support"
1285 depends on ARM_CPU_TOPOLOGY
1287 Improves the CPU scheduler's decision making when dealing with
1288 MultiThreading at a cost of slightly increased overhead in some
1289 places. If unsure say N here.
1294 This option enables support for the ARM system coherency unit
1296 config HAVE_ARM_ARCH_TIMER
1297 bool "Architected timer support"
1299 select ARM_ARCH_TIMER
1300 select GENERIC_CLOCKEVENTS
1302 This option enables support for the ARM architected timer
1306 select CLKSRC_OF if OF
1308 This options enables support for the ARM timer and watchdog unit
1311 bool "Multi-Cluster Power Management"
1312 depends on CPU_V7 && SMP
1314 This option provides the common power management infrastructure
1315 for (multi-)cluster based systems, such as big.LITTLE based
1318 config MCPM_QUAD_CLUSTER
1322 To avoid wasting resources unnecessarily, MCPM only supports up
1323 to 2 clusters by default.
1324 Platforms with 3 or 4 clusters that use MCPM must select this
1325 option to allow the additional clusters to be managed.
1328 bool "big.LITTLE support (Experimental)"
1329 depends on CPU_V7 && SMP
1332 This option enables support selections for the big.LITTLE
1333 system architecture.
1336 bool "big.LITTLE switcher support"
1337 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1340 The big.LITTLE "switcher" provides the core functionality to
1341 transparently handle transition between a cluster of A15's
1342 and a cluster of A7's in a big.LITTLE system.
1344 config BL_SWITCHER_DUMMY_IF
1345 tristate "Simple big.LITTLE switcher user interface"
1346 depends on BL_SWITCHER && DEBUG_KERNEL
1348 This is a simple and dummy char dev interface to control
1349 the big.LITTLE switcher core code. It is meant for
1350 debugging purposes only.
1353 prompt "Memory split"
1357 Select the desired split between kernel and user memory.
1359 If you are not absolutely sure what you are doing, leave this
1363 bool "3G/1G user/kernel split"
1364 config VMSPLIT_3G_OPT
1365 bool "3G/1G user/kernel split (for full 1G low memory)"
1367 bool "2G/2G user/kernel split"
1369 bool "1G/3G user/kernel split"
1374 default PHYS_OFFSET if !MMU
1375 default 0x40000000 if VMSPLIT_1G
1376 default 0x80000000 if VMSPLIT_2G
1377 default 0xB0000000 if VMSPLIT_3G_OPT
1381 int "Maximum number of CPUs (2-32)"
1387 bool "Support for hot-pluggable CPUs"
1390 Say Y here to experiment with turning CPUs off and on. CPUs
1391 can be controlled through /sys/devices/system/cpu.
1394 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1395 depends on HAVE_ARM_SMCCC
1398 Say Y here if you want Linux to communicate with system firmware
1399 implementing the PSCI specification for CPU-centric power
1400 management operations described in ARM document number ARM DEN
1401 0022A ("Power State Coordination Interface System Software on
1404 # The GPIO number here must be sorted by descending number. In case of
1405 # a multiplatform kernel, we just want the highest value required by the
1406 # selected platforms.
1409 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1411 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1412 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1413 default 416 if ARCH_SUNXI
1414 default 392 if ARCH_U8500
1415 default 352 if ARCH_VT8500
1416 default 288 if ARCH_ROCKCHIP
1417 default 264 if MACH_H4700
1420 Maximum number of GPIOs in the system.
1422 If unsure, leave the default value.
1424 source kernel/Kconfig.preempt
1428 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1429 ARCH_S5PV210 || ARCH_EXYNOS4
1430 default 128 if SOC_AT91RM9200
1434 depends on HZ_FIXED = 0
1435 prompt "Timer frequency"
1459 default HZ_FIXED if HZ_FIXED != 0
1460 default 100 if HZ_100
1461 default 200 if HZ_200
1462 default 250 if HZ_250
1463 default 300 if HZ_300
1464 default 500 if HZ_500
1468 def_bool HIGH_RES_TIMERS
1470 config THUMB2_KERNEL
1471 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1472 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1473 default y if CPU_THUMBONLY
1475 select ARM_ASM_UNIFIED
1478 By enabling this option, the kernel will be compiled in
1479 Thumb-2 mode. A compiler/assembler that understand the unified
1480 ARM-Thumb syntax is needed.
1484 config THUMB2_AVOID_R_ARM_THM_JUMP11
1485 bool "Work around buggy Thumb-2 short branch relocations in gas"
1486 depends on THUMB2_KERNEL && MODULES
1489 Various binutils versions can resolve Thumb-2 branches to
1490 locally-defined, preemptible global symbols as short-range "b.n"
1491 branch instructions.
1493 This is a problem, because there's no guarantee the final
1494 destination of the symbol, or any candidate locations for a
1495 trampoline, are within range of the branch. For this reason, the
1496 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1497 relocation in modules at all, and it makes little sense to add
1500 The symptom is that the kernel fails with an "unsupported
1501 relocation" error when loading some modules.
1503 Until fixed tools are available, passing
1504 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1505 code which hits this problem, at the cost of a bit of extra runtime
1506 stack usage in some cases.
1508 The problem is described in more detail at:
1509 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1511 Only Thumb-2 kernels are affected.
1513 Unless you are sure your tools don't have this problem, say Y.
1515 config ARM_ASM_UNIFIED
1518 config ARM_PATCH_IDIV
1519 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1520 depends on CPU_32v7 && !XIP_KERNEL
1523 The ARM compiler inserts calls to __aeabi_idiv() and
1524 __aeabi_uidiv() when it needs to perform division on signed
1525 and unsigned integers. Some v7 CPUs have support for the sdiv
1526 and udiv instructions that can be used to implement those
1529 Enabling this option allows the kernel to modify itself to
1530 replace the first two instructions of these library functions
1531 with the sdiv or udiv plus "bx lr" instructions when the CPU
1532 it is running on supports them. Typically this will be faster
1533 and less power intensive than running the original library
1534 code to do integer division.
1537 bool "Use the ARM EABI to compile the kernel"
1539 This option allows for the kernel to be compiled using the latest
1540 ARM ABI (aka EABI). This is only useful if you are using a user
1541 space environment that is also compiled with EABI.
1543 Since there are major incompatibilities between the legacy ABI and
1544 EABI, especially with regard to structure member alignment, this
1545 option also changes the kernel syscall calling convention to
1546 disambiguate both ABIs and allow for backward compatibility support
1547 (selected with CONFIG_OABI_COMPAT).
1549 To use this you need GCC version 4.0.0 or later.
1552 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1553 depends on AEABI && !THUMB2_KERNEL
1555 This option preserves the old syscall interface along with the
1556 new (ARM EABI) one. It also provides a compatibility layer to
1557 intercept syscalls that have structure arguments which layout
1558 in memory differs between the legacy ABI and the new ARM EABI
1559 (only for non "thumb" binaries). This option adds a tiny
1560 overhead to all syscalls and produces a slightly larger kernel.
1562 The seccomp filter system will not be available when this is
1563 selected, since there is no way yet to sensibly distinguish
1564 between calling conventions during filtering.
1566 If you know you'll be using only pure EABI user space then you
1567 can say N here. If this option is not selected and you attempt
1568 to execute a legacy ABI binary then the result will be
1569 UNPREDICTABLE (in fact it can be predicted that it won't work
1570 at all). If in doubt say N.
1572 config ARCH_HAS_HOLES_MEMORYMODEL
1575 config ARCH_SPARSEMEM_ENABLE
1578 config ARCH_SPARSEMEM_DEFAULT
1579 def_bool ARCH_SPARSEMEM_ENABLE
1581 config ARCH_SELECT_MEMORY_MODEL
1582 def_bool ARCH_SPARSEMEM_ENABLE
1584 config HAVE_ARCH_PFN_VALID
1585 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1587 config HAVE_GENERIC_RCU_GUP
1592 bool "High Memory Support"
1595 The address space of ARM processors is only 4 Gigabytes large
1596 and it has to accommodate user address space, kernel address
1597 space as well as some memory mapped IO. That means that, if you
1598 have a large amount of physical memory and/or IO, not all of the
1599 memory can be "permanently mapped" by the kernel. The physical
1600 memory that is not permanently mapped is called "high memory".
1602 Depending on the selected kernel/user memory split, minimum
1603 vmalloc space and actual amount of RAM, you may not need this
1604 option which should result in a slightly faster kernel.
1609 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1613 The VM uses one page of physical memory for each page table.
1614 For systems with a lot of processes, this can use a lot of
1615 precious low memory, eventually leading to low memory being
1616 consumed by page tables. Setting this option will allow
1617 user-space 2nd level page tables to reside in high memory.
1619 config CPU_SW_DOMAIN_PAN
1620 bool "Enable use of CPU domains to implement privileged no-access"
1621 depends on MMU && !ARM_LPAE
1624 Increase kernel security by ensuring that normal kernel accesses
1625 are unable to access userspace addresses. This can help prevent
1626 use-after-free bugs becoming an exploitable privilege escalation
1627 by ensuring that magic values (such as LIST_POISON) will always
1628 fault when dereferenced.
1630 CPUs with low-vector mappings use a best-efforts implementation.
1631 Their lower 1MB needs to remain accessible for the vectors, but
1632 the remainder of userspace will become appropriately inaccessible.
1634 config HW_PERF_EVENTS
1638 config SYS_SUPPORTS_HUGETLBFS
1642 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1646 config ARCH_WANT_GENERAL_HUGETLB
1649 config ARM_MODULE_PLTS
1650 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1653 Allocate PLTs when loading modules so that jumps and calls whose
1654 targets are too far away for their relative offsets to be encoded
1655 in the instructions themselves can be bounced via veneers in the
1656 module's PLT. This allows modules to be allocated in the generic
1657 vmalloc area after the dedicated module memory area has been
1658 exhausted. The modules will use slightly more memory, but after
1659 rounding up to page size, the actual memory footprint is usually
1662 Say y if you are getting out of memory errors while loading modules
1666 config FORCE_MAX_ZONEORDER
1667 int "Maximum zone order"
1668 default "12" if SOC_AM33XX
1669 default "9" if SA1111 || ARCH_EFM32
1672 The kernel memory allocator divides physically contiguous memory
1673 blocks into "zones", where each zone is a power of two number of
1674 pages. This option selects the largest power of two that the kernel
1675 keeps in the memory allocator. If you need to allocate very large
1676 blocks of physically contiguous memory, then you may need to
1677 increase this value.
1679 This config option is actually maximum order plus one. For example,
1680 a value of 11 means that the largest free memory block is 2^10 pages.
1682 config ALIGNMENT_TRAP
1684 depends on CPU_CP15_MMU
1685 default y if !ARCH_EBSA110
1686 select HAVE_PROC_CPU if PROC_FS
1688 ARM processors cannot fetch/store information which is not
1689 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1690 address divisible by 4. On 32-bit ARM processors, these non-aligned
1691 fetch/store instructions will be emulated in software if you say
1692 here, which has a severe performance impact. This is necessary for
1693 correct operation of some network protocols. With an IP-only
1694 configuration it is safe to say N, otherwise say Y.
1696 config UACCESS_WITH_MEMCPY
1697 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1699 default y if CPU_FEROCEON
1701 Implement faster copy_to_user and clear_user methods for CPU
1702 cores where a 8-word STM instruction give significantly higher
1703 memory write throughput than a sequence of individual 32bit stores.
1705 A possible side effect is a slight increase in scheduling latency
1706 between threads sharing the same address space if they invoke
1707 such copy operations with large buffers.
1709 However, if the CPU data cache is using a write-allocate mode,
1710 this option is unlikely to provide any performance gain.
1714 prompt "Enable seccomp to safely compute untrusted bytecode"
1716 This kernel feature is useful for number crunching applications
1717 that may need to compute untrusted bytecode during their
1718 execution. By using pipes or other transports made available to
1719 the process as file descriptors supporting the read/write
1720 syscalls, it's possible to isolate those applications in
1721 their own address space using seccomp. Once seccomp is
1722 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1723 and the task is only allowed to execute a few safe syscalls
1724 defined by each seccomp mode.
1733 bool "Enable paravirtualization code"
1735 This changes the kernel so it can modify itself when it is run
1736 under a hypervisor, potentially improving performance significantly
1737 over full virtualization.
1739 config PARAVIRT_TIME_ACCOUNTING
1740 bool "Paravirtual steal time accounting"
1744 Select this option to enable fine granularity task steal time
1745 accounting. Time spent executing other tasks in parallel with
1746 the current vCPU is discounted from the vCPU power. To account for
1747 that, there can be a small performance impact.
1749 If in doubt, say N here.
1756 bool "Xen guest support on ARM"
1757 depends on ARM && AEABI && OF
1758 depends on CPU_V7 && !CPU_V6
1759 depends on !GENERIC_ATOMIC64
1761 select ARCH_DMA_ADDR_T_64BIT
1766 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1773 bool "Flattened Device Tree support"
1777 Include support for flattened device tree machine descriptions.
1780 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1783 This is the traditional way of passing data to the kernel at boot
1784 time. If you are solely relying on the flattened device tree (or
1785 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1786 to remove ATAGS support from your kernel binary. If unsure,
1789 config DEPRECATED_PARAM_STRUCT
1790 bool "Provide old way to pass kernel parameters"
1793 This was deprecated in 2001 and announced to live on for 5 years.
1794 Some old boot loaders still use this way.
1796 # Compressed boot loader in ROM. Yes, we really want to ask about
1797 # TEXT and BSS so we preserve their values in the config files.
1798 config ZBOOT_ROM_TEXT
1799 hex "Compressed ROM boot loader base address"
1802 The physical address at which the ROM-able zImage is to be
1803 placed in the target. Platforms which normally make use of
1804 ROM-able zImage formats normally set this to a suitable
1805 value in their defconfig file.
1807 If ZBOOT_ROM is not enabled, this has no effect.
1809 config ZBOOT_ROM_BSS
1810 hex "Compressed ROM boot loader BSS address"
1813 The base address of an area of read/write memory in the target
1814 for the ROM-able zImage which must be available while the
1815 decompressor is running. It must be large enough to hold the
1816 entire decompressed kernel plus an additional 128 KiB.
1817 Platforms which normally make use of ROM-able zImage formats
1818 normally set this to a suitable value in their defconfig file.
1820 If ZBOOT_ROM is not enabled, this has no effect.
1823 bool "Compressed boot loader in ROM/flash"
1824 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1825 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1827 Say Y here if you intend to execute your compressed kernel image
1828 (zImage) directly from ROM or flash. If unsure, say N.
1830 config ARM_APPENDED_DTB
1831 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1834 With this option, the boot code will look for a device tree binary
1835 (DTB) appended to zImage
1836 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1838 This is meant as a backward compatibility convenience for those
1839 systems with a bootloader that can't be upgraded to accommodate
1840 the documented boot protocol using a device tree.
1842 Beware that there is very little in terms of protection against
1843 this option being confused by leftover garbage in memory that might
1844 look like a DTB header after a reboot if no actual DTB is appended
1845 to zImage. Do not leave this option active in a production kernel
1846 if you don't intend to always append a DTB. Proper passing of the
1847 location into r2 of a bootloader provided DTB is always preferable
1850 config ARM_ATAG_DTB_COMPAT
1851 bool "Supplement the appended DTB with traditional ATAG information"
1852 depends on ARM_APPENDED_DTB
1854 Some old bootloaders can't be updated to a DTB capable one, yet
1855 they provide ATAGs with memory configuration, the ramdisk address,
1856 the kernel cmdline string, etc. Such information is dynamically
1857 provided by the bootloader and can't always be stored in a static
1858 DTB. To allow a device tree enabled kernel to be used with such
1859 bootloaders, this option allows zImage to extract the information
1860 from the ATAG list and store it at run time into the appended DTB.
1863 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1864 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1866 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1867 bool "Use bootloader kernel arguments if available"
1869 Uses the command-line options passed by the boot loader instead of
1870 the device tree bootargs property. If the boot loader doesn't provide
1871 any, the device tree bootargs property will be used.
1873 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1874 bool "Extend with bootloader kernel arguments"
1876 The command-line arguments provided by the boot loader will be
1877 appended to the the device tree bootargs property.
1882 string "Default kernel command string"
1885 On some architectures (EBSA110 and CATS), there is currently no way
1886 for the boot loader to pass arguments to the kernel. For these
1887 architectures, you should supply some command-line options at build
1888 time by entering them here. As a minimum, you should specify the
1889 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1892 prompt "Kernel command line type" if CMDLINE != ""
1893 default CMDLINE_FROM_BOOTLOADER
1896 config CMDLINE_FROM_BOOTLOADER
1897 bool "Use bootloader kernel arguments if available"
1899 Uses the command-line options passed by the boot loader. If
1900 the boot loader doesn't provide any, the default kernel command
1901 string provided in CMDLINE will be used.
1903 config CMDLINE_EXTEND
1904 bool "Extend bootloader kernel arguments"
1906 The command-line arguments provided by the boot loader will be
1907 appended to the default kernel command string.
1909 config CMDLINE_FORCE
1910 bool "Always use the default kernel command string"
1912 Always use the default kernel command string, even if the boot
1913 loader passes other arguments to the kernel.
1914 This is useful if you cannot or don't want to change the
1915 command-line options your boot loader passes to the kernel.
1919 bool "Kernel Execute-In-Place from ROM"
1920 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1922 Execute-In-Place allows the kernel to run from non-volatile storage
1923 directly addressable by the CPU, such as NOR flash. This saves RAM
1924 space since the text section of the kernel is not loaded from flash
1925 to RAM. Read-write sections, such as the data section and stack,
1926 are still copied to RAM. The XIP kernel is not compressed since
1927 it has to run directly from flash, so it will take more space to
1928 store it. The flash address used to link the kernel object files,
1929 and for storing it, is configuration dependent. Therefore, if you
1930 say Y here, you must know the proper physical address where to
1931 store the kernel image depending on your own flash memory usage.
1933 Also note that the make target becomes "make xipImage" rather than
1934 "make zImage" or "make Image". The final kernel binary to put in
1935 ROM memory will be arch/arm/boot/xipImage.
1939 config XIP_PHYS_ADDR
1940 hex "XIP Kernel Physical Location"
1941 depends on XIP_KERNEL
1942 default "0x00080000"
1944 This is the physical address in your flash memory the kernel will
1945 be linked for and stored to. This address is dependent on your
1949 bool "Kexec system call (EXPERIMENTAL)"
1950 depends on (!SMP || PM_SLEEP_SMP)
1954 kexec is a system call that implements the ability to shutdown your
1955 current kernel, and to start another kernel. It is like a reboot
1956 but it is independent of the system firmware. And like a reboot
1957 you can start any kernel with it, not just Linux.
1959 It is an ongoing process to be certain the hardware in a machine
1960 is properly shutdown, so do not be surprised if this code does not
1961 initially work for you.
1964 bool "Export atags in procfs"
1965 depends on ATAGS && KEXEC
1968 Should the atags used to boot the kernel be exported in an "atags"
1969 file in procfs. Useful with kexec.
1972 bool "Build kdump crash kernel (EXPERIMENTAL)"
1974 Generate crash dump after being started by kexec. This should
1975 be normally only set in special crash dump kernels which are
1976 loaded in the main kernel with kexec-tools into a specially
1977 reserved region and then later executed after a crash by
1978 kdump/kexec. The crash dump kernel must be compiled to a
1979 memory address not used by the main kernel
1981 For more details see Documentation/kdump/kdump.txt
1983 config AUTO_ZRELADDR
1984 bool "Auto calculation of the decompressed kernel image address"
1986 ZRELADDR is the physical address where the decompressed kernel
1987 image will be placed. If AUTO_ZRELADDR is selected, the address
1988 will be determined at run-time by masking the current IP with
1989 0xf8000000. This assumes the zImage being placed in the first 128MB
1990 from start of memory.
1996 bool "UEFI runtime support"
1997 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1999 select EFI_PARAMS_FROM_FDT
2002 select EFI_RUNTIME_WRAPPERS
2004 This option provides support for runtime services provided
2005 by UEFI firmware (such as non-volatile variables, realtime
2006 clock, and platform reset). A UEFI stub is also provided to
2007 allow the kernel to be booted as an EFI application. This
2008 is only useful for kernels that may run on systems that have
2013 menu "CPU Power Management"
2015 source "drivers/cpufreq/Kconfig"
2017 source "drivers/cpuidle/Kconfig"
2021 menu "Floating point emulation"
2023 comment "At least one emulation must be selected"
2026 bool "NWFPE math emulation"
2027 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2029 Say Y to include the NWFPE floating point emulator in the kernel.
2030 This is necessary to run most binaries. Linux does not currently
2031 support floating point hardware so you need to say Y here even if
2032 your machine has an FPA or floating point co-processor podule.
2034 You may say N here if you are going to load the Acorn FPEmulator
2035 early in the bootup.
2038 bool "Support extended precision"
2039 depends on FPE_NWFPE
2041 Say Y to include 80-bit support in the kernel floating-point
2042 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2043 Note that gcc does not generate 80-bit operations by default,
2044 so in most cases this option only enlarges the size of the
2045 floating point emulator without any good reason.
2047 You almost surely want to say N here.
2050 bool "FastFPE math emulation (EXPERIMENTAL)"
2051 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2053 Say Y here to include the FAST floating point emulator in the kernel.
2054 This is an experimental much faster emulator which now also has full
2055 precision for the mantissa. It does not support any exceptions.
2056 It is very simple, and approximately 3-6 times faster than NWFPE.
2058 It should be sufficient for most programs. It may be not suitable
2059 for scientific calculations, but you have to check this for yourself.
2060 If you do not feel you need a faster FP emulation you should better
2064 bool "VFP-format floating point maths"
2065 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2067 Say Y to include VFP support code in the kernel. This is needed
2068 if your hardware includes a VFP unit.
2070 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2071 release notes and additional status information.
2073 Say N if your target does not have VFP hardware.
2081 bool "Advanced SIMD (NEON) Extension support"
2082 depends on VFPv3 && CPU_V7
2084 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2087 config KERNEL_MODE_NEON
2088 bool "Support for NEON in kernel mode"
2089 depends on NEON && AEABI
2091 Say Y to include support for NEON in kernel mode.
2095 menu "Userspace binary formats"
2097 source "fs/Kconfig.binfmt"
2101 menu "Power management options"
2103 source "kernel/power/Kconfig"
2105 config ARCH_SUSPEND_POSSIBLE
2106 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2107 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2110 config ARM_CPU_SUSPEND
2111 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2112 depends on ARCH_SUSPEND_POSSIBLE
2114 config ARCH_HIBERNATION_POSSIBLE
2117 default y if ARCH_SUSPEND_POSSIBLE
2121 source "net/Kconfig"
2123 source "drivers/Kconfig"
2125 source "drivers/firmware/Kconfig"
2129 source "arch/arm/Kconfig.debug"
2131 source "security/Kconfig"
2133 source "crypto/Kconfig"
2135 source "arch/arm/crypto/Kconfig"
2138 source "lib/Kconfig"
2140 source "arch/arm/kvm/Kconfig"