1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND
7 select ARCH_HAS_BINFMT_FLAT
8 select ARCH_HAS_CURRENT_STACK_POINTER
9 select ARCH_HAS_DEBUG_VIRTUAL if MMU
10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
11 select ARCH_HAS_ELF_RANDOMIZE
12 select ARCH_HAS_FORTIFY_SOURCE
13 select ARCH_HAS_KEEPINITRD
15 select ARCH_HAS_MEMBARRIER_SYNC_CORE
16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
18 select ARCH_HAS_SETUP_DMA_OPS
19 select ARCH_HAS_SET_MEMORY
21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
22 select ARCH_HAS_STRICT_MODULE_RWX if MMU
23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
24 select ARCH_HAS_SYNC_DMA_FOR_CPU
25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
27 select ARCH_HAVE_CUSTOM_GPIO_H
28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
29 select ARCH_HAS_GCOV_PROFILE_ALL
30 select ARCH_KEEP_MEMBLOCK
31 select ARCH_HAS_UBSAN_SANITIZE_ALL
32 select ARCH_MIGHT_HAVE_PC_PARPORT
33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
35 select ARCH_SUPPORTS_ATOMIC_RMW
36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
37 select ARCH_USE_BUILTIN_BSWAP
38 select ARCH_USE_CMPXCHG_LOCKREF
39 select ARCH_USE_MEMTEST
40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
41 select ARCH_WANT_GENERAL_HUGETLB
42 select ARCH_WANT_IPC_PARSE_VERSION
43 select ARCH_WANT_LD_ORPHAN_WARN
44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
45 select BUILDTIME_TABLE_SORT if MMU
46 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE)
47 select CLONE_BACKWARDS
48 select CPU_PM if SUSPEND || CPU_IDLE
49 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
50 select DMA_DECLARE_COHERENT
51 select DMA_GLOBAL_POOL if !MMU
53 select DMA_NONCOHERENT_MMAP if MMU
55 select EDAC_ATOMIC_SCRUB
56 select GENERIC_ALLOCATOR
57 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
58 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
59 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
60 select GENERIC_IRQ_IPI if SMP
61 select GENERIC_CPU_AUTOPROBE
62 select GENERIC_EARLY_IOREMAP
63 select GENERIC_IDLE_POLL_SETUP
64 select GENERIC_IRQ_MULTI_HANDLER
65 select GENERIC_IRQ_PROBE
66 select GENERIC_IRQ_SHOW
67 select GENERIC_IRQ_SHOW_LEVEL
68 select GENERIC_LIB_DEVMEM_IS_ALLOWED
69 select GENERIC_PCI_IOMAP
70 select GENERIC_SCHED_CLOCK
71 select GENERIC_SMP_IDLE_THREAD
72 select HARDIRQS_SW_RESEND
73 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
74 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
75 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
76 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL
77 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
78 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
79 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
80 select HAVE_ARCH_MMAP_RND_BITS if MMU
81 select HAVE_ARCH_PFN_VALID
82 select HAVE_ARCH_SECCOMP
83 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
84 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
85 select HAVE_ARCH_TRACEHOOK
86 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
87 select HAVE_ARM_SMCCC if CPU_V7
88 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
89 select HAVE_CONTEXT_TRACKING_USER
90 select HAVE_C_RECORDMCOUNT
91 select HAVE_BUILDTIME_MCOUNT_SORT
92 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
93 select HAVE_DMA_CONTIGUOUS if MMU
94 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
95 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
96 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
97 select HAVE_EXIT_THREAD
98 select HAVE_FAST_GUP if ARM_LPAE
99 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
100 select HAVE_FUNCTION_ERROR_INJECTION
101 select HAVE_FUNCTION_GRAPH_TRACER
102 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
103 select HAVE_GCC_PLUGINS
104 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
105 select HAVE_IRQ_TIME_ACCOUNTING
106 select HAVE_KERNEL_GZIP
107 select HAVE_KERNEL_LZ4
108 select HAVE_KERNEL_LZMA
109 select HAVE_KERNEL_LZO
110 select HAVE_KERNEL_XZ
111 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
112 select HAVE_KRETPROBES if HAVE_KPROBES
113 select HAVE_MOD_ARCH_SPECIFIC
115 select HAVE_OPTPROBES if !THUMB2_KERNEL
116 select HAVE_PCI if MMU
117 select HAVE_PERF_EVENTS
118 select HAVE_PERF_REGS
119 select HAVE_PERF_USER_STACK_DUMP
120 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
121 select HAVE_REGS_AND_STACK_ACCESS_API
123 select HAVE_STACKPROTECTOR
124 select HAVE_SYSCALL_TRACEPOINTS
126 select HAVE_VIRT_CPU_ACCOUNTING_GEN
127 select IRQ_FORCED_THREADING
128 select MODULES_USE_ELF_REL
129 select NEED_DMA_MAP_STATE
130 select OF_EARLY_FLATTREE if OF
132 select OLD_SIGSUSPEND3
133 select PCI_DOMAINS_GENERIC if PCI
134 select PCI_SYSCALL if PCI
135 select PERF_USE_VMALLOC
137 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC)
138 select SYS_SUPPORTS_APM_EMULATION
139 select THREAD_INFO_IN_TASK
140 select TIMER_OF if OF
141 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
142 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
143 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
144 # Above selects are sorted alphabetically; please add new ones
145 # according to that. Thanks.
147 The ARM series is a line of low-power-consumption RISC chip designs
148 licensed by ARM Ltd and targeted at embedded applications and
149 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
150 manufactured, but legacy ARM-based PC hardware remains popular in
151 Europe. There is an ARM Linux project with a web page at
152 <http://www.arm.linux.org.uk/>.
154 config ARM_HAS_GROUP_RELOCS
156 depends on !LD_IS_LLD || LLD_VERSION >= 140000
157 depends on !COMPILE_TEST
159 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group
160 relocations, which have been around for a long time, but were not
161 supported in LLD until version 14. The combined range is -/+ 256 MiB,
162 which is usually sufficient, but not for allyesconfig, so we disable
163 this feature when doing compile testing.
165 config ARM_DMA_USE_IOMMU
167 select NEED_SG_DMA_LENGTH
171 config ARM_DMA_IOMMU_ALIGNMENT
172 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
176 DMA mapping framework by default aligns all buffers to the smallest
177 PAGE_SIZE order which is greater than or equal to the requested buffer
178 size. This works well for buffers up to a few hundreds kilobytes, but
179 for larger buffers it just a waste of address space. Drivers which has
180 relatively small addressing window (like 64Mib) might run out of
181 virtual space with just a few allocations.
183 With this parameter you can specify the maximum PAGE_SIZE order for
184 DMA IOMMU buffers. Larger buffers will be aligned only to this
185 specified order. The order is expressed as a power of two multiplied
190 config SYS_SUPPORTS_APM_EMULATION
195 select GENERIC_ALLOCATOR
206 config STACKTRACE_SUPPORT
210 config LOCKDEP_SUPPORT
214 config ARCH_HAS_ILOG2_U32
217 config ARCH_HAS_ILOG2_U64
220 config ARCH_HAS_BANDGAP
223 config FIX_EARLYCON_MEM
226 config GENERIC_HWEIGHT
230 config GENERIC_CALIBRATE_DELAY
234 config ARCH_MAY_HAVE_PC_FDC
237 config ARCH_SUPPORTS_UPROBES
240 config GENERIC_ISA_DMA
249 config ARM_PATCH_PHYS_VIRT
250 bool "Patch physical to virtual translations at runtime" if EMBEDDED
254 Patch phys-to-virt and virt-to-phys translation functions at
255 boot and module load time according to the position of the
256 kernel in system memory.
258 This can only be used with non-XIP MMU kernels where the base
259 of physical memory is at a 2 MiB boundary.
261 Only disable this option if you know that you do not require
262 this feature (eg, building a kernel for a single machine) and
263 you need to shrink the kernel to the minimal size.
265 config NEED_MACH_IO_H
268 Select this when mach/io.h is required to provide special
269 definitions for this platform. The need for mach/io.h should
270 be avoided when possible.
272 config NEED_MACH_MEMORY_H
275 Select this when mach/memory.h is required to provide special
276 definitions for this platform. The need for mach/memory.h should
277 be avoided when possible.
280 hex "Physical address of main memory" if MMU
281 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR
282 default DRAM_BASE if !MMU
283 default 0x00000000 if ARCH_FOOTBRIDGE
284 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
285 default 0xa0000000 if ARCH_PXA
286 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
289 Please provide the physical address corresponding to the
290 location of main memory in your system.
296 config PGTABLE_LEVELS
298 default 3 if ARM_LPAE
304 bool "MMU-based Paged Memory Management Support"
307 Select if you want MMU-based virtualised addressing space
308 support by paged memory management. If unsure, say 'Y'.
310 config ARM_SINGLE_ARMV7M
316 config ARCH_MMAP_RND_BITS_MIN
319 config ARCH_MMAP_RND_BITS_MAX
320 default 14 if PAGE_OFFSET=0x40000000
321 default 15 if PAGE_OFFSET=0x80000000
324 config ARCH_MULTIPLATFORM
325 bool "Require kernel to be portable to multiple machines" if EXPERT
326 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
329 In general, all Arm machines can be supported in a single
330 kernel image, covering either Armv4/v5 or Armv6/v7.
332 However, some configuration options require hardcoding machine
333 specific physical addresses or enable errata workarounds that may
334 break other machines.
336 Selecting N here allows using those options, including
337 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y.
339 menu "Platform selection"
342 comment "CPU Core family selection"
345 bool "ARMv4 based platforms (FA526, StrongARM)"
346 depends on !ARCH_MULTI_V6_V7
347 # https://github.com/llvm/llvm-project/issues/50764
348 depends on !LD_IS_LLD || LLD_VERSION >= 160000
349 select ARCH_MULTI_V4_V5
350 select CPU_FA526 if !(CPU_SA110 || CPU_SA1100)
352 config ARCH_MULTI_V4T
353 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
354 depends on !ARCH_MULTI_V6_V7
355 # https://github.com/llvm/llvm-project/issues/50764
356 depends on !LD_IS_LLD || LLD_VERSION >= 160000
357 select ARCH_MULTI_V4_V5
358 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
359 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
360 CPU_ARM925T || CPU_ARM940T)
363 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
364 depends on !ARCH_MULTI_V6_V7
365 select ARCH_MULTI_V4_V5
366 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
367 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
368 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
370 config ARCH_MULTI_V4_V5
374 bool "ARMv6 based platforms (ARM11)"
375 select ARCH_MULTI_V6_V7
379 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
381 select ARCH_MULTI_V6_V7
385 config ARCH_MULTI_V6_V7
387 select MIGHT_HAVE_CACHE_L2X0
389 config ARCH_MULTI_CPU_AUTO
390 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
396 bool "Dummy Virtual Machine"
397 depends on ARCH_MULTI_V7
400 select ARM_GIC_V2M if PCI
402 select ARM_GIC_V3_ITS if PCI
404 select HAVE_ARM_ARCH_TIMER
407 bool "Airoha SoC Support"
408 depends on ARCH_MULTI_V7
413 select HAVE_ARM_ARCH_TIMER
415 Support for Airoha EN7523 SoCs
418 # This is sorted alphabetically by mach-* pathname. However, plat-*
419 # Kconfigs may be included either alphabetically (according to the
420 # plat- suffix) or along side the corresponding mach-* source.
422 source "arch/arm/mach-actions/Kconfig"
424 source "arch/arm/mach-alpine/Kconfig"
426 source "arch/arm/mach-artpec/Kconfig"
428 source "arch/arm/mach-asm9260/Kconfig"
430 source "arch/arm/mach-aspeed/Kconfig"
432 source "arch/arm/mach-at91/Kconfig"
434 source "arch/arm/mach-axxia/Kconfig"
436 source "arch/arm/mach-bcm/Kconfig"
438 source "arch/arm/mach-berlin/Kconfig"
440 source "arch/arm/mach-clps711x/Kconfig"
442 source "arch/arm/mach-davinci/Kconfig"
444 source "arch/arm/mach-digicolor/Kconfig"
446 source "arch/arm/mach-dove/Kconfig"
448 source "arch/arm/mach-ep93xx/Kconfig"
450 source "arch/arm/mach-exynos/Kconfig"
452 source "arch/arm/mach-footbridge/Kconfig"
454 source "arch/arm/mach-gemini/Kconfig"
456 source "arch/arm/mach-highbank/Kconfig"
458 source "arch/arm/mach-hisi/Kconfig"
460 source "arch/arm/mach-hpe/Kconfig"
462 source "arch/arm/mach-imx/Kconfig"
464 source "arch/arm/mach-ixp4xx/Kconfig"
466 source "arch/arm/mach-keystone/Kconfig"
468 source "arch/arm/mach-lpc32xx/Kconfig"
470 source "arch/arm/mach-mediatek/Kconfig"
472 source "arch/arm/mach-meson/Kconfig"
474 source "arch/arm/mach-milbeaut/Kconfig"
476 source "arch/arm/mach-mmp/Kconfig"
478 source "arch/arm/mach-moxart/Kconfig"
480 source "arch/arm/mach-mstar/Kconfig"
482 source "arch/arm/mach-mv78xx0/Kconfig"
484 source "arch/arm/mach-mvebu/Kconfig"
486 source "arch/arm/mach-mxs/Kconfig"
488 source "arch/arm/mach-nomadik/Kconfig"
490 source "arch/arm/mach-npcm/Kconfig"
492 source "arch/arm/mach-nspire/Kconfig"
494 source "arch/arm/mach-omap1/Kconfig"
496 source "arch/arm/mach-omap2/Kconfig"
498 source "arch/arm/mach-orion5x/Kconfig"
500 source "arch/arm/mach-pxa/Kconfig"
502 source "arch/arm/mach-qcom/Kconfig"
504 source "arch/arm/mach-rda/Kconfig"
506 source "arch/arm/mach-realtek/Kconfig"
508 source "arch/arm/mach-rpc/Kconfig"
510 source "arch/arm/mach-rockchip/Kconfig"
512 source "arch/arm/mach-s3c/Kconfig"
514 source "arch/arm/mach-s5pv210/Kconfig"
516 source "arch/arm/mach-sa1100/Kconfig"
518 source "arch/arm/mach-shmobile/Kconfig"
520 source "arch/arm/mach-socfpga/Kconfig"
522 source "arch/arm/mach-spear/Kconfig"
524 source "arch/arm/mach-sti/Kconfig"
526 source "arch/arm/mach-stm32/Kconfig"
528 source "arch/arm/mach-sunplus/Kconfig"
530 source "arch/arm/mach-sunxi/Kconfig"
532 source "arch/arm/mach-tegra/Kconfig"
534 source "arch/arm/mach-uniphier/Kconfig"
536 source "arch/arm/mach-ux500/Kconfig"
538 source "arch/arm/mach-versatile/Kconfig"
540 source "arch/arm/mach-vt8500/Kconfig"
542 source "arch/arm/mach-zynq/Kconfig"
544 # ARMv7-M architecture
546 bool "NXP LPC18xx/LPC43xx"
547 depends on ARM_SINGLE_ARMV7M
548 select ARCH_HAS_RESET_CONTROLLER
550 select CLKSRC_LPC32XX
553 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
554 high performance microcontrollers.
557 bool "ARM MPS2 platform"
558 depends on ARM_SINGLE_ARMV7M
562 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
563 with a range of available cores like Cortex-M3/M4/M7.
565 Please, note that depends which Application Note is used memory map
566 for the platform may vary, so adjustment of RAM base might be needed.
568 # Definitions to make life easier
575 select GENERIC_IRQ_CHIP
578 config PLAT_ORION_LEGACY
582 config PLAT_VERSATILE
585 source "arch/arm/mm/Kconfig"
588 bool "Enable iWMMXt support"
589 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
590 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
592 Enable support for iWMMXt context switching at run time if
593 running on a CPU that supports it.
596 source "arch/arm/Kconfig-nommu"
599 config PJ4B_ERRATA_4742
600 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
601 depends on CPU_PJ4B && MACH_ARMADA_370
604 When coming out of either a Wait for Interrupt (WFI) or a Wait for
605 Event (WFE) IDLE states, a specific timing sensitivity exists between
606 the retiring WFI/WFE instructions and the newly issued subsequent
607 instructions. This sensitivity can result in a CPU hang scenario.
609 The software must insert either a Data Synchronization Barrier (DSB)
610 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
613 config ARM_ERRATA_326103
614 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
617 Executing a SWP instruction to read-only memory does not set bit 11
618 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
619 treat the access as a read, preventing a COW from occurring and
620 causing the faulting task to livelock.
622 config ARM_ERRATA_411920
623 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
624 depends on CPU_V6 || CPU_V6K
626 Invalidation of the Instruction Cache operation can
627 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
628 It does not affect the MPCore. This option enables the ARM Ltd.
629 recommended workaround.
631 config ARM_ERRATA_430973
632 bool "ARM errata: Stale prediction on replaced interworking branch"
635 This option enables the workaround for the 430973 Cortex-A8
636 r1p* erratum. If a code sequence containing an ARM/Thumb
637 interworking branch is replaced with another code sequence at the
638 same virtual address, whether due to self-modifying code or virtual
639 to physical address re-mapping, Cortex-A8 does not recover from the
640 stale interworking branch prediction. This results in Cortex-A8
641 executing the new code sequence in the incorrect ARM or Thumb state.
642 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
643 and also flushes the branch target cache at every context switch.
644 Note that setting specific bits in the ACTLR register may not be
645 available in non-secure mode.
647 config ARM_ERRATA_458693
648 bool "ARM errata: Processor deadlock when a false hazard is created"
650 depends on !ARCH_MULTIPLATFORM
652 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
653 erratum. For very specific sequences of memory operations, it is
654 possible for a hazard condition intended for a cache line to instead
655 be incorrectly associated with a different cache line. This false
656 hazard might then cause a processor deadlock. The workaround enables
657 the L1 caching of the NEON accesses and disables the PLD instruction
658 in the ACTLR register. Note that setting specific bits in the ACTLR
659 register may not be available in non-secure mode and thus is not
660 available on a multiplatform kernel. This should be applied by the
663 config ARM_ERRATA_460075
664 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
666 depends on !ARCH_MULTIPLATFORM
668 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
669 erratum. Any asynchronous access to the L2 cache may encounter a
670 situation in which recent store transactions to the L2 cache are lost
671 and overwritten with stale memory contents from external memory. The
672 workaround disables the write-allocate mode for the L2 cache via the
673 ACTLR register. Note that setting specific bits in the ACTLR register
674 may not be available in non-secure mode and thus is not available on
675 a multiplatform kernel. This should be applied by the bootloader
678 config ARM_ERRATA_742230
679 bool "ARM errata: DMB operation may be faulty"
680 depends on CPU_V7 && SMP
681 depends on !ARCH_MULTIPLATFORM
683 This option enables the workaround for the 742230 Cortex-A9
684 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
685 between two write operations may not ensure the correct visibility
686 ordering of the two writes. This workaround sets a specific bit in
687 the diagnostic register of the Cortex-A9 which causes the DMB
688 instruction to behave as a DSB, ensuring the correct behaviour of
689 the two writes. Note that setting specific bits in the diagnostics
690 register may not be available in non-secure mode and thus is not
691 available on a multiplatform kernel. This should be applied by the
694 config ARM_ERRATA_742231
695 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
696 depends on CPU_V7 && SMP
697 depends on !ARCH_MULTIPLATFORM
699 This option enables the workaround for the 742231 Cortex-A9
700 (r2p0..r2p2) erratum. Under certain conditions, specific to the
701 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
702 accessing some data located in the same cache line, may get corrupted
703 data due to bad handling of the address hazard when the line gets
704 replaced from one of the CPUs at the same time as another CPU is
705 accessing it. This workaround sets specific bits in the diagnostic
706 register of the Cortex-A9 which reduces the linefill issuing
707 capabilities of the processor. Note that setting specific bits in the
708 diagnostics register may not be available in non-secure mode and thus
709 is not available on a multiplatform kernel. This should be applied by
710 the bootloader instead.
712 config ARM_ERRATA_643719
713 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
714 depends on CPU_V7 && SMP
717 This option enables the workaround for the 643719 Cortex-A9 (prior to
718 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
719 register returns zero when it should return one. The workaround
720 corrects this value, ensuring cache maintenance operations which use
721 it behave as intended and avoiding data corruption.
723 config ARM_ERRATA_720789
724 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
727 This option enables the workaround for the 720789 Cortex-A9 (prior to
728 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
729 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
730 As a consequence of this erratum, some TLB entries which should be
731 invalidated are not, resulting in an incoherency in the system page
732 tables. The workaround changes the TLB flushing routines to invalidate
733 entries regardless of the ASID.
735 config ARM_ERRATA_743622
736 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
738 depends on !ARCH_MULTIPLATFORM
740 This option enables the workaround for the 743622 Cortex-A9
741 (r2p*) erratum. Under very rare conditions, a faulty
742 optimisation in the Cortex-A9 Store Buffer may lead to data
743 corruption. This workaround sets a specific bit in the diagnostic
744 register of the Cortex-A9 which disables the Store Buffer
745 optimisation, preventing the defect from occurring. This has no
746 visible impact on the overall performance or power consumption of the
747 processor. Note that setting specific bits in the diagnostics register
748 may not be available in non-secure mode and thus is not available on a
749 multiplatform kernel. This should be applied by the bootloader instead.
751 config ARM_ERRATA_751472
752 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
754 depends on !ARCH_MULTIPLATFORM
756 This option enables the workaround for the 751472 Cortex-A9 (prior
757 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
758 completion of a following broadcasted operation if the second
759 operation is received by a CPU before the ICIALLUIS has completed,
760 potentially leading to corrupted entries in the cache or TLB.
761 Note that setting specific bits in the diagnostics register may
762 not be available in non-secure mode and thus is not available on
763 a multiplatform kernel. This should be applied by the bootloader
766 config ARM_ERRATA_754322
767 bool "ARM errata: possible faulty MMU translations following an ASID switch"
770 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
771 r3p*) erratum. A speculative memory access may cause a page table walk
772 which starts prior to an ASID switch but completes afterwards. This
773 can populate the micro-TLB with a stale entry which may be hit with
774 the new ASID. This workaround places two dsb instructions in the mm
775 switching code so that no page table walks can cross the ASID switch.
777 config ARM_ERRATA_754327
778 bool "ARM errata: no automatic Store Buffer drain"
779 depends on CPU_V7 && SMP
781 This option enables the workaround for the 754327 Cortex-A9 (prior to
782 r2p0) erratum. The Store Buffer does not have any automatic draining
783 mechanism and therefore a livelock may occur if an external agent
784 continuously polls a memory location waiting to observe an update.
785 This workaround defines cpu_relax() as smp_mb(), preventing correctly
786 written polling loops from denying visibility of updates to memory.
788 config ARM_ERRATA_364296
789 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
792 This options enables the workaround for the 364296 ARM1136
793 r0p2 erratum (possible cache data corruption with
794 hit-under-miss enabled). It sets the undocumented bit 31 in
795 the auxiliary control register and the FI bit in the control
796 register, thus disabling hit-under-miss without putting the
797 processor into full low interrupt latency mode. ARM11MPCore
800 config ARM_ERRATA_764369
801 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
802 depends on CPU_V7 && SMP
804 This option enables the workaround for erratum 764369
805 affecting Cortex-A9 MPCore with two or more processors (all
806 current revisions). Under certain timing circumstances, a data
807 cache line maintenance operation by MVA targeting an Inner
808 Shareable memory region may fail to proceed up to either the
809 Point of Coherency or to the Point of Unification of the
810 system. This workaround adds a DSB instruction before the
811 relevant cache maintenance functions and sets a specific bit
812 in the diagnostic control register of the SCU.
814 config ARM_ERRATA_764319
815 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"
818 This option enables the workaround for the 764319 Cortex A-9 erratum.
819 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an
820 unexpected Undefined Instruction exception when the DBGSWENABLE
821 external pin is set to 0, even when the CP14 accesses are performed
822 from a privileged mode. This work around catches the exception in a
823 way the kernel does not stop execution.
825 config ARM_ERRATA_775420
826 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
829 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
830 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
831 operation aborts with MMU exception, it might cause the processor
832 to deadlock. This workaround puts DSB before executing ISB if
833 an abort may occur on cache maintenance.
835 config ARM_ERRATA_798181
836 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
837 depends on CPU_V7 && SMP
839 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
840 adequately shooting down all use of the old entries. This
841 option enables the Linux kernel workaround for this erratum
842 which sends an IPI to the CPUs that are running the same ASID
843 as the one being invalidated.
845 config ARM_ERRATA_773022
846 bool "ARM errata: incorrect instructions may be executed from loop buffer"
849 This option enables the workaround for the 773022 Cortex-A15
850 (up to r0p4) erratum. In certain rare sequences of code, the
851 loop buffer may deliver incorrect instructions. This
852 workaround disables the loop buffer to avoid the erratum.
854 config ARM_ERRATA_818325_852422
855 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
858 This option enables the workaround for:
859 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
860 instruction might deadlock. Fixed in r0p1.
861 - Cortex-A12 852422: Execution of a sequence of instructions might
862 lead to either a data corruption or a CPU deadlock. Not fixed in
863 any Cortex-A12 cores yet.
864 This workaround for all both errata involves setting bit[12] of the
865 Feature Register. This bit disables an optimisation applied to a
866 sequence of 2 instructions that use opposing condition codes.
868 config ARM_ERRATA_821420
869 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
872 This option enables the workaround for the 821420 Cortex-A12
873 (all revs) erratum. In very rare timing conditions, a sequence
874 of VMOV to Core registers instructions, for which the second
875 one is in the shadow of a branch or abort, can lead to a
876 deadlock when the VMOV instructions are issued out-of-order.
878 config ARM_ERRATA_825619
879 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
882 This option enables the workaround for the 825619 Cortex-A12
883 (all revs) erratum. Within rare timing constraints, executing a
884 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
885 and Device/Strongly-Ordered loads and stores might cause deadlock
887 config ARM_ERRATA_857271
888 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
891 This option enables the workaround for the 857271 Cortex-A12
892 (all revs) erratum. Under very rare timing conditions, the CPU might
893 hang. The workaround is expected to have a < 1% performance impact.
895 config ARM_ERRATA_852421
896 bool "ARM errata: A17: DMB ST might fail to create order between stores"
899 This option enables the workaround for the 852421 Cortex-A17
900 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
901 execution of a DMB ST instruction might fail to properly order
902 stores from GroupA and stores from GroupB.
904 config ARM_ERRATA_852423
905 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
908 This option enables the workaround for:
909 - Cortex-A17 852423: Execution of a sequence of instructions might
910 lead to either a data corruption or a CPU deadlock. Not fixed in
911 any Cortex-A17 cores yet.
912 This is identical to Cortex-A12 erratum 852422. It is a separate
913 config option from the A12 erratum due to the way errata are checked
916 config ARM_ERRATA_857272
917 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
920 This option enables the workaround for the 857272 Cortex-A17 erratum.
921 This erratum is not known to be fixed in any A17 revision.
922 This is identical to Cortex-A12 erratum 857271. It is a separate
923 config option from the A12 erratum due to the way errata are checked
928 source "arch/arm/common/Kconfig"
935 Find out whether you have ISA slots on your motherboard. ISA is the
936 name of a bus system, i.e. the way the CPU talks to the other stuff
937 inside your box. Other bus systems are PCI, EISA, MicroChannel
938 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
939 newer boards don't support it. If you have ISA, say Y, otherwise N.
941 # Select ISA DMA interface
945 config ARM_ERRATA_814220
946 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
949 The v7 ARM states that all cache and branch predictor maintenance
950 operations that do not specify an address execute, relative to
951 each other, in program order.
952 However, because of this erratum, an L2 set/way cache maintenance
953 operation can overtake an L1 set/way cache maintenance operation.
954 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
959 menu "Kernel Features"
964 This option should be selected by machines which have an SMP-
967 The only effect of this option is to make the SMP-related
968 options available to the user for configuration.
971 bool "Symmetric Multi-Processing"
972 depends on CPU_V6K || CPU_V7
974 depends on MMU || ARM_MPU
977 This enables support for systems with more than one CPU. If you have
978 a system with only one CPU, say N. If you have a system with more
981 If you say N here, the kernel will run on uni- and multiprocessor
982 machines, but will use only one CPU of a multiprocessor machine. If
983 you say Y here, the kernel will run on many, but not all,
984 uniprocessor machines. On a uniprocessor machine, the kernel
985 will run faster if you say N here.
987 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
988 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
989 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
991 If you don't know what to do here, say N.
994 bool "Allow booting SMP kernel on uniprocessor systems"
995 depends on SMP && MMU
998 SMP kernels contain instructions which fail on non-SMP processors.
999 Enabling this option allows the kernel to modify itself to make
1000 these instructions safe. Disabling it allows about 1K of space
1003 If you don't know what to do here, say Y.
1006 config CURRENT_POINTER_IN_TPIDRURO
1008 depends on CPU_32v6K && !CPU_V6
1012 select HAVE_IRQ_EXIT_ON_IRQ_STACK
1013 select HAVE_SOFTIRQ_ON_OWN_STACK
1015 config ARM_CPU_TOPOLOGY
1016 bool "Support cpu topology definition"
1017 depends on SMP && CPU_V7
1020 Support ARM cpu topology definition. The MPIDR register defines
1021 affinity between processors which is then used to describe the cpu
1022 topology of an ARM System.
1025 bool "Multi-core scheduler support"
1026 depends on ARM_CPU_TOPOLOGY
1028 Multi-core scheduler support improves the CPU scheduler's decision
1029 making when dealing with multi-core CPU chips at a cost of slightly
1030 increased overhead in some places. If unsure say N here.
1033 bool "SMT scheduler support"
1034 depends on ARM_CPU_TOPOLOGY
1036 Improves the CPU scheduler's decision making when dealing with
1037 MultiThreading at a cost of slightly increased overhead in some
1038 places. If unsure say N here.
1043 This option enables support for the ARM snoop control unit
1045 config HAVE_ARM_ARCH_TIMER
1046 bool "Architected timer support"
1048 select ARM_ARCH_TIMER
1050 This option enables support for the ARM architected timer
1055 This options enables support for the ARM timer and watchdog unit
1058 bool "Multi-Cluster Power Management"
1059 depends on CPU_V7 && SMP
1061 This option provides the common power management infrastructure
1062 for (multi-)cluster based systems, such as big.LITTLE based
1065 config MCPM_QUAD_CLUSTER
1069 To avoid wasting resources unnecessarily, MCPM only supports up
1070 to 2 clusters by default.
1071 Platforms with 3 or 4 clusters that use MCPM must select this
1072 option to allow the additional clusters to be managed.
1075 bool "big.LITTLE support (Experimental)"
1076 depends on CPU_V7 && SMP
1079 This option enables support selections for the big.LITTLE
1080 system architecture.
1083 bool "big.LITTLE switcher support"
1084 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1087 The big.LITTLE "switcher" provides the core functionality to
1088 transparently handle transition between a cluster of A15's
1089 and a cluster of A7's in a big.LITTLE system.
1091 config BL_SWITCHER_DUMMY_IF
1092 tristate "Simple big.LITTLE switcher user interface"
1093 depends on BL_SWITCHER && DEBUG_KERNEL
1095 This is a simple and dummy char dev interface to control
1096 the big.LITTLE switcher core code. It is meant for
1097 debugging purposes only.
1100 prompt "Memory split"
1104 Select the desired split between kernel and user memory.
1106 If you are not absolutely sure what you are doing, leave this
1110 bool "3G/1G user/kernel split"
1111 config VMSPLIT_3G_OPT
1112 depends on !ARM_LPAE
1113 bool "3G/1G user/kernel split (for full 1G low memory)"
1115 bool "2G/2G user/kernel split"
1117 bool "1G/3G user/kernel split"
1122 default PHYS_OFFSET if !MMU
1123 default 0x40000000 if VMSPLIT_1G
1124 default 0x80000000 if VMSPLIT_2G
1125 default 0xB0000000 if VMSPLIT_3G_OPT
1128 config KASAN_SHADOW_OFFSET
1131 default 0x1f000000 if PAGE_OFFSET=0x40000000
1132 default 0x5f000000 if PAGE_OFFSET=0x80000000
1133 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1134 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1138 int "Maximum number of CPUs (2-32)"
1139 range 2 16 if DEBUG_KMAP_LOCAL
1140 range 2 32 if !DEBUG_KMAP_LOCAL
1144 The maximum number of CPUs that the kernel can support.
1145 Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1146 debugging is enabled, which uses half of the per-CPU fixmap
1147 slots as guard regions.
1150 bool "Support for hot-pluggable CPUs"
1152 select GENERIC_IRQ_MIGRATION
1154 Say Y here to experiment with turning CPUs off and on. CPUs
1155 can be controlled through /sys/devices/system/cpu.
1158 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1159 depends on HAVE_ARM_SMCCC
1162 Say Y here if you want Linux to communicate with system firmware
1163 implementing the PSCI specification for CPU-centric power
1164 management operations described in ARM document number ARM DEN
1165 0022A ("Power State Coordination Interface System Software on
1170 default 128 if SOC_AT91RM9200
1174 depends on HZ_FIXED = 0
1175 prompt "Timer frequency"
1199 default HZ_FIXED if HZ_FIXED != 0
1200 default 100 if HZ_100
1201 default 200 if HZ_200
1202 default 250 if HZ_250
1203 default 300 if HZ_300
1204 default 500 if HZ_500
1208 def_bool HIGH_RES_TIMERS
1210 config THUMB2_KERNEL
1211 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1212 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1213 default y if CPU_THUMBONLY
1216 By enabling this option, the kernel will be compiled in
1221 config ARM_PATCH_IDIV
1222 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1226 The ARM compiler inserts calls to __aeabi_idiv() and
1227 __aeabi_uidiv() when it needs to perform division on signed
1228 and unsigned integers. Some v7 CPUs have support for the sdiv
1229 and udiv instructions that can be used to implement those
1232 Enabling this option allows the kernel to modify itself to
1233 replace the first two instructions of these library functions
1234 with the sdiv or udiv plus "bx lr" instructions when the CPU
1235 it is running on supports them. Typically this will be faster
1236 and less power intensive than running the original library
1237 code to do integer division.
1240 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1241 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1242 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1244 This option allows for the kernel to be compiled using the latest
1245 ARM ABI (aka EABI). This is only useful if you are using a user
1246 space environment that is also compiled with EABI.
1248 Since there are major incompatibilities between the legacy ABI and
1249 EABI, especially with regard to structure member alignment, this
1250 option also changes the kernel syscall calling convention to
1251 disambiguate both ABIs and allow for backward compatibility support
1252 (selected with CONFIG_OABI_COMPAT).
1254 To use this you need GCC version 4.0.0 or later.
1257 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1258 depends on AEABI && !THUMB2_KERNEL
1260 This option preserves the old syscall interface along with the
1261 new (ARM EABI) one. It also provides a compatibility layer to
1262 intercept syscalls that have structure arguments which layout
1263 in memory differs between the legacy ABI and the new ARM EABI
1264 (only for non "thumb" binaries). This option adds a tiny
1265 overhead to all syscalls and produces a slightly larger kernel.
1267 The seccomp filter system will not be available when this is
1268 selected, since there is no way yet to sensibly distinguish
1269 between calling conventions during filtering.
1271 If you know you'll be using only pure EABI user space then you
1272 can say N here. If this option is not selected and you attempt
1273 to execute a legacy ABI binary then the result will be
1274 UNPREDICTABLE (in fact it can be predicted that it won't work
1275 at all). If in doubt say N.
1277 config ARCH_SELECT_MEMORY_MODEL
1280 config ARCH_FLATMEM_ENABLE
1281 def_bool !(ARCH_RPC || ARCH_SA1100)
1283 config ARCH_SPARSEMEM_ENABLE
1284 def_bool !ARCH_FOOTBRIDGE
1285 select SPARSEMEM_STATIC if SPARSEMEM
1288 bool "High Memory Support"
1291 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY
1293 The address space of ARM processors is only 4 Gigabytes large
1294 and it has to accommodate user address space, kernel address
1295 space as well as some memory mapped IO. That means that, if you
1296 have a large amount of physical memory and/or IO, not all of the
1297 memory can be "permanently mapped" by the kernel. The physical
1298 memory that is not permanently mapped is called "high memory".
1300 Depending on the selected kernel/user memory split, minimum
1301 vmalloc space and actual amount of RAM, you may not need this
1302 option which should result in a slightly faster kernel.
1307 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1311 The VM uses one page of physical memory for each page table.
1312 For systems with a lot of processes, this can use a lot of
1313 precious low memory, eventually leading to low memory being
1314 consumed by page tables. Setting this option will allow
1315 user-space 2nd level page tables to reside in high memory.
1317 config CPU_SW_DOMAIN_PAN
1318 bool "Enable use of CPU domains to implement privileged no-access"
1319 depends on MMU && !ARM_LPAE
1322 Increase kernel security by ensuring that normal kernel accesses
1323 are unable to access userspace addresses. This can help prevent
1324 use-after-free bugs becoming an exploitable privilege escalation
1325 by ensuring that magic values (such as LIST_POISON) will always
1326 fault when dereferenced.
1328 CPUs with low-vector mappings use a best-efforts implementation.
1329 Their lower 1MB needs to remain accessible for the vectors, but
1330 the remainder of userspace will become appropriately inaccessible.
1332 config HW_PERF_EVENTS
1336 config ARM_MODULE_PLTS
1337 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1339 select KASAN_VMALLOC if KASAN
1342 Allocate PLTs when loading modules so that jumps and calls whose
1343 targets are too far away for their relative offsets to be encoded
1344 in the instructions themselves can be bounced via veneers in the
1345 module's PLT. This allows modules to be allocated in the generic
1346 vmalloc area after the dedicated module memory area has been
1347 exhausted. The modules will use slightly more memory, but after
1348 rounding up to page size, the actual memory footprint is usually
1351 Disabling this is usually safe for small single-platform
1352 configurations. If unsure, say y.
1354 config ARCH_FORCE_MAX_ORDER
1355 int "Maximum zone order"
1356 default "12" if SOC_AM33XX
1357 default "9" if SA1111
1360 The kernel memory allocator divides physically contiguous memory
1361 blocks into "zones", where each zone is a power of two number of
1362 pages. This option selects the largest power of two that the kernel
1363 keeps in the memory allocator. If you need to allocate very large
1364 blocks of physically contiguous memory, then you may need to
1365 increase this value.
1367 This config option is actually maximum order plus one. For example,
1368 a value of 11 means that the largest free memory block is 2^10 pages.
1370 config ALIGNMENT_TRAP
1371 def_bool CPU_CP15_MMU
1372 select HAVE_PROC_CPU if PROC_FS
1374 ARM processors cannot fetch/store information which is not
1375 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1376 address divisible by 4. On 32-bit ARM processors, these non-aligned
1377 fetch/store instructions will be emulated in software if you say
1378 here, which has a severe performance impact. This is necessary for
1379 correct operation of some network protocols. With an IP-only
1380 configuration it is safe to say N, otherwise say Y.
1382 config UACCESS_WITH_MEMCPY
1383 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1385 default y if CPU_FEROCEON
1387 Implement faster copy_to_user and clear_user methods for CPU
1388 cores where a 8-word STM instruction give significantly higher
1389 memory write throughput than a sequence of individual 32bit stores.
1391 A possible side effect is a slight increase in scheduling latency
1392 between threads sharing the same address space if they invoke
1393 such copy operations with large buffers.
1395 However, if the CPU data cache is using a write-allocate mode,
1396 this option is unlikely to provide any performance gain.
1399 bool "Enable paravirtualization code"
1401 This changes the kernel so it can modify itself when it is run
1402 under a hypervisor, potentially improving performance significantly
1403 over full virtualization.
1405 config PARAVIRT_TIME_ACCOUNTING
1406 bool "Paravirtual steal time accounting"
1409 Select this option to enable fine granularity task steal time
1410 accounting. Time spent executing other tasks in parallel with
1411 the current vCPU is discounted from the vCPU power. To account for
1412 that, there can be a small performance impact.
1414 If in doubt, say N here.
1421 bool "Xen guest support on ARM"
1422 depends on ARM && AEABI && OF
1423 depends on CPU_V7 && !CPU_V6
1424 depends on !GENERIC_ATOMIC64
1426 select ARCH_DMA_ADDR_T_64BIT
1432 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1434 config CC_HAVE_STACKPROTECTOR_TLS
1435 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1437 config STACKPROTECTOR_PER_TASK
1438 bool "Use a unique stack canary value for each task"
1439 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA
1440 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS
1441 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS
1444 Due to the fact that GCC uses an ordinary symbol reference from
1445 which to load the value of the stack canary, this value can only
1446 change at reboot time on SMP systems, and all tasks running in the
1447 kernel's address space are forced to use the same canary value for
1448 the entire duration that the system is up.
1450 Enable this option to switch to a different method that uses a
1451 different canary value for each task.
1458 bool "Flattened Device Tree support"
1462 Include support for flattened device tree machine descriptions.
1465 bool "Support for the traditional ATAGS boot data passing"
1468 This is the traditional way of passing data to the kernel at boot
1469 time. If you are solely relying on the flattened device tree (or
1470 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1471 to remove ATAGS support from your kernel binary.
1473 config DEPRECATED_PARAM_STRUCT
1474 bool "Provide old way to pass kernel parameters"
1477 This was deprecated in 2001 and announced to live on for 5 years.
1478 Some old boot loaders still use this way.
1480 # Compressed boot loader in ROM. Yes, we really want to ask about
1481 # TEXT and BSS so we preserve their values in the config files.
1482 config ZBOOT_ROM_TEXT
1483 hex "Compressed ROM boot loader base address"
1486 The physical address at which the ROM-able zImage is to be
1487 placed in the target. Platforms which normally make use of
1488 ROM-able zImage formats normally set this to a suitable
1489 value in their defconfig file.
1491 If ZBOOT_ROM is not enabled, this has no effect.
1493 config ZBOOT_ROM_BSS
1494 hex "Compressed ROM boot loader BSS address"
1497 The base address of an area of read/write memory in the target
1498 for the ROM-able zImage which must be available while the
1499 decompressor is running. It must be large enough to hold the
1500 entire decompressed kernel plus an additional 128 KiB.
1501 Platforms which normally make use of ROM-able zImage formats
1502 normally set this to a suitable value in their defconfig file.
1504 If ZBOOT_ROM is not enabled, this has no effect.
1507 bool "Compressed boot loader in ROM/flash"
1508 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1509 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1511 Say Y here if you intend to execute your compressed kernel image
1512 (zImage) directly from ROM or flash. If unsure, say N.
1514 config ARM_APPENDED_DTB
1515 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1518 With this option, the boot code will look for a device tree binary
1519 (DTB) appended to zImage
1520 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1522 This is meant as a backward compatibility convenience for those
1523 systems with a bootloader that can't be upgraded to accommodate
1524 the documented boot protocol using a device tree.
1526 Beware that there is very little in terms of protection against
1527 this option being confused by leftover garbage in memory that might
1528 look like a DTB header after a reboot if no actual DTB is appended
1529 to zImage. Do not leave this option active in a production kernel
1530 if you don't intend to always append a DTB. Proper passing of the
1531 location into r2 of a bootloader provided DTB is always preferable
1534 config ARM_ATAG_DTB_COMPAT
1535 bool "Supplement the appended DTB with traditional ATAG information"
1536 depends on ARM_APPENDED_DTB
1538 Some old bootloaders can't be updated to a DTB capable one, yet
1539 they provide ATAGs with memory configuration, the ramdisk address,
1540 the kernel cmdline string, etc. Such information is dynamically
1541 provided by the bootloader and can't always be stored in a static
1542 DTB. To allow a device tree enabled kernel to be used with such
1543 bootloaders, this option allows zImage to extract the information
1544 from the ATAG list and store it at run time into the appended DTB.
1547 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1548 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1550 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1551 bool "Use bootloader kernel arguments if available"
1553 Uses the command-line options passed by the boot loader instead of
1554 the device tree bootargs property. If the boot loader doesn't provide
1555 any, the device tree bootargs property will be used.
1557 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1558 bool "Extend with bootloader kernel arguments"
1560 The command-line arguments provided by the boot loader will be
1561 appended to the the device tree bootargs property.
1566 string "Default kernel command string"
1569 On some architectures (e.g. CATS), there is currently no way
1570 for the boot loader to pass arguments to the kernel. For these
1571 architectures, you should supply some command-line options at build
1572 time by entering them here. As a minimum, you should specify the
1573 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1576 prompt "Kernel command line type" if CMDLINE != ""
1577 default CMDLINE_FROM_BOOTLOADER
1579 config CMDLINE_FROM_BOOTLOADER
1580 bool "Use bootloader kernel arguments if available"
1582 Uses the command-line options passed by the boot loader. If
1583 the boot loader doesn't provide any, the default kernel command
1584 string provided in CMDLINE will be used.
1586 config CMDLINE_EXTEND
1587 bool "Extend bootloader kernel arguments"
1589 The command-line arguments provided by the boot loader will be
1590 appended to the default kernel command string.
1592 config CMDLINE_FORCE
1593 bool "Always use the default kernel command string"
1595 Always use the default kernel command string, even if the boot
1596 loader passes other arguments to the kernel.
1597 This is useful if you cannot or don't want to change the
1598 command-line options your boot loader passes to the kernel.
1602 bool "Kernel Execute-In-Place from ROM"
1603 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1604 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP
1606 Execute-In-Place allows the kernel to run from non-volatile storage
1607 directly addressable by the CPU, such as NOR flash. This saves RAM
1608 space since the text section of the kernel is not loaded from flash
1609 to RAM. Read-write sections, such as the data section and stack,
1610 are still copied to RAM. The XIP kernel is not compressed since
1611 it has to run directly from flash, so it will take more space to
1612 store it. The flash address used to link the kernel object files,
1613 and for storing it, is configuration dependent. Therefore, if you
1614 say Y here, you must know the proper physical address where to
1615 store the kernel image depending on your own flash memory usage.
1617 Also note that the make target becomes "make xipImage" rather than
1618 "make zImage" or "make Image". The final kernel binary to put in
1619 ROM memory will be arch/arm/boot/xipImage.
1623 config XIP_PHYS_ADDR
1624 hex "XIP Kernel Physical Location"
1625 depends on XIP_KERNEL
1626 default "0x00080000"
1628 This is the physical address in your flash memory the kernel will
1629 be linked for and stored to. This address is dependent on your
1632 config XIP_DEFLATED_DATA
1633 bool "Store kernel .data section compressed in ROM"
1634 depends on XIP_KERNEL
1637 Before the kernel is actually executed, its .data section has to be
1638 copied to RAM from ROM. This option allows for storing that data
1639 in compressed form and decompressed to RAM rather than merely being
1640 copied, saving some precious ROM space. A possible drawback is a
1641 slightly longer boot delay.
1644 bool "Kexec system call (EXPERIMENTAL)"
1645 depends on (!SMP || PM_SLEEP_SMP)
1649 kexec is a system call that implements the ability to shutdown your
1650 current kernel, and to start another kernel. It is like a reboot
1651 but it is independent of the system firmware. And like a reboot
1652 you can start any kernel with it, not just Linux.
1654 It is an ongoing process to be certain the hardware in a machine
1655 is properly shutdown, so do not be surprised if this code does not
1656 initially work for you.
1659 bool "Export atags in procfs"
1660 depends on ATAGS && KEXEC
1663 Should the atags used to boot the kernel be exported in an "atags"
1664 file in procfs. Useful with kexec.
1667 bool "Build kdump crash kernel (EXPERIMENTAL)"
1669 Generate crash dump after being started by kexec. This should
1670 be normally only set in special crash dump kernels which are
1671 loaded in the main kernel with kexec-tools into a specially
1672 reserved region and then later executed after a crash by
1673 kdump/kexec. The crash dump kernel must be compiled to a
1674 memory address not used by the main kernel
1676 For more details see Documentation/admin-guide/kdump/kdump.rst
1678 config AUTO_ZRELADDR
1679 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM
1680 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
1682 ZRELADDR is the physical address where the decompressed kernel
1683 image will be placed. If AUTO_ZRELADDR is selected, the address
1684 will be determined at run-time, either by masking the current IP
1685 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1686 This assumes the zImage being placed in the first 128MB from
1693 bool "UEFI runtime support"
1694 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1696 select EFI_PARAMS_FROM_FDT
1698 select EFI_GENERIC_STUB
1699 select EFI_RUNTIME_WRAPPERS
1701 This option provides support for runtime services provided
1702 by UEFI firmware (such as non-volatile variables, realtime
1703 clock, and platform reset). A UEFI stub is also provided to
1704 allow the kernel to be booted as an EFI application. This
1705 is only useful for kernels that may run on systems that have
1709 bool "Enable support for SMBIOS (DMI) tables"
1713 This enables SMBIOS/DMI feature for systems.
1715 This option is only useful on systems that have UEFI firmware.
1716 However, even with this option, the resultant kernel should
1717 continue to boot on existing non-UEFI platforms.
1719 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1720 i.e., the the practice of identifying the platform via DMI to
1721 decide whether certain workarounds for buggy hardware and/or
1722 firmware need to be enabled. This would require the DMI subsystem
1723 to be enabled much earlier than we do on ARM, which is non-trivial.
1727 menu "CPU Power Management"
1729 source "drivers/cpufreq/Kconfig"
1731 source "drivers/cpuidle/Kconfig"
1735 menu "Floating point emulation"
1737 comment "At least one emulation must be selected"
1740 bool "NWFPE math emulation"
1741 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1743 Say Y to include the NWFPE floating point emulator in the kernel.
1744 This is necessary to run most binaries. Linux does not currently
1745 support floating point hardware so you need to say Y here even if
1746 your machine has an FPA or floating point co-processor podule.
1748 You may say N here if you are going to load the Acorn FPEmulator
1749 early in the bootup.
1752 bool "Support extended precision"
1753 depends on FPE_NWFPE
1755 Say Y to include 80-bit support in the kernel floating-point
1756 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1757 Note that gcc does not generate 80-bit operations by default,
1758 so in most cases this option only enlarges the size of the
1759 floating point emulator without any good reason.
1761 You almost surely want to say N here.
1764 bool "FastFPE math emulation (EXPERIMENTAL)"
1765 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1767 Say Y here to include the FAST floating point emulator in the kernel.
1768 This is an experimental much faster emulator which now also has full
1769 precision for the mantissa. It does not support any exceptions.
1770 It is very simple, and approximately 3-6 times faster than NWFPE.
1772 It should be sufficient for most programs. It may be not suitable
1773 for scientific calculations, but you have to check this for yourself.
1774 If you do not feel you need a faster FP emulation you should better
1778 bool "VFP-format floating point maths"
1779 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1781 Say Y to include VFP support code in the kernel. This is needed
1782 if your hardware includes a VFP unit.
1784 Please see <file:Documentation/arm/vfp/release-notes.rst> for
1785 release notes and additional status information.
1787 Say N if your target does not have VFP hardware.
1795 bool "Advanced SIMD (NEON) Extension support"
1796 depends on VFPv3 && CPU_V7
1798 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1801 config KERNEL_MODE_NEON
1802 bool "Support for NEON in kernel mode"
1803 depends on NEON && AEABI
1805 Say Y to include support for NEON in kernel mode.
1809 menu "Power management options"
1811 source "kernel/power/Kconfig"
1813 config ARCH_SUSPEND_POSSIBLE
1814 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1815 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
1818 config ARM_CPU_SUSPEND
1819 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1820 depends on ARCH_SUSPEND_POSSIBLE
1822 config ARCH_HIBERNATION_POSSIBLE
1825 default y if ARCH_SUSPEND_POSSIBLE
1829 source "arch/arm/Kconfig.assembler"