4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_USE_BUILTIN_BSWAP
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_WANT_IPC_PARSE_VERSION
13 select BUILDTIME_EXTABLE_SORT if MMU
14 select CLONE_BACKWARDS
15 select CPU_PM if (SUSPEND || CPU_IDLE)
16 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
17 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
18 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
19 select GENERIC_IDLE_POLL_SETUP
20 select GENERIC_IRQ_PROBE
21 select GENERIC_IRQ_SHOW
22 select GENERIC_PCI_IOMAP
23 select GENERIC_SCHED_CLOCK
24 select GENERIC_SMP_IDLE_THREAD
25 select GENERIC_STRNCPY_FROM_USER
26 select GENERIC_STRNLEN_USER
27 select HANDLE_DOMAIN_IRQ
28 select HARDIRQS_SW_RESEND
29 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
30 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
32 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
33 select HAVE_ARCH_TRACEHOOK
35 select HAVE_CC_STACKPROTECTOR
36 select HAVE_CONTEXT_TRACKING
37 select HAVE_C_RECORDMCOUNT
38 select HAVE_DEBUG_KMEMLEAK
39 select HAVE_DMA_API_DEBUG
41 select HAVE_DMA_CONTIGUOUS if MMU
42 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
43 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
44 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
45 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
46 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
47 select HAVE_GENERIC_DMA_COHERENT
48 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
49 select HAVE_IDE if PCI || ISA || PCMCIA
50 select HAVE_IRQ_TIME_ACCOUNTING
51 select HAVE_KERNEL_GZIP
52 select HAVE_KERNEL_LZ4
53 select HAVE_KERNEL_LZMA
54 select HAVE_KERNEL_LZO
56 select HAVE_KPROBES if !XIP_KERNEL
57 select HAVE_KRETPROBES if (HAVE_KPROBES)
59 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
60 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
61 select HAVE_PERF_EVENTS
63 select HAVE_PERF_USER_STACK_DUMP
64 select HAVE_REGS_AND_STACK_ACCESS_API
65 select HAVE_SYSCALL_TRACEPOINTS
67 select HAVE_VIRT_CPU_ACCOUNTING_GEN
68 select IRQ_FORCED_THREADING
69 select MODULES_USE_ELF_REL
72 select OLD_SIGSUSPEND3
73 select PERF_USE_VMALLOC
75 select SYS_SUPPORTS_APM_EMULATION
76 # Above selects are sorted alphabetically; please add new ones
77 # according to that. Thanks.
79 The ARM series is a line of low-power-consumption RISC chip designs
80 licensed by ARM Ltd and targeted at embedded applications and
81 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
82 manufactured, but legacy ARM-based PC hardware remains popular in
83 Europe. There is an ARM Linux project with a web page at
84 <http://www.arm.linux.org.uk/>.
86 config ARM_HAS_SG_CHAIN
87 select ARCH_HAS_SG_CHAIN
90 config NEED_SG_DMA_LENGTH
93 config ARM_DMA_USE_IOMMU
95 select ARM_HAS_SG_CHAIN
96 select NEED_SG_DMA_LENGTH
100 config ARM_DMA_IOMMU_ALIGNMENT
101 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
105 DMA mapping framework by default aligns all buffers to the smallest
106 PAGE_SIZE order which is greater than or equal to the requested buffer
107 size. This works well for buffers up to a few hundreds kilobytes, but
108 for larger buffers it just a waste of address space. Drivers which has
109 relatively small addressing window (like 64Mib) might run out of
110 virtual space with just a few allocations.
112 With this parameter you can specify the maximum PAGE_SIZE order for
113 DMA IOMMU buffers. Larger buffers will be aligned only to this
114 specified order. The order is expressed as a power of two multiplied
119 config MIGHT_HAVE_PCI
122 config SYS_SUPPORTS_APM_EMULATION
127 select GENERIC_ALLOCATOR
138 The Extended Industry Standard Architecture (EISA) bus was
139 developed as an open alternative to the IBM MicroChannel bus.
141 The EISA bus provided some of the features of the IBM MicroChannel
142 bus while maintaining backward compatibility with cards made for
143 the older ISA bus. The EISA bus saw limited use between 1988 and
144 1995 when it was made obsolete by the PCI bus.
146 Say Y here if you are building a kernel for an EISA-based machine.
153 config STACKTRACE_SUPPORT
157 config HAVE_LATENCYTOP_SUPPORT
162 config LOCKDEP_SUPPORT
166 config TRACE_IRQFLAGS_SUPPORT
170 config RWSEM_XCHGADD_ALGORITHM
174 config ARCH_HAS_ILOG2_U32
177 config ARCH_HAS_ILOG2_U64
180 config ARCH_HAS_BANDGAP
183 config GENERIC_HWEIGHT
187 config GENERIC_CALIBRATE_DELAY
191 config ARCH_MAY_HAVE_PC_FDC
197 config NEED_DMA_MAP_STATE
200 config ARCH_SUPPORTS_UPROBES
203 config ARCH_HAS_DMA_SET_COHERENT_MASK
206 config GENERIC_ISA_DMA
212 config NEED_RET_TO_USER
220 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
221 default DRAM_BASE if REMAP_VECTORS_TO_RAM
224 The base address of exception vectors. This must be two pages
227 config ARM_PATCH_PHYS_VIRT
228 bool "Patch physical to virtual translations at runtime" if EMBEDDED
230 depends on !XIP_KERNEL && MMU
231 depends on !ARCH_REALVIEW || !SPARSEMEM
233 Patch phys-to-virt and virt-to-phys translation functions at
234 boot and module load time according to the position of the
235 kernel in system memory.
237 This can only be used with non-XIP MMU kernels where the base
238 of physical memory is at a 16MB boundary.
240 Only disable this option if you know that you do not require
241 this feature (eg, building a kernel for a single machine) and
242 you need to shrink the kernel to the minimal size.
244 config NEED_MACH_IO_H
247 Select this when mach/io.h is required to provide special
248 definitions for this platform. The need for mach/io.h should
249 be avoided when possible.
251 config NEED_MACH_MEMORY_H
254 Select this when mach/memory.h is required to provide special
255 definitions for this platform. The need for mach/memory.h should
256 be avoided when possible.
259 hex "Physical address of main memory" if MMU
260 depends on !ARM_PATCH_PHYS_VIRT
261 default DRAM_BASE if !MMU
262 default 0x00000000 if ARCH_EBSA110 || \
263 EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
268 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
269 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
270 default 0x20000000 if ARCH_S5PV210
271 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
272 default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
273 default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
274 default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
275 default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
277 Please provide the physical address corresponding to the
278 location of main memory in your system.
284 source "init/Kconfig"
286 source "kernel/Kconfig.freezer"
291 bool "MMU-based Paged Memory Management Support"
294 Select if you want MMU-based virtualised addressing space
295 support by paged memory management. If unsure, say 'Y'.
298 # The "ARM system type" choice list is ordered alphabetically by option
299 # text. Please add new entries in the option alphabetic order.
302 prompt "ARM system type"
303 default ARCH_VERSATILE if !MMU
304 default ARCH_MULTIPLATFORM if MMU
306 config ARCH_MULTIPLATFORM
307 bool "Allow multiple platforms to be selected"
309 select ARCH_WANT_OPTIONAL_GPIOLIB
310 select ARM_HAS_SG_CHAIN
311 select ARM_PATCH_PHYS_VIRT
315 select GENERIC_CLOCKEVENTS
316 select MIGHT_HAVE_PCI
317 select MULTI_IRQ_HANDLER
321 config ARCH_INTEGRATOR
322 bool "ARM Ltd. Integrator family"
324 select ARM_PATCH_PHYS_VIRT if MMU
327 select COMMON_CLK_VERSATILE
328 select GENERIC_CLOCKEVENTS
331 select MULTI_IRQ_HANDLER
332 select PLAT_VERSATILE
335 select VERSATILE_FPGA_IRQ
337 Support for ARM's Integrator platform.
340 bool "ARM Ltd. RealView family"
341 select ARCH_WANT_OPTIONAL_GPIOLIB
343 select ARM_TIMER_SP804
345 select COMMON_CLK_VERSATILE
346 select GENERIC_CLOCKEVENTS
347 select GPIO_PL061 if GPIOLIB
349 select NEED_MACH_MEMORY_H
350 select PLAT_VERSATILE
352 This enables support for ARM Ltd RealView boards.
354 config ARCH_VERSATILE
355 bool "ARM Ltd. Versatile family"
356 select ARCH_WANT_OPTIONAL_GPIOLIB
358 select ARM_TIMER_SP804
361 select GENERIC_CLOCKEVENTS
362 select HAVE_MACH_CLKDEV
364 select PLAT_VERSATILE
365 select PLAT_VERSATILE_CLOCK
366 select VERSATILE_FPGA_IRQ
368 This enables support for ARM Ltd Versatile board.
372 select ARCH_REQUIRE_GPIOLIB
375 select NEED_MACH_IO_H if PCCARD
377 select PINCTRL_AT91 if USE_OF
379 This enables support for systems based on Atmel
380 AT91RM9200 and AT91SAM9* processors.
383 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
384 select ARCH_REQUIRE_GPIOLIB
389 select GENERIC_CLOCKEVENTS
393 Support for Cirrus Logic 711x/721x/731x based boards.
396 bool "Cortina Systems Gemini"
397 select ARCH_REQUIRE_GPIOLIB
400 select GENERIC_CLOCKEVENTS
402 Support for the Cortina Systems Gemini family SoCs
406 select ARCH_USES_GETTIMEOFFSET
409 select NEED_MACH_IO_H
410 select NEED_MACH_MEMORY_H
413 This is an evaluation board for the StrongARM processor available
414 from Digital. It has limited hardware on-board, including an
415 Ethernet interface, two PCMCIA sockets, two serial ports and a
419 bool "Energy Micro efm32"
421 select ARCH_REQUIRE_GPIOLIB
427 select GENERIC_CLOCKEVENTS
433 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
438 select ARCH_HAS_HOLES_MEMORYMODEL
439 select ARCH_REQUIRE_GPIOLIB
440 select ARCH_USES_GETTIMEOFFSET
446 This enables support for the Cirrus EP93xx series of CPUs.
448 config ARCH_FOOTBRIDGE
452 select GENERIC_CLOCKEVENTS
454 select NEED_MACH_IO_H if !MMU
455 select NEED_MACH_MEMORY_H
457 Support for systems based on the DC21285 companion chip
458 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
461 bool "Hilscher NetX based"
465 select GENERIC_CLOCKEVENTS
467 This enables support for systems based on the Hilscher NetX Soc
473 select NEED_MACH_MEMORY_H
474 select NEED_RET_TO_USER
480 Support for Intel's IOP13XX (XScale) family of processors.
485 select ARCH_REQUIRE_GPIOLIB
488 select NEED_RET_TO_USER
492 Support for Intel's 80219 and IOP32X (XScale) family of
498 select ARCH_REQUIRE_GPIOLIB
501 select NEED_RET_TO_USER
505 Support for Intel's IOP33X (XScale) family of processors.
510 select ARCH_HAS_DMA_SET_COHERENT_MASK
511 select ARCH_REQUIRE_GPIOLIB
512 select ARCH_SUPPORTS_BIG_ENDIAN
515 select DMABOUNCE if PCI
516 select GENERIC_CLOCKEVENTS
517 select MIGHT_HAVE_PCI
518 select NEED_MACH_IO_H
519 select USB_EHCI_BIG_ENDIAN_DESC
520 select USB_EHCI_BIG_ENDIAN_MMIO
522 Support for Intel's IXP4XX (XScale) family of processors.
526 select ARCH_REQUIRE_GPIOLIB
528 select GENERIC_CLOCKEVENTS
529 select MIGHT_HAVE_PCI
533 select PLAT_ORION_LEGACY
535 Support for the Marvell Dove SoC 88AP510
538 bool "Marvell MV78xx0"
539 select ARCH_REQUIRE_GPIOLIB
541 select GENERIC_CLOCKEVENTS
544 select PLAT_ORION_LEGACY
546 Support for the following Marvell MV78xx0 series SoCs:
552 select ARCH_REQUIRE_GPIOLIB
554 select GENERIC_CLOCKEVENTS
557 select PLAT_ORION_LEGACY
559 Support for the following Marvell Orion 5x series SoCs:
560 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
561 Orion-2 (5281), Orion-1-90 (6183).
564 bool "Marvell PXA168/910/MMP2"
566 select ARCH_REQUIRE_GPIOLIB
568 select GENERIC_ALLOCATOR
569 select GENERIC_CLOCKEVENTS
572 select MULTI_IRQ_HANDLER
577 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
580 bool "Micrel/Kendin KS8695"
581 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_CLOCKEVENTS
585 select NEED_MACH_MEMORY_H
587 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
588 System-on-Chip devices.
591 bool "Nuvoton W90X900 CPU"
592 select ARCH_REQUIRE_GPIOLIB
596 select GENERIC_CLOCKEVENTS
598 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
599 At present, the w90x900 has been renamed nuc900, regarding
600 the ARM series product line, you can login the following
601 link address to know more.
603 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
604 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
608 select ARCH_REQUIRE_GPIOLIB
613 select GENERIC_CLOCKEVENTS
617 Support for the NXP LPC32XX family of processors
620 bool "PXA2xx/PXA3xx-based"
623 select ARCH_REQUIRE_GPIOLIB
624 select ARM_CPU_SUSPEND if PM
629 select GENERIC_CLOCKEVENTS
632 select MULTI_IRQ_HANDLER
636 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
639 bool "Qualcomm MSM (non-multiplatform)"
640 select ARCH_REQUIRE_GPIOLIB
642 select GENERIC_CLOCKEVENTS
644 Support for Qualcomm MSM/QSD based systems. This runs on the
645 apps processor of the MSM/QSD and depends on a shared memory
646 interface to the modem processor which runs the baseband
647 stack and controls some vital subsystems
648 (clock and power control, etc).
650 config ARCH_SHMOBILE_LEGACY
651 bool "Renesas ARM SoCs (non-multiplatform)"
653 select ARM_PATCH_PHYS_VIRT if MMU
656 select GENERIC_CLOCKEVENTS
657 select HAVE_ARM_SCU if SMP
658 select HAVE_ARM_TWD if SMP
659 select HAVE_MACH_CLKDEV
661 select MIGHT_HAVE_CACHE_L2X0
662 select MULTI_IRQ_HANDLER
665 select PM_GENERIC_DOMAINS if PM
669 Support for Renesas ARM SoC platforms using a non-multiplatform
670 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
676 select ARCH_MAY_HAVE_PC_FDC
677 select ARCH_SPARSEMEM_ENABLE
678 select ARCH_USES_GETTIMEOFFSET
682 select HAVE_PATA_PLATFORM
684 select NEED_MACH_IO_H
685 select NEED_MACH_MEMORY_H
689 On the Acorn Risc-PC, Linux can support the internal IDE disk and
690 CD-ROM interface, serial and parallel port, and the floppy drive.
695 select ARCH_REQUIRE_GPIOLIB
696 select ARCH_SPARSEMEM_ENABLE
701 select GENERIC_CLOCKEVENTS
704 select NEED_MACH_MEMORY_H
707 Support for StrongARM 11x0 based boards.
710 bool "Samsung S3C24XX SoCs"
711 select ARCH_REQUIRE_GPIOLIB
714 select CLKSRC_SAMSUNG_PWM
715 select GENERIC_CLOCKEVENTS
717 select HAVE_S3C2410_I2C if I2C
718 select HAVE_S3C2410_WATCHDOG if WATCHDOG
719 select HAVE_S3C_RTC if RTC_CLASS
720 select MULTI_IRQ_HANDLER
721 select NEED_MACH_IO_H
724 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
725 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
726 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
727 Samsung SMDK2410 development board (and derivatives).
730 bool "Samsung S3C64XX"
731 select ARCH_REQUIRE_GPIOLIB
736 select CLKSRC_SAMSUNG_PWM
737 select COMMON_CLK_SAMSUNG
739 select GENERIC_CLOCKEVENTS
741 select HAVE_S3C2410_I2C if I2C
742 select HAVE_S3C2410_WATCHDOG if WATCHDOG
746 select PM_GENERIC_DOMAINS if PM
748 select S3C_GPIO_TRACK
750 select SAMSUNG_WAKEMASK
751 select SAMSUNG_WDT_RESET
753 Samsung S3C64XX series based systems
757 select ARCH_HAS_HOLES_MEMORYMODEL
758 select ARCH_REQUIRE_GPIOLIB
760 select GENERIC_ALLOCATOR
761 select GENERIC_CLOCKEVENTS
762 select GENERIC_IRQ_CHIP
768 Support for TI's DaVinci platform.
773 select ARCH_HAS_HOLES_MEMORYMODEL
775 select ARCH_REQUIRE_GPIOLIB
778 select GENERIC_CLOCKEVENTS
779 select GENERIC_IRQ_CHIP
782 select NEED_MACH_IO_H if PCCARD
783 select NEED_MACH_MEMORY_H
785 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
789 menu "Multiple platform selection"
790 depends on ARCH_MULTIPLATFORM
792 comment "CPU Core family selection"
795 bool "ARMv4 based platforms (FA526)"
796 depends on !ARCH_MULTI_V6_V7
797 select ARCH_MULTI_V4_V5
800 config ARCH_MULTI_V4T
801 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
802 depends on !ARCH_MULTI_V6_V7
803 select ARCH_MULTI_V4_V5
804 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
805 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
806 CPU_ARM925T || CPU_ARM940T)
809 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
810 depends on !ARCH_MULTI_V6_V7
811 select ARCH_MULTI_V4_V5
812 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
813 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
814 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
816 config ARCH_MULTI_V4_V5
820 bool "ARMv6 based platforms (ARM11)"
821 select ARCH_MULTI_V6_V7
825 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
827 select ARCH_MULTI_V6_V7
831 config ARCH_MULTI_V6_V7
833 select MIGHT_HAVE_CACHE_L2X0
835 config ARCH_MULTI_CPU_AUTO
836 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
842 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
846 select HAVE_ARM_ARCH_TIMER
849 # This is sorted alphabetically by mach-* pathname. However, plat-*
850 # Kconfigs may be included either alphabetically (according to the
851 # plat- suffix) or along side the corresponding mach-* source.
853 source "arch/arm/mach-mvebu/Kconfig"
855 source "arch/arm/mach-at91/Kconfig"
857 source "arch/arm/mach-axxia/Kconfig"
859 source "arch/arm/mach-bcm/Kconfig"
861 source "arch/arm/mach-berlin/Kconfig"
863 source "arch/arm/mach-clps711x/Kconfig"
865 source "arch/arm/mach-cns3xxx/Kconfig"
867 source "arch/arm/mach-davinci/Kconfig"
869 source "arch/arm/mach-dove/Kconfig"
871 source "arch/arm/mach-ep93xx/Kconfig"
873 source "arch/arm/mach-footbridge/Kconfig"
875 source "arch/arm/mach-gemini/Kconfig"
877 source "arch/arm/mach-highbank/Kconfig"
879 source "arch/arm/mach-hisi/Kconfig"
881 source "arch/arm/mach-integrator/Kconfig"
883 source "arch/arm/mach-iop32x/Kconfig"
885 source "arch/arm/mach-iop33x/Kconfig"
887 source "arch/arm/mach-iop13xx/Kconfig"
889 source "arch/arm/mach-ixp4xx/Kconfig"
891 source "arch/arm/mach-keystone/Kconfig"
893 source "arch/arm/mach-ks8695/Kconfig"
895 source "arch/arm/mach-meson/Kconfig"
897 source "arch/arm/mach-msm/Kconfig"
899 source "arch/arm/mach-moxart/Kconfig"
901 source "arch/arm/mach-mv78xx0/Kconfig"
903 source "arch/arm/mach-imx/Kconfig"
905 source "arch/arm/mach-mediatek/Kconfig"
907 source "arch/arm/mach-mxs/Kconfig"
909 source "arch/arm/mach-netx/Kconfig"
911 source "arch/arm/mach-nomadik/Kconfig"
913 source "arch/arm/mach-nspire/Kconfig"
915 source "arch/arm/plat-omap/Kconfig"
917 source "arch/arm/mach-omap1/Kconfig"
919 source "arch/arm/mach-omap2/Kconfig"
921 source "arch/arm/mach-orion5x/Kconfig"
923 source "arch/arm/mach-picoxcell/Kconfig"
925 source "arch/arm/mach-pxa/Kconfig"
926 source "arch/arm/plat-pxa/Kconfig"
928 source "arch/arm/mach-mmp/Kconfig"
930 source "arch/arm/mach-qcom/Kconfig"
932 source "arch/arm/mach-realview/Kconfig"
934 source "arch/arm/mach-rockchip/Kconfig"
936 source "arch/arm/mach-sa1100/Kconfig"
938 source "arch/arm/mach-socfpga/Kconfig"
940 source "arch/arm/mach-spear/Kconfig"
942 source "arch/arm/mach-sti/Kconfig"
944 source "arch/arm/mach-s3c24xx/Kconfig"
946 source "arch/arm/mach-s3c64xx/Kconfig"
948 source "arch/arm/mach-s5pv210/Kconfig"
950 source "arch/arm/mach-exynos/Kconfig"
951 source "arch/arm/plat-samsung/Kconfig"
953 source "arch/arm/mach-shmobile/Kconfig"
955 source "arch/arm/mach-sunxi/Kconfig"
957 source "arch/arm/mach-prima2/Kconfig"
959 source "arch/arm/mach-tegra/Kconfig"
961 source "arch/arm/mach-u300/Kconfig"
963 source "arch/arm/mach-ux500/Kconfig"
965 source "arch/arm/mach-versatile/Kconfig"
967 source "arch/arm/mach-vexpress/Kconfig"
968 source "arch/arm/plat-versatile/Kconfig"
970 source "arch/arm/mach-vt8500/Kconfig"
972 source "arch/arm/mach-w90x900/Kconfig"
974 source "arch/arm/mach-zynq/Kconfig"
976 # Definitions to make life easier
982 select GENERIC_CLOCKEVENTS
988 select GENERIC_IRQ_CHIP
991 config PLAT_ORION_LEGACY
998 config PLAT_VERSATILE
1001 config ARM_TIMER_SP804
1004 select CLKSRC_OF if OF
1006 source "arch/arm/firmware/Kconfig"
1008 source arch/arm/mm/Kconfig
1011 bool "Enable iWMMXt support"
1012 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1013 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1015 Enable support for iWMMXt context switching at run time if
1016 running on a CPU that supports it.
1018 config MULTI_IRQ_HANDLER
1021 Allow each machine to specify it's own IRQ handler at run time.
1024 source "arch/arm/Kconfig-nommu"
1027 config PJ4B_ERRATA_4742
1028 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1029 depends on CPU_PJ4B && MACH_ARMADA_370
1032 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1033 Event (WFE) IDLE states, a specific timing sensitivity exists between
1034 the retiring WFI/WFE instructions and the newly issued subsequent
1035 instructions. This sensitivity can result in a CPU hang scenario.
1037 The software must insert either a Data Synchronization Barrier (DSB)
1038 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1041 config ARM_ERRATA_326103
1042 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1045 Executing a SWP instruction to read-only memory does not set bit 11
1046 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1047 treat the access as a read, preventing a COW from occurring and
1048 causing the faulting task to livelock.
1050 config ARM_ERRATA_411920
1051 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1052 depends on CPU_V6 || CPU_V6K
1054 Invalidation of the Instruction Cache operation can
1055 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1056 It does not affect the MPCore. This option enables the ARM Ltd.
1057 recommended workaround.
1059 config ARM_ERRATA_430973
1060 bool "ARM errata: Stale prediction on replaced interworking branch"
1063 This option enables the workaround for the 430973 Cortex-A8
1064 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1065 interworking branch is replaced with another code sequence at the
1066 same virtual address, whether due to self-modifying code or virtual
1067 to physical address re-mapping, Cortex-A8 does not recover from the
1068 stale interworking branch prediction. This results in Cortex-A8
1069 executing the new code sequence in the incorrect ARM or Thumb state.
1070 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1071 and also flushes the branch target cache at every context switch.
1072 Note that setting specific bits in the ACTLR register may not be
1073 available in non-secure mode.
1075 config ARM_ERRATA_458693
1076 bool "ARM errata: Processor deadlock when a false hazard is created"
1078 depends on !ARCH_MULTIPLATFORM
1080 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1081 erratum. For very specific sequences of memory operations, it is
1082 possible for a hazard condition intended for a cache line to instead
1083 be incorrectly associated with a different cache line. This false
1084 hazard might then cause a processor deadlock. The workaround enables
1085 the L1 caching of the NEON accesses and disables the PLD instruction
1086 in the ACTLR register. Note that setting specific bits in the ACTLR
1087 register may not be available in non-secure mode.
1089 config ARM_ERRATA_460075
1090 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1092 depends on !ARCH_MULTIPLATFORM
1094 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1095 erratum. Any asynchronous access to the L2 cache may encounter a
1096 situation in which recent store transactions to the L2 cache are lost
1097 and overwritten with stale memory contents from external memory. The
1098 workaround disables the write-allocate mode for the L2 cache via the
1099 ACTLR register. Note that setting specific bits in the ACTLR register
1100 may not be available in non-secure mode.
1102 config ARM_ERRATA_742230
1103 bool "ARM errata: DMB operation may be faulty"
1104 depends on CPU_V7 && SMP
1105 depends on !ARCH_MULTIPLATFORM
1107 This option enables the workaround for the 742230 Cortex-A9
1108 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1109 between two write operations may not ensure the correct visibility
1110 ordering of the two writes. This workaround sets a specific bit in
1111 the diagnostic register of the Cortex-A9 which causes the DMB
1112 instruction to behave as a DSB, ensuring the correct behaviour of
1115 config ARM_ERRATA_742231
1116 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1117 depends on CPU_V7 && SMP
1118 depends on !ARCH_MULTIPLATFORM
1120 This option enables the workaround for the 742231 Cortex-A9
1121 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1122 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1123 accessing some data located in the same cache line, may get corrupted
1124 data due to bad handling of the address hazard when the line gets
1125 replaced from one of the CPUs at the same time as another CPU is
1126 accessing it. This workaround sets specific bits in the diagnostic
1127 register of the Cortex-A9 which reduces the linefill issuing
1128 capabilities of the processor.
1130 config ARM_ERRATA_643719
1131 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1132 depends on CPU_V7 && SMP
1134 This option enables the workaround for the 643719 Cortex-A9 (prior to
1135 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1136 register returns zero when it should return one. The workaround
1137 corrects this value, ensuring cache maintenance operations which use
1138 it behave as intended and avoiding data corruption.
1140 config ARM_ERRATA_720789
1141 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1144 This option enables the workaround for the 720789 Cortex-A9 (prior to
1145 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1146 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1147 As a consequence of this erratum, some TLB entries which should be
1148 invalidated are not, resulting in an incoherency in the system page
1149 tables. The workaround changes the TLB flushing routines to invalidate
1150 entries regardless of the ASID.
1152 config ARM_ERRATA_743622
1153 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1155 depends on !ARCH_MULTIPLATFORM
1157 This option enables the workaround for the 743622 Cortex-A9
1158 (r2p*) erratum. Under very rare conditions, a faulty
1159 optimisation in the Cortex-A9 Store Buffer may lead to data
1160 corruption. This workaround sets a specific bit in the diagnostic
1161 register of the Cortex-A9 which disables the Store Buffer
1162 optimisation, preventing the defect from occurring. This has no
1163 visible impact on the overall performance or power consumption of the
1166 config ARM_ERRATA_751472
1167 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1169 depends on !ARCH_MULTIPLATFORM
1171 This option enables the workaround for the 751472 Cortex-A9 (prior
1172 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1173 completion of a following broadcasted operation if the second
1174 operation is received by a CPU before the ICIALLUIS has completed,
1175 potentially leading to corrupted entries in the cache or TLB.
1177 config ARM_ERRATA_754322
1178 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1181 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1182 r3p*) erratum. A speculative memory access may cause a page table walk
1183 which starts prior to an ASID switch but completes afterwards. This
1184 can populate the micro-TLB with a stale entry which may be hit with
1185 the new ASID. This workaround places two dsb instructions in the mm
1186 switching code so that no page table walks can cross the ASID switch.
1188 config ARM_ERRATA_754327
1189 bool "ARM errata: no automatic Store Buffer drain"
1190 depends on CPU_V7 && SMP
1192 This option enables the workaround for the 754327 Cortex-A9 (prior to
1193 r2p0) erratum. The Store Buffer does not have any automatic draining
1194 mechanism and therefore a livelock may occur if an external agent
1195 continuously polls a memory location waiting to observe an update.
1196 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1197 written polling loops from denying visibility of updates to memory.
1199 config ARM_ERRATA_364296
1200 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1203 This options enables the workaround for the 364296 ARM1136
1204 r0p2 erratum (possible cache data corruption with
1205 hit-under-miss enabled). It sets the undocumented bit 31 in
1206 the auxiliary control register and the FI bit in the control
1207 register, thus disabling hit-under-miss without putting the
1208 processor into full low interrupt latency mode. ARM11MPCore
1211 config ARM_ERRATA_764369
1212 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1213 depends on CPU_V7 && SMP
1215 This option enables the workaround for erratum 764369
1216 affecting Cortex-A9 MPCore with two or more processors (all
1217 current revisions). Under certain timing circumstances, a data
1218 cache line maintenance operation by MVA targeting an Inner
1219 Shareable memory region may fail to proceed up to either the
1220 Point of Coherency or to the Point of Unification of the
1221 system. This workaround adds a DSB instruction before the
1222 relevant cache maintenance functions and sets a specific bit
1223 in the diagnostic control register of the SCU.
1225 config ARM_ERRATA_775420
1226 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1229 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1230 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1231 operation aborts with MMU exception, it might cause the processor
1232 to deadlock. This workaround puts DSB before executing ISB if
1233 an abort may occur on cache maintenance.
1235 config ARM_ERRATA_798181
1236 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1237 depends on CPU_V7 && SMP
1239 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1240 adequately shooting down all use of the old entries. This
1241 option enables the Linux kernel workaround for this erratum
1242 which sends an IPI to the CPUs that are running the same ASID
1243 as the one being invalidated.
1245 config ARM_ERRATA_773022
1246 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1249 This option enables the workaround for the 773022 Cortex-A15
1250 (up to r0p4) erratum. In certain rare sequences of code, the
1251 loop buffer may deliver incorrect instructions. This
1252 workaround disables the loop buffer to avoid the erratum.
1256 source "arch/arm/common/Kconfig"
1266 Find out whether you have ISA slots on your motherboard. ISA is the
1267 name of a bus system, i.e. the way the CPU talks to the other stuff
1268 inside your box. Other bus systems are PCI, EISA, MicroChannel
1269 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1270 newer boards don't support it. If you have ISA, say Y, otherwise N.
1272 # Select ISA DMA controller support
1277 # Select ISA DMA interface
1282 bool "PCI support" if MIGHT_HAVE_PCI
1284 Find out whether you have a PCI motherboard. PCI is the name of a
1285 bus system, i.e. the way the CPU talks to the other stuff inside
1286 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1287 VESA. If you have PCI, say Y, otherwise N.
1293 config PCI_NANOENGINE
1294 bool "BSE nanoEngine PCI support"
1295 depends on SA1100_NANOENGINE
1297 Enable PCI on the BSE nanoEngine board.
1302 config PCI_HOST_ITE8152
1304 depends on PCI && MACH_ARMCORE
1308 source "drivers/pci/Kconfig"
1309 source "drivers/pci/pcie/Kconfig"
1311 source "drivers/pcmcia/Kconfig"
1315 menu "Kernel Features"
1320 This option should be selected by machines which have an SMP-
1323 The only effect of this option is to make the SMP-related
1324 options available to the user for configuration.
1327 bool "Symmetric Multi-Processing"
1328 depends on CPU_V6K || CPU_V7
1329 depends on GENERIC_CLOCKEVENTS
1331 depends on MMU || ARM_MPU
1333 This enables support for systems with more than one CPU. If you have
1334 a system with only one CPU, say N. If you have a system with more
1335 than one CPU, say Y.
1337 If you say N here, the kernel will run on uni- and multiprocessor
1338 machines, but will use only one CPU of a multiprocessor machine. If
1339 you say Y here, the kernel will run on many, but not all,
1340 uniprocessor machines. On a uniprocessor machine, the kernel
1341 will run faster if you say N here.
1343 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1344 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1345 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1347 If you don't know what to do here, say N.
1350 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1351 depends on SMP && !XIP_KERNEL && MMU
1354 SMP kernels contain instructions which fail on non-SMP processors.
1355 Enabling this option allows the kernel to modify itself to make
1356 these instructions safe. Disabling it allows about 1K of space
1359 If you don't know what to do here, say Y.
1361 config ARM_CPU_TOPOLOGY
1362 bool "Support cpu topology definition"
1363 depends on SMP && CPU_V7
1366 Support ARM cpu topology definition. The MPIDR register defines
1367 affinity between processors which is then used to describe the cpu
1368 topology of an ARM System.
1371 bool "Multi-core scheduler support"
1372 depends on ARM_CPU_TOPOLOGY
1374 Multi-core scheduler support improves the CPU scheduler's decision
1375 making when dealing with multi-core CPU chips at a cost of slightly
1376 increased overhead in some places. If unsure say N here.
1379 bool "SMT scheduler support"
1380 depends on ARM_CPU_TOPOLOGY
1382 Improves the CPU scheduler's decision making when dealing with
1383 MultiThreading at a cost of slightly increased overhead in some
1384 places. If unsure say N here.
1389 This option enables support for the ARM system coherency unit
1391 config HAVE_ARM_ARCH_TIMER
1392 bool "Architected timer support"
1394 select ARM_ARCH_TIMER
1395 select GENERIC_CLOCKEVENTS
1397 This option enables support for the ARM architected timer
1402 select CLKSRC_OF if OF
1404 This options enables support for the ARM timer and watchdog unit
1407 bool "Multi-Cluster Power Management"
1408 depends on CPU_V7 && SMP
1410 This option provides the common power management infrastructure
1411 for (multi-)cluster based systems, such as big.LITTLE based
1414 config MCPM_QUAD_CLUSTER
1418 To avoid wasting resources unnecessarily, MCPM only supports up
1419 to 2 clusters by default.
1420 Platforms with 3 or 4 clusters that use MCPM must select this
1421 option to allow the additional clusters to be managed.
1424 bool "big.LITTLE support (Experimental)"
1425 depends on CPU_V7 && SMP
1428 This option enables support selections for the big.LITTLE
1429 system architecture.
1432 bool "big.LITTLE switcher support"
1433 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1434 select ARM_CPU_SUSPEND
1437 The big.LITTLE "switcher" provides the core functionality to
1438 transparently handle transition between a cluster of A15's
1439 and a cluster of A7's in a big.LITTLE system.
1441 config BL_SWITCHER_DUMMY_IF
1442 tristate "Simple big.LITTLE switcher user interface"
1443 depends on BL_SWITCHER && DEBUG_KERNEL
1445 This is a simple and dummy char dev interface to control
1446 the big.LITTLE switcher core code. It is meant for
1447 debugging purposes only.
1450 prompt "Memory split"
1454 Select the desired split between kernel and user memory.
1456 If you are not absolutely sure what you are doing, leave this
1460 bool "3G/1G user/kernel split"
1462 bool "2G/2G user/kernel split"
1464 bool "1G/3G user/kernel split"
1469 default PHYS_OFFSET if !MMU
1470 default 0x40000000 if VMSPLIT_1G
1471 default 0x80000000 if VMSPLIT_2G
1475 int "Maximum number of CPUs (2-32)"
1481 bool "Support for hot-pluggable CPUs"
1484 Say Y here to experiment with turning CPUs off and on. CPUs
1485 can be controlled through /sys/devices/system/cpu.
1488 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1491 Say Y here if you want Linux to communicate with system firmware
1492 implementing the PSCI specification for CPU-centric power
1493 management operations described in ARM document number ARM DEN
1494 0022A ("Power State Coordination Interface System Software on
1497 # The GPIO number here must be sorted by descending number. In case of
1498 # a multiplatform kernel, we just want the highest value required by the
1499 # selected platforms.
1502 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1503 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1504 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1505 default 416 if ARCH_SUNXI
1506 default 392 if ARCH_U8500
1507 default 352 if ARCH_VT8500
1508 default 288 if ARCH_ROCKCHIP
1509 default 264 if MACH_H4700
1512 Maximum number of GPIOs in the system.
1514 If unsure, leave the default value.
1516 source kernel/Kconfig.preempt
1520 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1521 ARCH_S5PV210 || ARCH_EXYNOS4
1522 default AT91_TIMER_HZ if ARCH_AT91
1523 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1527 depends on HZ_FIXED = 0
1528 prompt "Timer frequency"
1552 default HZ_FIXED if HZ_FIXED != 0
1553 default 100 if HZ_100
1554 default 200 if HZ_200
1555 default 250 if HZ_250
1556 default 300 if HZ_300
1557 default 500 if HZ_500
1561 def_bool HIGH_RES_TIMERS
1563 config THUMB2_KERNEL
1564 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1565 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1566 default y if CPU_THUMBONLY
1568 select ARM_ASM_UNIFIED
1571 By enabling this option, the kernel will be compiled in
1572 Thumb-2 mode. A compiler/assembler that understand the unified
1573 ARM-Thumb syntax is needed.
1577 config THUMB2_AVOID_R_ARM_THM_JUMP11
1578 bool "Work around buggy Thumb-2 short branch relocations in gas"
1579 depends on THUMB2_KERNEL && MODULES
1582 Various binutils versions can resolve Thumb-2 branches to
1583 locally-defined, preemptible global symbols as short-range "b.n"
1584 branch instructions.
1586 This is a problem, because there's no guarantee the final
1587 destination of the symbol, or any candidate locations for a
1588 trampoline, are within range of the branch. For this reason, the
1589 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1590 relocation in modules at all, and it makes little sense to add
1593 The symptom is that the kernel fails with an "unsupported
1594 relocation" error when loading some modules.
1596 Until fixed tools are available, passing
1597 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1598 code which hits this problem, at the cost of a bit of extra runtime
1599 stack usage in some cases.
1601 The problem is described in more detail at:
1602 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1604 Only Thumb-2 kernels are affected.
1606 Unless you are sure your tools don't have this problem, say Y.
1608 config ARM_ASM_UNIFIED
1612 bool "Use the ARM EABI to compile the kernel"
1614 This option allows for the kernel to be compiled using the latest
1615 ARM ABI (aka EABI). This is only useful if you are using a user
1616 space environment that is also compiled with EABI.
1618 Since there are major incompatibilities between the legacy ABI and
1619 EABI, especially with regard to structure member alignment, this
1620 option also changes the kernel syscall calling convention to
1621 disambiguate both ABIs and allow for backward compatibility support
1622 (selected with CONFIG_OABI_COMPAT).
1624 To use this you need GCC version 4.0.0 or later.
1627 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1628 depends on AEABI && !THUMB2_KERNEL
1630 This option preserves the old syscall interface along with the
1631 new (ARM EABI) one. It also provides a compatibility layer to
1632 intercept syscalls that have structure arguments which layout
1633 in memory differs between the legacy ABI and the new ARM EABI
1634 (only for non "thumb" binaries). This option adds a tiny
1635 overhead to all syscalls and produces a slightly larger kernel.
1637 The seccomp filter system will not be available when this is
1638 selected, since there is no way yet to sensibly distinguish
1639 between calling conventions during filtering.
1641 If you know you'll be using only pure EABI user space then you
1642 can say N here. If this option is not selected and you attempt
1643 to execute a legacy ABI binary then the result will be
1644 UNPREDICTABLE (in fact it can be predicted that it won't work
1645 at all). If in doubt say N.
1647 config ARCH_HAS_HOLES_MEMORYMODEL
1650 config ARCH_SPARSEMEM_ENABLE
1653 config ARCH_SPARSEMEM_DEFAULT
1654 def_bool ARCH_SPARSEMEM_ENABLE
1656 config ARCH_SELECT_MEMORY_MODEL
1657 def_bool ARCH_SPARSEMEM_ENABLE
1659 config HAVE_ARCH_PFN_VALID
1660 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1663 bool "High Memory Support"
1666 The address space of ARM processors is only 4 Gigabytes large
1667 and it has to accommodate user address space, kernel address
1668 space as well as some memory mapped IO. That means that, if you
1669 have a large amount of physical memory and/or IO, not all of the
1670 memory can be "permanently mapped" by the kernel. The physical
1671 memory that is not permanently mapped is called "high memory".
1673 Depending on the selected kernel/user memory split, minimum
1674 vmalloc space and actual amount of RAM, you may not need this
1675 option which should result in a slightly faster kernel.
1680 bool "Allocate 2nd-level pagetables from highmem"
1683 config HW_PERF_EVENTS
1684 bool "Enable hardware performance counter support for perf events"
1685 depends on PERF_EVENTS
1688 Enable hardware performance counter support for perf events. If
1689 disabled, perf events will use software events only.
1691 config SYS_SUPPORTS_HUGETLBFS
1695 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1699 config ARCH_WANT_GENERAL_HUGETLB
1704 config FORCE_MAX_ZONEORDER
1705 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1706 range 11 64 if ARCH_SHMOBILE_LEGACY
1707 default "12" if SOC_AM33XX
1708 default "9" if SA1111 || ARCH_EFM32
1711 The kernel memory allocator divides physically contiguous memory
1712 blocks into "zones", where each zone is a power of two number of
1713 pages. This option selects the largest power of two that the kernel
1714 keeps in the memory allocator. If you need to allocate very large
1715 blocks of physically contiguous memory, then you may need to
1716 increase this value.
1718 This config option is actually maximum order plus one. For example,
1719 a value of 11 means that the largest free memory block is 2^10 pages.
1721 config ALIGNMENT_TRAP
1723 depends on CPU_CP15_MMU
1724 default y if !ARCH_EBSA110
1725 select HAVE_PROC_CPU if PROC_FS
1727 ARM processors cannot fetch/store information which is not
1728 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1729 address divisible by 4. On 32-bit ARM processors, these non-aligned
1730 fetch/store instructions will be emulated in software if you say
1731 here, which has a severe performance impact. This is necessary for
1732 correct operation of some network protocols. With an IP-only
1733 configuration it is safe to say N, otherwise say Y.
1735 config UACCESS_WITH_MEMCPY
1736 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1738 default y if CPU_FEROCEON
1740 Implement faster copy_to_user and clear_user methods for CPU
1741 cores where a 8-word STM instruction give significantly higher
1742 memory write throughput than a sequence of individual 32bit stores.
1744 A possible side effect is a slight increase in scheduling latency
1745 between threads sharing the same address space if they invoke
1746 such copy operations with large buffers.
1748 However, if the CPU data cache is using a write-allocate mode,
1749 this option is unlikely to provide any performance gain.
1753 prompt "Enable seccomp to safely compute untrusted bytecode"
1755 This kernel feature is useful for number crunching applications
1756 that may need to compute untrusted bytecode during their
1757 execution. By using pipes or other transports made available to
1758 the process as file descriptors supporting the read/write
1759 syscalls, it's possible to isolate those applications in
1760 their own address space using seccomp. Once seccomp is
1761 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1762 and the task is only allowed to execute a few safe syscalls
1763 defined by each seccomp mode.
1776 bool "Xen guest support on ARM (EXPERIMENTAL)"
1777 depends on ARM && AEABI && OF
1778 depends on CPU_V7 && !CPU_V6
1779 depends on !GENERIC_ATOMIC64
1781 select ARCH_DMA_ADDR_T_64BIT
1785 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1792 bool "Flattened Device Tree support"
1795 select OF_EARLY_FLATTREE
1796 select OF_RESERVED_MEM
1798 Include support for flattened device tree machine descriptions.
1801 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1804 This is the traditional way of passing data to the kernel at boot
1805 time. If you are solely relying on the flattened device tree (or
1806 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1807 to remove ATAGS support from your kernel binary. If unsure,
1810 config DEPRECATED_PARAM_STRUCT
1811 bool "Provide old way to pass kernel parameters"
1814 This was deprecated in 2001 and announced to live on for 5 years.
1815 Some old boot loaders still use this way.
1817 # Compressed boot loader in ROM. Yes, we really want to ask about
1818 # TEXT and BSS so we preserve their values in the config files.
1819 config ZBOOT_ROM_TEXT
1820 hex "Compressed ROM boot loader base address"
1823 The physical address at which the ROM-able zImage is to be
1824 placed in the target. Platforms which normally make use of
1825 ROM-able zImage formats normally set this to a suitable
1826 value in their defconfig file.
1828 If ZBOOT_ROM is not enabled, this has no effect.
1830 config ZBOOT_ROM_BSS
1831 hex "Compressed ROM boot loader BSS address"
1834 The base address of an area of read/write memory in the target
1835 for the ROM-able zImage which must be available while the
1836 decompressor is running. It must be large enough to hold the
1837 entire decompressed kernel plus an additional 128 KiB.
1838 Platforms which normally make use of ROM-able zImage formats
1839 normally set this to a suitable value in their defconfig file.
1841 If ZBOOT_ROM is not enabled, this has no effect.
1844 bool "Compressed boot loader in ROM/flash"
1845 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1846 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1848 Say Y here if you intend to execute your compressed kernel image
1849 (zImage) directly from ROM or flash. If unsure, say N.
1852 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1853 depends on ZBOOT_ROM && ARCH_SH7372
1854 default ZBOOT_ROM_NONE
1856 Include experimental SD/MMC loading code in the ROM-able zImage.
1857 With this enabled it is possible to write the ROM-able zImage
1858 kernel image to an MMC or SD card and boot the kernel straight
1859 from the reset vector. At reset the processor Mask ROM will load
1860 the first part of the ROM-able zImage which in turn loads the
1861 rest the kernel image to RAM.
1863 config ZBOOT_ROM_NONE
1864 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1866 Do not load image from SD or MMC
1868 config ZBOOT_ROM_MMCIF
1869 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1871 Load image from MMCIF hardware block.
1873 config ZBOOT_ROM_SH_MOBILE_SDHI
1874 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1876 Load image from SDHI hardware block
1880 config ARM_APPENDED_DTB
1881 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1884 With this option, the boot code will look for a device tree binary
1885 (DTB) appended to zImage
1886 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1888 This is meant as a backward compatibility convenience for those
1889 systems with a bootloader that can't be upgraded to accommodate
1890 the documented boot protocol using a device tree.
1892 Beware that there is very little in terms of protection against
1893 this option being confused by leftover garbage in memory that might
1894 look like a DTB header after a reboot if no actual DTB is appended
1895 to zImage. Do not leave this option active in a production kernel
1896 if you don't intend to always append a DTB. Proper passing of the
1897 location into r2 of a bootloader provided DTB is always preferable
1900 config ARM_ATAG_DTB_COMPAT
1901 bool "Supplement the appended DTB with traditional ATAG information"
1902 depends on ARM_APPENDED_DTB
1904 Some old bootloaders can't be updated to a DTB capable one, yet
1905 they provide ATAGs with memory configuration, the ramdisk address,
1906 the kernel cmdline string, etc. Such information is dynamically
1907 provided by the bootloader and can't always be stored in a static
1908 DTB. To allow a device tree enabled kernel to be used with such
1909 bootloaders, this option allows zImage to extract the information
1910 from the ATAG list and store it at run time into the appended DTB.
1913 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1914 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1916 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1917 bool "Use bootloader kernel arguments if available"
1919 Uses the command-line options passed by the boot loader instead of
1920 the device tree bootargs property. If the boot loader doesn't provide
1921 any, the device tree bootargs property will be used.
1923 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1924 bool "Extend with bootloader kernel arguments"
1926 The command-line arguments provided by the boot loader will be
1927 appended to the the device tree bootargs property.
1932 string "Default kernel command string"
1935 On some architectures (EBSA110 and CATS), there is currently no way
1936 for the boot loader to pass arguments to the kernel. For these
1937 architectures, you should supply some command-line options at build
1938 time by entering them here. As a minimum, you should specify the
1939 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1942 prompt "Kernel command line type" if CMDLINE != ""
1943 default CMDLINE_FROM_BOOTLOADER
1946 config CMDLINE_FROM_BOOTLOADER
1947 bool "Use bootloader kernel arguments if available"
1949 Uses the command-line options passed by the boot loader. If
1950 the boot loader doesn't provide any, the default kernel command
1951 string provided in CMDLINE will be used.
1953 config CMDLINE_EXTEND
1954 bool "Extend bootloader kernel arguments"
1956 The command-line arguments provided by the boot loader will be
1957 appended to the default kernel command string.
1959 config CMDLINE_FORCE
1960 bool "Always use the default kernel command string"
1962 Always use the default kernel command string, even if the boot
1963 loader passes other arguments to the kernel.
1964 This is useful if you cannot or don't want to change the
1965 command-line options your boot loader passes to the kernel.
1969 bool "Kernel Execute-In-Place from ROM"
1970 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1972 Execute-In-Place allows the kernel to run from non-volatile storage
1973 directly addressable by the CPU, such as NOR flash. This saves RAM
1974 space since the text section of the kernel is not loaded from flash
1975 to RAM. Read-write sections, such as the data section and stack,
1976 are still copied to RAM. The XIP kernel is not compressed since
1977 it has to run directly from flash, so it will take more space to
1978 store it. The flash address used to link the kernel object files,
1979 and for storing it, is configuration dependent. Therefore, if you
1980 say Y here, you must know the proper physical address where to
1981 store the kernel image depending on your own flash memory usage.
1983 Also note that the make target becomes "make xipImage" rather than
1984 "make zImage" or "make Image". The final kernel binary to put in
1985 ROM memory will be arch/arm/boot/xipImage.
1989 config XIP_PHYS_ADDR
1990 hex "XIP Kernel Physical Location"
1991 depends on XIP_KERNEL
1992 default "0x00080000"
1994 This is the physical address in your flash memory the kernel will
1995 be linked for and stored to. This address is dependent on your
1999 bool "Kexec system call (EXPERIMENTAL)"
2000 depends on (!SMP || PM_SLEEP_SMP)
2002 kexec is a system call that implements the ability to shutdown your
2003 current kernel, and to start another kernel. It is like a reboot
2004 but it is independent of the system firmware. And like a reboot
2005 you can start any kernel with it, not just Linux.
2007 It is an ongoing process to be certain the hardware in a machine
2008 is properly shutdown, so do not be surprised if this code does not
2009 initially work for you.
2012 bool "Export atags in procfs"
2013 depends on ATAGS && KEXEC
2016 Should the atags used to boot the kernel be exported in an "atags"
2017 file in procfs. Useful with kexec.
2020 bool "Build kdump crash kernel (EXPERIMENTAL)"
2022 Generate crash dump after being started by kexec. This should
2023 be normally only set in special crash dump kernels which are
2024 loaded in the main kernel with kexec-tools into a specially
2025 reserved region and then later executed after a crash by
2026 kdump/kexec. The crash dump kernel must be compiled to a
2027 memory address not used by the main kernel
2029 For more details see Documentation/kdump/kdump.txt
2031 config AUTO_ZRELADDR
2032 bool "Auto calculation of the decompressed kernel image address"
2034 ZRELADDR is the physical address where the decompressed kernel
2035 image will be placed. If AUTO_ZRELADDR is selected, the address
2036 will be determined at run-time by masking the current IP with
2037 0xf8000000. This assumes the zImage being placed in the first 128MB
2038 from start of memory.
2042 menu "CPU Power Management"
2044 source "drivers/cpufreq/Kconfig"
2046 source "drivers/cpuidle/Kconfig"
2050 menu "Floating point emulation"
2052 comment "At least one emulation must be selected"
2055 bool "NWFPE math emulation"
2056 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2058 Say Y to include the NWFPE floating point emulator in the kernel.
2059 This is necessary to run most binaries. Linux does not currently
2060 support floating point hardware so you need to say Y here even if
2061 your machine has an FPA or floating point co-processor podule.
2063 You may say N here if you are going to load the Acorn FPEmulator
2064 early in the bootup.
2067 bool "Support extended precision"
2068 depends on FPE_NWFPE
2070 Say Y to include 80-bit support in the kernel floating-point
2071 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2072 Note that gcc does not generate 80-bit operations by default,
2073 so in most cases this option only enlarges the size of the
2074 floating point emulator without any good reason.
2076 You almost surely want to say N here.
2079 bool "FastFPE math emulation (EXPERIMENTAL)"
2080 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2082 Say Y here to include the FAST floating point emulator in the kernel.
2083 This is an experimental much faster emulator which now also has full
2084 precision for the mantissa. It does not support any exceptions.
2085 It is very simple, and approximately 3-6 times faster than NWFPE.
2087 It should be sufficient for most programs. It may be not suitable
2088 for scientific calculations, but you have to check this for yourself.
2089 If you do not feel you need a faster FP emulation you should better
2093 bool "VFP-format floating point maths"
2094 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2096 Say Y to include VFP support code in the kernel. This is needed
2097 if your hardware includes a VFP unit.
2099 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2100 release notes and additional status information.
2102 Say N if your target does not have VFP hardware.
2110 bool "Advanced SIMD (NEON) Extension support"
2111 depends on VFPv3 && CPU_V7
2113 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2116 config KERNEL_MODE_NEON
2117 bool "Support for NEON in kernel mode"
2118 depends on NEON && AEABI
2120 Say Y to include support for NEON in kernel mode.
2124 menu "Userspace binary formats"
2126 source "fs/Kconfig.binfmt"
2129 tristate "RISC OS personality"
2132 Say Y here to include the kernel code necessary if you want to run
2133 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2134 experimental; if this sounds frightening, say N and sleep in peace.
2135 You can also say M here to compile this support as a module (which
2136 will be called arthur).
2140 menu "Power management options"
2142 source "kernel/power/Kconfig"
2144 config ARCH_SUSPEND_POSSIBLE
2145 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2146 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2149 config ARM_CPU_SUSPEND
2152 config ARCH_HIBERNATION_POSSIBLE
2155 default y if ARCH_SUSPEND_POSSIBLE
2159 source "net/Kconfig"
2161 source "drivers/Kconfig"
2165 source "arch/arm/Kconfig.debug"
2167 source "security/Kconfig"
2169 source "crypto/Kconfig"
2171 source "lib/Kconfig"
2173 source "arch/arm/kvm/Kconfig"