1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_CLOCKSOURCE_DATA
7 select ARCH_HAS_BINFMT_FLAT
8 select ARCH_HAS_DEBUG_VIRTUAL if MMU
9 select ARCH_HAS_DEVMEM_IS_ALLOWED
10 select ARCH_HAS_ELF_RANDOMIZE
11 select ARCH_HAS_FORTIFY_SOURCE
12 select ARCH_HAS_KEEPINITRD
14 select ARCH_HAS_MEMBARRIER_SYNC_CORE
15 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
16 select ARCH_HAS_PHYS_TO_DMA
17 select ARCH_HAS_SETUP_DMA_OPS
18 select ARCH_HAS_SET_MEMORY
19 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
20 select ARCH_HAS_STRICT_MODULE_RWX if MMU
21 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
22 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
23 select ARCH_HAVE_CUSTOM_GPIO_H
24 select ARCH_HAS_GCOV_PROFILE_ALL
25 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC
26 select ARCH_MIGHT_HAVE_PC_PARPORT
27 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
28 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
29 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
30 select ARCH_SUPPORTS_ATOMIC_RMW
31 select ARCH_USE_BUILTIN_BSWAP
32 select ARCH_USE_CMPXCHG_LOCKREF
33 select ARCH_WANT_IPC_PARSE_VERSION
34 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
35 select BUILDTIME_EXTABLE_SORT if MMU
36 select CLONE_BACKWARDS
37 select CPU_PM if SUSPEND || CPU_IDLE
38 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
39 select DMA_DECLARE_COHERENT
40 select DMA_REMAP if MMU
42 select EDAC_ATOMIC_SCRUB
43 select GENERIC_ALLOCATOR
44 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
45 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
46 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
47 select GENERIC_CPU_AUTOPROBE
48 select GENERIC_EARLY_IOREMAP
49 select GENERIC_IDLE_POLL_SETUP
50 select GENERIC_IRQ_PROBE
51 select GENERIC_IRQ_SHOW
52 select GENERIC_IRQ_SHOW_LEVEL
53 select GENERIC_PCI_IOMAP
54 select GENERIC_SCHED_CLOCK
55 select GENERIC_SMP_IDLE_THREAD
56 select GENERIC_STRNCPY_FROM_USER
57 select GENERIC_STRNLEN_USER
58 select HANDLE_DOMAIN_IRQ
59 select HARDIRQS_SW_RESEND
60 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
61 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
62 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
63 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
64 select HAVE_ARCH_MMAP_RND_BITS if MMU
65 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
66 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
67 select HAVE_ARCH_TRACEHOOK
68 select HAVE_ARM_SMCCC if CPU_V7
69 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
70 select HAVE_CONTEXT_TRACKING
71 select HAVE_C_RECORDMCOUNT
72 select HAVE_DEBUG_KMEMLEAK
73 select HAVE_DMA_CONTIGUOUS if MMU
74 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
75 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
76 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
77 select HAVE_EXIT_THREAD
78 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
79 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
80 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
81 select HAVE_GCC_PLUGINS
82 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
83 select HAVE_IDE if PCI || ISA || PCMCIA
84 select HAVE_IRQ_TIME_ACCOUNTING
85 select HAVE_KERNEL_GZIP
86 select HAVE_KERNEL_LZ4
87 select HAVE_KERNEL_LZMA
88 select HAVE_KERNEL_LZO
90 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
91 select HAVE_KRETPROBES if HAVE_KPROBES
92 select HAVE_MOD_ARCH_SPECIFIC
94 select HAVE_OPROFILE if HAVE_PERF_EVENTS
95 select HAVE_OPTPROBES if !THUMB2_KERNEL
96 select HAVE_PERF_EVENTS
98 select HAVE_PERF_USER_STACK_DUMP
99 select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE
100 select HAVE_REGS_AND_STACK_ACCESS_API
102 select HAVE_STACKPROTECTOR
103 select HAVE_SYSCALL_TRACEPOINTS
105 select HAVE_VIRT_CPU_ACCOUNTING_GEN
106 select IRQ_FORCED_THREADING
107 select MODULES_USE_ELF_REL
108 select NEED_DMA_MAP_STATE
109 select OF_EARLY_FLATTREE if OF
111 select OLD_SIGSUSPEND3
112 select PCI_SYSCALL if PCI
113 select PERF_USE_VMALLOC
116 select SYS_SUPPORTS_APM_EMULATION
117 # Above selects are sorted alphabetically; please add new ones
118 # according to that. Thanks.
120 The ARM series is a line of low-power-consumption RISC chip designs
121 licensed by ARM Ltd and targeted at embedded applications and
122 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
123 manufactured, but legacy ARM-based PC hardware remains popular in
124 Europe. There is an ARM Linux project with a web page at
125 <http://www.arm.linux.org.uk/>.
127 config ARM_HAS_SG_CHAIN
130 config ARM_DMA_USE_IOMMU
132 select ARM_HAS_SG_CHAIN
133 select NEED_SG_DMA_LENGTH
137 config ARM_DMA_IOMMU_ALIGNMENT
138 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
142 DMA mapping framework by default aligns all buffers to the smallest
143 PAGE_SIZE order which is greater than or equal to the requested buffer
144 size. This works well for buffers up to a few hundreds kilobytes, but
145 for larger buffers it just a waste of address space. Drivers which has
146 relatively small addressing window (like 64Mib) might run out of
147 virtual space with just a few allocations.
149 With this parameter you can specify the maximum PAGE_SIZE order for
150 DMA IOMMU buffers. Larger buffers will be aligned only to this
151 specified order. The order is expressed as a power of two multiplied
156 config SYS_SUPPORTS_APM_EMULATION
161 select GENERIC_ALLOCATOR
172 config STACKTRACE_SUPPORT
176 config LOCKDEP_SUPPORT
180 config TRACE_IRQFLAGS_SUPPORT
184 config ARCH_HAS_ILOG2_U32
187 config ARCH_HAS_ILOG2_U64
190 config ARCH_HAS_BANDGAP
193 config FIX_EARLYCON_MEM
196 config GENERIC_HWEIGHT
200 config GENERIC_CALIBRATE_DELAY
204 config ARCH_MAY_HAVE_PC_FDC
210 config ARCH_SUPPORTS_UPROBES
213 config ARCH_HAS_DMA_SET_COHERENT_MASK
216 config GENERIC_ISA_DMA
222 config NEED_RET_TO_USER
228 config ARM_PATCH_PHYS_VIRT
229 bool "Patch physical to virtual translations at runtime" if EMBEDDED
231 depends on !XIP_KERNEL && MMU
233 Patch phys-to-virt and virt-to-phys translation functions at
234 boot and module load time according to the position of the
235 kernel in system memory.
237 This can only be used with non-XIP MMU kernels where the base
238 of physical memory is at a 16MB boundary.
240 Only disable this option if you know that you do not require
241 this feature (eg, building a kernel for a single machine) and
242 you need to shrink the kernel to the minimal size.
244 config NEED_MACH_IO_H
247 Select this when mach/io.h is required to provide special
248 definitions for this platform. The need for mach/io.h should
249 be avoided when possible.
251 config NEED_MACH_MEMORY_H
254 Select this when mach/memory.h is required to provide special
255 definitions for this platform. The need for mach/memory.h should
256 be avoided when possible.
259 hex "Physical address of main memory" if MMU
260 depends on !ARM_PATCH_PHYS_VIRT
261 default DRAM_BASE if !MMU
262 default 0x00000000 if ARCH_EBSA110 || \
268 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
269 default 0x20000000 if ARCH_S5PV210
270 default 0xc0000000 if ARCH_SA1100
272 Please provide the physical address corresponding to the
273 location of main memory in your system.
279 config PGTABLE_LEVELS
281 default 3 if ARM_LPAE
287 bool "MMU-based Paged Memory Management Support"
290 Select if you want MMU-based virtualised addressing space
291 support by paged memory management. If unsure, say 'Y'.
293 config ARCH_MMAP_RND_BITS_MIN
296 config ARCH_MMAP_RND_BITS_MAX
297 default 14 if PAGE_OFFSET=0x40000000
298 default 15 if PAGE_OFFSET=0x80000000
302 # The "ARM system type" choice list is ordered alphabetically by option
303 # text. Please add new entries in the option alphabetic order.
306 prompt "ARM system type"
307 default ARM_SINGLE_ARMV7M if !MMU
308 default ARCH_MULTIPLATFORM if MMU
310 config ARCH_MULTIPLATFORM
311 bool "Allow multiple platforms to be selected"
313 select ARM_HAS_SG_CHAIN
314 select ARM_PATCH_PHYS_VIRT
318 select GENERIC_CLOCKEVENTS
319 select GENERIC_IRQ_MULTI_HANDLER
321 select PCI_DOMAINS_GENERIC if PCI
325 config ARM_SINGLE_ARMV7M
326 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
333 select GENERIC_CLOCKEVENTS
340 select ARCH_USES_GETTIMEOFFSET
343 select NEED_MACH_IO_H
344 select NEED_MACH_MEMORY_H
347 This is an evaluation board for the StrongARM processor available
348 from Digital. It has limited hardware on-board, including an
349 Ethernet interface, two PCMCIA sockets, two serial ports and a
354 select ARCH_SPARSEMEM_ENABLE
356 imply ARM_PATCH_PHYS_VIRT
362 select GENERIC_CLOCKEVENTS
365 This enables support for the Cirrus EP93xx series of CPUs.
367 config ARCH_FOOTBRIDGE
371 select GENERIC_CLOCKEVENTS
373 select NEED_MACH_IO_H if !MMU
374 select NEED_MACH_MEMORY_H
376 Support for systems based on the DC21285 companion chip
377 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
380 bool "Hilscher NetX based"
384 select GENERIC_CLOCKEVENTS
386 This enables support for systems based on the Hilscher NetX Soc
392 select NEED_MACH_MEMORY_H
393 select NEED_RET_TO_USER
399 Support for Intel's IOP13XX (XScale) family of processors.
407 select NEED_RET_TO_USER
411 Support for Intel's 80219 and IOP32X (XScale) family of
420 select NEED_RET_TO_USER
424 Support for Intel's IOP33X (XScale) family of processors.
429 select ARCH_HAS_DMA_SET_COHERENT_MASK
430 select ARCH_SUPPORTS_BIG_ENDIAN
432 select DMABOUNCE if PCI
433 select GENERIC_CLOCKEVENTS
434 select GENERIC_IRQ_MULTI_HANDLER
440 select NEED_MACH_IO_H
441 select USB_EHCI_BIG_ENDIAN_DESC
442 select USB_EHCI_BIG_ENDIAN_MMIO
444 Support for Intel's IXP4XX (XScale) family of processors.
449 select GENERIC_CLOCKEVENTS
450 select GENERIC_IRQ_MULTI_HANDLER
456 select PLAT_ORION_LEGACY
458 select PM_GENERIC_DOMAINS if PM
460 Support for the Marvell Dove SoC 88AP510
463 bool "Micrel/Kendin KS8695"
466 select GENERIC_CLOCKEVENTS
468 select NEED_MACH_MEMORY_H
470 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
471 System-on-Chip devices.
474 bool "Nuvoton W90X900 CPU"
478 select GENERIC_CLOCKEVENTS
481 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
482 At present, the w90x900 has been renamed nuc900, regarding
483 the ARM series product line, you can login the following
484 link address to know more.
486 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
487 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
493 select CLKSRC_LPC32XX
496 select GENERIC_CLOCKEVENTS
497 select GENERIC_IRQ_MULTI_HANDLER
502 Support for the NXP LPC32XX family of processors
505 bool "PXA2xx/PXA3xx-based"
508 select ARM_CPU_SUSPEND if PM
515 select CPU_XSCALE if !CPU_XSC3
516 select GENERIC_CLOCKEVENTS
517 select GENERIC_IRQ_MULTI_HANDLER
525 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
531 select ARCH_MAY_HAVE_PC_FDC
532 select ARCH_SPARSEMEM_ENABLE
533 select ARCH_USES_GETTIMEOFFSET
537 select HAVE_PATA_PLATFORM
539 select NEED_MACH_IO_H
540 select NEED_MACH_MEMORY_H
543 On the Acorn Risc-PC, Linux can support the internal IDE disk and
544 CD-ROM interface, serial and parallel port, and the floppy drive.
549 select ARCH_SPARSEMEM_ENABLE
553 select TIMER_OF if OF
556 select GENERIC_CLOCKEVENTS
557 select GENERIC_IRQ_MULTI_HANDLER
562 select NEED_MACH_MEMORY_H
565 Support for StrongARM 11x0 based boards.
568 bool "Samsung S3C24XX SoCs"
571 select CLKSRC_SAMSUNG_PWM
572 select GENERIC_CLOCKEVENTS
575 select GENERIC_IRQ_MULTI_HANDLER
576 select HAVE_S3C2410_I2C if I2C
577 select HAVE_S3C2410_WATCHDOG if WATCHDOG
578 select HAVE_S3C_RTC if RTC_CLASS
579 select NEED_MACH_IO_H
583 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
584 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
585 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
586 Samsung SMDK2410 development board (and derivatives).
590 select ARCH_HAS_HOLES_MEMORYMODEL
593 select GENERIC_ALLOCATOR
594 select GENERIC_CLOCKEVENTS
595 select GENERIC_IRQ_CHIP
596 select GENERIC_IRQ_MULTI_HANDLER
599 select PM_GENERIC_DOMAINS if PM
600 select PM_GENERIC_DOMAINS_OF if PM && OF
602 select RESET_CONTROLLER
607 Support for TI's DaVinci platform.
612 select ARCH_HAS_HOLES_MEMORYMODEL
616 select GENERIC_CLOCKEVENTS
617 select GENERIC_IRQ_CHIP
618 select GENERIC_IRQ_MULTI_HANDLER
622 select NEED_MACH_IO_H if PCCARD
623 select NEED_MACH_MEMORY_H
626 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
630 menu "Multiple platform selection"
631 depends on ARCH_MULTIPLATFORM
633 comment "CPU Core family selection"
636 bool "ARMv4 based platforms (FA526)"
637 depends on !ARCH_MULTI_V6_V7
638 select ARCH_MULTI_V4_V5
641 config ARCH_MULTI_V4T
642 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
643 depends on !ARCH_MULTI_V6_V7
644 select ARCH_MULTI_V4_V5
645 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
646 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
647 CPU_ARM925T || CPU_ARM940T)
650 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
651 depends on !ARCH_MULTI_V6_V7
652 select ARCH_MULTI_V4_V5
653 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
654 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
655 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
657 config ARCH_MULTI_V4_V5
661 bool "ARMv6 based platforms (ARM11)"
662 select ARCH_MULTI_V6_V7
666 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
668 select ARCH_MULTI_V6_V7
672 config ARCH_MULTI_V6_V7
674 select MIGHT_HAVE_CACHE_L2X0
676 config ARCH_MULTI_CPU_AUTO
677 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
683 bool "Dummy Virtual Machine"
684 depends on ARCH_MULTI_V7
687 select ARM_GIC_V2M if PCI
689 select ARM_GIC_V3_ITS if PCI
691 select HAVE_ARM_ARCH_TIMER
692 select ARCH_SUPPORTS_BIG_ENDIAN
695 # This is sorted alphabetically by mach-* pathname. However, plat-*
696 # Kconfigs may be included either alphabetically (according to the
697 # plat- suffix) or along side the corresponding mach-* source.
699 source "arch/arm/mach-actions/Kconfig"
701 source "arch/arm/mach-alpine/Kconfig"
703 source "arch/arm/mach-artpec/Kconfig"
705 source "arch/arm/mach-asm9260/Kconfig"
707 source "arch/arm/mach-aspeed/Kconfig"
709 source "arch/arm/mach-at91/Kconfig"
711 source "arch/arm/mach-axxia/Kconfig"
713 source "arch/arm/mach-bcm/Kconfig"
715 source "arch/arm/mach-berlin/Kconfig"
717 source "arch/arm/mach-clps711x/Kconfig"
719 source "arch/arm/mach-cns3xxx/Kconfig"
721 source "arch/arm/mach-davinci/Kconfig"
723 source "arch/arm/mach-digicolor/Kconfig"
725 source "arch/arm/mach-dove/Kconfig"
727 source "arch/arm/mach-ep93xx/Kconfig"
729 source "arch/arm/mach-exynos/Kconfig"
730 source "arch/arm/plat-samsung/Kconfig"
732 source "arch/arm/mach-footbridge/Kconfig"
734 source "arch/arm/mach-gemini/Kconfig"
736 source "arch/arm/mach-highbank/Kconfig"
738 source "arch/arm/mach-hisi/Kconfig"
740 source "arch/arm/mach-imx/Kconfig"
742 source "arch/arm/mach-integrator/Kconfig"
744 source "arch/arm/mach-iop13xx/Kconfig"
746 source "arch/arm/mach-iop32x/Kconfig"
748 source "arch/arm/mach-iop33x/Kconfig"
750 source "arch/arm/mach-ixp4xx/Kconfig"
752 source "arch/arm/mach-keystone/Kconfig"
754 source "arch/arm/mach-ks8695/Kconfig"
756 source "arch/arm/mach-mediatek/Kconfig"
758 source "arch/arm/mach-meson/Kconfig"
760 source "arch/arm/mach-milbeaut/Kconfig"
762 source "arch/arm/mach-mmp/Kconfig"
764 source "arch/arm/mach-moxart/Kconfig"
766 source "arch/arm/mach-mv78xx0/Kconfig"
768 source "arch/arm/mach-mvebu/Kconfig"
770 source "arch/arm/mach-mxs/Kconfig"
772 source "arch/arm/mach-netx/Kconfig"
774 source "arch/arm/mach-nomadik/Kconfig"
776 source "arch/arm/mach-npcm/Kconfig"
778 source "arch/arm/mach-nspire/Kconfig"
780 source "arch/arm/plat-omap/Kconfig"
782 source "arch/arm/mach-omap1/Kconfig"
784 source "arch/arm/mach-omap2/Kconfig"
786 source "arch/arm/mach-orion5x/Kconfig"
788 source "arch/arm/mach-oxnas/Kconfig"
790 source "arch/arm/mach-picoxcell/Kconfig"
792 source "arch/arm/mach-prima2/Kconfig"
794 source "arch/arm/mach-pxa/Kconfig"
795 source "arch/arm/plat-pxa/Kconfig"
797 source "arch/arm/mach-qcom/Kconfig"
799 source "arch/arm/mach-rda/Kconfig"
801 source "arch/arm/mach-realview/Kconfig"
803 source "arch/arm/mach-rockchip/Kconfig"
805 source "arch/arm/mach-s3c24xx/Kconfig"
807 source "arch/arm/mach-s3c64xx/Kconfig"
809 source "arch/arm/mach-s5pv210/Kconfig"
811 source "arch/arm/mach-sa1100/Kconfig"
813 source "arch/arm/mach-shmobile/Kconfig"
815 source "arch/arm/mach-socfpga/Kconfig"
817 source "arch/arm/mach-spear/Kconfig"
819 source "arch/arm/mach-sti/Kconfig"
821 source "arch/arm/mach-stm32/Kconfig"
823 source "arch/arm/mach-sunxi/Kconfig"
825 source "arch/arm/mach-tango/Kconfig"
827 source "arch/arm/mach-tegra/Kconfig"
829 source "arch/arm/mach-u300/Kconfig"
831 source "arch/arm/mach-uniphier/Kconfig"
833 source "arch/arm/mach-ux500/Kconfig"
835 source "arch/arm/mach-versatile/Kconfig"
837 source "arch/arm/mach-vexpress/Kconfig"
838 source "arch/arm/plat-versatile/Kconfig"
840 source "arch/arm/mach-vt8500/Kconfig"
842 source "arch/arm/mach-w90x900/Kconfig"
844 source "arch/arm/mach-zx/Kconfig"
846 source "arch/arm/mach-zynq/Kconfig"
848 # ARMv7-M architecture
850 bool "Energy Micro efm32"
851 depends on ARM_SINGLE_ARMV7M
854 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
858 bool "NXP LPC18xx/LPC43xx"
859 depends on ARM_SINGLE_ARMV7M
860 select ARCH_HAS_RESET_CONTROLLER
862 select CLKSRC_LPC32XX
865 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
866 high performance microcontrollers.
869 bool "ARM MPS2 platform"
870 depends on ARM_SINGLE_ARMV7M
874 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
875 with a range of available cores like Cortex-M3/M4/M7.
877 Please, note that depends which Application Note is used memory map
878 for the platform may vary, so adjustment of RAM base might be needed.
880 # Definitions to make life easier
886 select GENERIC_CLOCKEVENTS
892 select GENERIC_IRQ_CHIP
895 config PLAT_ORION_LEGACY
902 config PLAT_VERSATILE
905 source "arch/arm/mm/Kconfig"
908 bool "Enable iWMMXt support"
909 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
910 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
912 Enable support for iWMMXt context switching at run time if
913 running on a CPU that supports it.
916 source "arch/arm/Kconfig-nommu"
919 config PJ4B_ERRATA_4742
920 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
921 depends on CPU_PJ4B && MACH_ARMADA_370
924 When coming out of either a Wait for Interrupt (WFI) or a Wait for
925 Event (WFE) IDLE states, a specific timing sensitivity exists between
926 the retiring WFI/WFE instructions and the newly issued subsequent
927 instructions. This sensitivity can result in a CPU hang scenario.
929 The software must insert either a Data Synchronization Barrier (DSB)
930 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
933 config ARM_ERRATA_326103
934 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
937 Executing a SWP instruction to read-only memory does not set bit 11
938 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
939 treat the access as a read, preventing a COW from occurring and
940 causing the faulting task to livelock.
942 config ARM_ERRATA_411920
943 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
944 depends on CPU_V6 || CPU_V6K
946 Invalidation of the Instruction Cache operation can
947 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
948 It does not affect the MPCore. This option enables the ARM Ltd.
949 recommended workaround.
951 config ARM_ERRATA_430973
952 bool "ARM errata: Stale prediction on replaced interworking branch"
955 This option enables the workaround for the 430973 Cortex-A8
956 r1p* erratum. If a code sequence containing an ARM/Thumb
957 interworking branch is replaced with another code sequence at the
958 same virtual address, whether due to self-modifying code or virtual
959 to physical address re-mapping, Cortex-A8 does not recover from the
960 stale interworking branch prediction. This results in Cortex-A8
961 executing the new code sequence in the incorrect ARM or Thumb state.
962 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
963 and also flushes the branch target cache at every context switch.
964 Note that setting specific bits in the ACTLR register may not be
965 available in non-secure mode.
967 config ARM_ERRATA_458693
968 bool "ARM errata: Processor deadlock when a false hazard is created"
970 depends on !ARCH_MULTIPLATFORM
972 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
973 erratum. For very specific sequences of memory operations, it is
974 possible for a hazard condition intended for a cache line to instead
975 be incorrectly associated with a different cache line. This false
976 hazard might then cause a processor deadlock. The workaround enables
977 the L1 caching of the NEON accesses and disables the PLD instruction
978 in the ACTLR register. Note that setting specific bits in the ACTLR
979 register may not be available in non-secure mode.
981 config ARM_ERRATA_460075
982 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
984 depends on !ARCH_MULTIPLATFORM
986 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
987 erratum. Any asynchronous access to the L2 cache may encounter a
988 situation in which recent store transactions to the L2 cache are lost
989 and overwritten with stale memory contents from external memory. The
990 workaround disables the write-allocate mode for the L2 cache via the
991 ACTLR register. Note that setting specific bits in the ACTLR register
992 may not be available in non-secure mode.
994 config ARM_ERRATA_742230
995 bool "ARM errata: DMB operation may be faulty"
996 depends on CPU_V7 && SMP
997 depends on !ARCH_MULTIPLATFORM
999 This option enables the workaround for the 742230 Cortex-A9
1000 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1001 between two write operations may not ensure the correct visibility
1002 ordering of the two writes. This workaround sets a specific bit in
1003 the diagnostic register of the Cortex-A9 which causes the DMB
1004 instruction to behave as a DSB, ensuring the correct behaviour of
1007 config ARM_ERRATA_742231
1008 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1009 depends on CPU_V7 && SMP
1010 depends on !ARCH_MULTIPLATFORM
1012 This option enables the workaround for the 742231 Cortex-A9
1013 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1014 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1015 accessing some data located in the same cache line, may get corrupted
1016 data due to bad handling of the address hazard when the line gets
1017 replaced from one of the CPUs at the same time as another CPU is
1018 accessing it. This workaround sets specific bits in the diagnostic
1019 register of the Cortex-A9 which reduces the linefill issuing
1020 capabilities of the processor.
1022 config ARM_ERRATA_643719
1023 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1024 depends on CPU_V7 && SMP
1027 This option enables the workaround for the 643719 Cortex-A9 (prior to
1028 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1029 register returns zero when it should return one. The workaround
1030 corrects this value, ensuring cache maintenance operations which use
1031 it behave as intended and avoiding data corruption.
1033 config ARM_ERRATA_720789
1034 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1037 This option enables the workaround for the 720789 Cortex-A9 (prior to
1038 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1039 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1040 As a consequence of this erratum, some TLB entries which should be
1041 invalidated are not, resulting in an incoherency in the system page
1042 tables. The workaround changes the TLB flushing routines to invalidate
1043 entries regardless of the ASID.
1045 config ARM_ERRATA_743622
1046 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1048 depends on !ARCH_MULTIPLATFORM
1050 This option enables the workaround for the 743622 Cortex-A9
1051 (r2p*) erratum. Under very rare conditions, a faulty
1052 optimisation in the Cortex-A9 Store Buffer may lead to data
1053 corruption. This workaround sets a specific bit in the diagnostic
1054 register of the Cortex-A9 which disables the Store Buffer
1055 optimisation, preventing the defect from occurring. This has no
1056 visible impact on the overall performance or power consumption of the
1059 config ARM_ERRATA_751472
1060 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1062 depends on !ARCH_MULTIPLATFORM
1064 This option enables the workaround for the 751472 Cortex-A9 (prior
1065 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1066 completion of a following broadcasted operation if the second
1067 operation is received by a CPU before the ICIALLUIS has completed,
1068 potentially leading to corrupted entries in the cache or TLB.
1070 config ARM_ERRATA_754322
1071 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1074 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1075 r3p*) erratum. A speculative memory access may cause a page table walk
1076 which starts prior to an ASID switch but completes afterwards. This
1077 can populate the micro-TLB with a stale entry which may be hit with
1078 the new ASID. This workaround places two dsb instructions in the mm
1079 switching code so that no page table walks can cross the ASID switch.
1081 config ARM_ERRATA_754327
1082 bool "ARM errata: no automatic Store Buffer drain"
1083 depends on CPU_V7 && SMP
1085 This option enables the workaround for the 754327 Cortex-A9 (prior to
1086 r2p0) erratum. The Store Buffer does not have any automatic draining
1087 mechanism and therefore a livelock may occur if an external agent
1088 continuously polls a memory location waiting to observe an update.
1089 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1090 written polling loops from denying visibility of updates to memory.
1092 config ARM_ERRATA_364296
1093 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1096 This options enables the workaround for the 364296 ARM1136
1097 r0p2 erratum (possible cache data corruption with
1098 hit-under-miss enabled). It sets the undocumented bit 31 in
1099 the auxiliary control register and the FI bit in the control
1100 register, thus disabling hit-under-miss without putting the
1101 processor into full low interrupt latency mode. ARM11MPCore
1104 config ARM_ERRATA_764369
1105 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1106 depends on CPU_V7 && SMP
1108 This option enables the workaround for erratum 764369
1109 affecting Cortex-A9 MPCore with two or more processors (all
1110 current revisions). Under certain timing circumstances, a data
1111 cache line maintenance operation by MVA targeting an Inner
1112 Shareable memory region may fail to proceed up to either the
1113 Point of Coherency or to the Point of Unification of the
1114 system. This workaround adds a DSB instruction before the
1115 relevant cache maintenance functions and sets a specific bit
1116 in the diagnostic control register of the SCU.
1118 config ARM_ERRATA_775420
1119 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1122 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1123 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1124 operation aborts with MMU exception, it might cause the processor
1125 to deadlock. This workaround puts DSB before executing ISB if
1126 an abort may occur on cache maintenance.
1128 config ARM_ERRATA_798181
1129 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1130 depends on CPU_V7 && SMP
1132 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1133 adequately shooting down all use of the old entries. This
1134 option enables the Linux kernel workaround for this erratum
1135 which sends an IPI to the CPUs that are running the same ASID
1136 as the one being invalidated.
1138 config ARM_ERRATA_773022
1139 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1142 This option enables the workaround for the 773022 Cortex-A15
1143 (up to r0p4) erratum. In certain rare sequences of code, the
1144 loop buffer may deliver incorrect instructions. This
1145 workaround disables the loop buffer to avoid the erratum.
1147 config ARM_ERRATA_818325_852422
1148 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1151 This option enables the workaround for:
1152 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1153 instruction might deadlock. Fixed in r0p1.
1154 - Cortex-A12 852422: Execution of a sequence of instructions might
1155 lead to either a data corruption or a CPU deadlock. Not fixed in
1156 any Cortex-A12 cores yet.
1157 This workaround for all both errata involves setting bit[12] of the
1158 Feature Register. This bit disables an optimisation applied to a
1159 sequence of 2 instructions that use opposing condition codes.
1161 config ARM_ERRATA_821420
1162 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1165 This option enables the workaround for the 821420 Cortex-A12
1166 (all revs) erratum. In very rare timing conditions, a sequence
1167 of VMOV to Core registers instructions, for which the second
1168 one is in the shadow of a branch or abort, can lead to a
1169 deadlock when the VMOV instructions are issued out-of-order.
1171 config ARM_ERRATA_825619
1172 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1175 This option enables the workaround for the 825619 Cortex-A12
1176 (all revs) erratum. Within rare timing constraints, executing a
1177 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1178 and Device/Strongly-Ordered loads and stores might cause deadlock
1180 config ARM_ERRATA_857271
1181 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1184 This option enables the workaround for the 857271 Cortex-A12
1185 (all revs) erratum. Under very rare timing conditions, the CPU might
1186 hang. The workaround is expected to have a < 1% performance impact.
1188 config ARM_ERRATA_852421
1189 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1192 This option enables the workaround for the 852421 Cortex-A17
1193 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1194 execution of a DMB ST instruction might fail to properly order
1195 stores from GroupA and stores from GroupB.
1197 config ARM_ERRATA_852423
1198 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1201 This option enables the workaround for:
1202 - Cortex-A17 852423: Execution of a sequence of instructions might
1203 lead to either a data corruption or a CPU deadlock. Not fixed in
1204 any Cortex-A17 cores yet.
1205 This is identical to Cortex-A12 erratum 852422. It is a separate
1206 config option from the A12 erratum due to the way errata are checked
1209 config ARM_ERRATA_857272
1210 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1213 This option enables the workaround for the 857272 Cortex-A17 erratum.
1214 This erratum is not known to be fixed in any A17 revision.
1215 This is identical to Cortex-A12 erratum 857271. It is a separate
1216 config option from the A12 erratum due to the way errata are checked
1221 source "arch/arm/common/Kconfig"
1228 Find out whether you have ISA slots on your motherboard. ISA is the
1229 name of a bus system, i.e. the way the CPU talks to the other stuff
1230 inside your box. Other bus systems are PCI, EISA, MicroChannel
1231 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1232 newer boards don't support it. If you have ISA, say Y, otherwise N.
1234 # Select ISA DMA controller support
1239 # Select ISA DMA interface
1243 config PCI_NANOENGINE
1244 bool "BSE nanoEngine PCI support"
1245 depends on SA1100_NANOENGINE
1247 Enable PCI on the BSE nanoEngine board.
1249 config PCI_HOST_ITE8152
1251 depends on PCI && MACH_ARMCORE
1255 config ARM_ERRATA_814220
1256 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1259 The v7 ARM states that all cache and branch predictor maintenance
1260 operations that do not specify an address execute, relative to
1261 each other, in program order.
1262 However, because of this erratum, an L2 set/way cache maintenance
1263 operation can overtake an L1 set/way cache maintenance operation.
1264 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1269 menu "Kernel Features"
1274 This option should be selected by machines which have an SMP-
1277 The only effect of this option is to make the SMP-related
1278 options available to the user for configuration.
1281 bool "Symmetric Multi-Processing"
1282 depends on CPU_V6K || CPU_V7
1283 depends on GENERIC_CLOCKEVENTS
1285 depends on MMU || ARM_MPU
1288 This enables support for systems with more than one CPU. If you have
1289 a system with only one CPU, say N. If you have a system with more
1290 than one CPU, say Y.
1292 If you say N here, the kernel will run on uni- and multiprocessor
1293 machines, but will use only one CPU of a multiprocessor machine. If
1294 you say Y here, the kernel will run on many, but not all,
1295 uniprocessor machines. On a uniprocessor machine, the kernel
1296 will run faster if you say N here.
1298 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1299 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at
1300 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1302 If you don't know what to do here, say N.
1305 bool "Allow booting SMP kernel on uniprocessor systems"
1306 depends on SMP && !XIP_KERNEL && MMU
1309 SMP kernels contain instructions which fail on non-SMP processors.
1310 Enabling this option allows the kernel to modify itself to make
1311 these instructions safe. Disabling it allows about 1K of space
1314 If you don't know what to do here, say Y.
1316 config ARM_CPU_TOPOLOGY
1317 bool "Support cpu topology definition"
1318 depends on SMP && CPU_V7
1321 Support ARM cpu topology definition. The MPIDR register defines
1322 affinity between processors which is then used to describe the cpu
1323 topology of an ARM System.
1326 bool "Multi-core scheduler support"
1327 depends on ARM_CPU_TOPOLOGY
1329 Multi-core scheduler support improves the CPU scheduler's decision
1330 making when dealing with multi-core CPU chips at a cost of slightly
1331 increased overhead in some places. If unsure say N here.
1334 bool "SMT scheduler support"
1335 depends on ARM_CPU_TOPOLOGY
1337 Improves the CPU scheduler's decision making when dealing with
1338 MultiThreading at a cost of slightly increased overhead in some
1339 places. If unsure say N here.
1344 This option enables support for the ARM snoop control unit
1346 config HAVE_ARM_ARCH_TIMER
1347 bool "Architected timer support"
1349 select ARM_ARCH_TIMER
1350 select GENERIC_CLOCKEVENTS
1352 This option enables support for the ARM architected timer
1357 This options enables support for the ARM timer and watchdog unit
1360 bool "Multi-Cluster Power Management"
1361 depends on CPU_V7 && SMP
1363 This option provides the common power management infrastructure
1364 for (multi-)cluster based systems, such as big.LITTLE based
1367 config MCPM_QUAD_CLUSTER
1371 To avoid wasting resources unnecessarily, MCPM only supports up
1372 to 2 clusters by default.
1373 Platforms with 3 or 4 clusters that use MCPM must select this
1374 option to allow the additional clusters to be managed.
1377 bool "big.LITTLE support (Experimental)"
1378 depends on CPU_V7 && SMP
1381 This option enables support selections for the big.LITTLE
1382 system architecture.
1385 bool "big.LITTLE switcher support"
1386 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1389 The big.LITTLE "switcher" provides the core functionality to
1390 transparently handle transition between a cluster of A15's
1391 and a cluster of A7's in a big.LITTLE system.
1393 config BL_SWITCHER_DUMMY_IF
1394 tristate "Simple big.LITTLE switcher user interface"
1395 depends on BL_SWITCHER && DEBUG_KERNEL
1397 This is a simple and dummy char dev interface to control
1398 the big.LITTLE switcher core code. It is meant for
1399 debugging purposes only.
1402 prompt "Memory split"
1406 Select the desired split between kernel and user memory.
1408 If you are not absolutely sure what you are doing, leave this
1412 bool "3G/1G user/kernel split"
1413 config VMSPLIT_3G_OPT
1414 depends on !ARM_LPAE
1415 bool "3G/1G user/kernel split (for full 1G low memory)"
1417 bool "2G/2G user/kernel split"
1419 bool "1G/3G user/kernel split"
1424 default PHYS_OFFSET if !MMU
1425 default 0x40000000 if VMSPLIT_1G
1426 default 0x80000000 if VMSPLIT_2G
1427 default 0xB0000000 if VMSPLIT_3G_OPT
1431 int "Maximum number of CPUs (2-32)"
1437 bool "Support for hot-pluggable CPUs"
1439 select GENERIC_IRQ_MIGRATION
1441 Say Y here to experiment with turning CPUs off and on. CPUs
1442 can be controlled through /sys/devices/system/cpu.
1445 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1446 depends on HAVE_ARM_SMCCC
1449 Say Y here if you want Linux to communicate with system firmware
1450 implementing the PSCI specification for CPU-centric power
1451 management operations described in ARM document number ARM DEN
1452 0022A ("Power State Coordination Interface System Software on
1455 # The GPIO number here must be sorted by descending number. In case of
1456 # a multiplatform kernel, we just want the highest value required by the
1457 # selected platforms.
1460 default 2048 if ARCH_SOCFPGA
1461 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1463 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1464 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1465 default 416 if ARCH_SUNXI
1466 default 392 if ARCH_U8500
1467 default 352 if ARCH_VT8500
1468 default 288 if ARCH_ROCKCHIP
1469 default 264 if MACH_H4700
1472 Maximum number of GPIOs in the system.
1474 If unsure, leave the default value.
1478 default 200 if ARCH_EBSA110
1479 default 128 if SOC_AT91RM9200
1483 depends on HZ_FIXED = 0
1484 prompt "Timer frequency"
1508 default HZ_FIXED if HZ_FIXED != 0
1509 default 100 if HZ_100
1510 default 200 if HZ_200
1511 default 250 if HZ_250
1512 default 300 if HZ_300
1513 default 500 if HZ_500
1517 def_bool HIGH_RES_TIMERS
1519 config THUMB2_KERNEL
1520 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1521 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1522 default y if CPU_THUMBONLY
1525 By enabling this option, the kernel will be compiled in
1530 config THUMB2_AVOID_R_ARM_THM_JUMP11
1531 bool "Work around buggy Thumb-2 short branch relocations in gas"
1532 depends on THUMB2_KERNEL && MODULES
1535 Various binutils versions can resolve Thumb-2 branches to
1536 locally-defined, preemptible global symbols as short-range "b.n"
1537 branch instructions.
1539 This is a problem, because there's no guarantee the final
1540 destination of the symbol, or any candidate locations for a
1541 trampoline, are within range of the branch. For this reason, the
1542 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1543 relocation in modules at all, and it makes little sense to add
1546 The symptom is that the kernel fails with an "unsupported
1547 relocation" error when loading some modules.
1549 Until fixed tools are available, passing
1550 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1551 code which hits this problem, at the cost of a bit of extra runtime
1552 stack usage in some cases.
1554 The problem is described in more detail at:
1555 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1557 Only Thumb-2 kernels are affected.
1559 Unless you are sure your tools don't have this problem, say Y.
1561 config ARM_PATCH_IDIV
1562 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1563 depends on CPU_32v7 && !XIP_KERNEL
1566 The ARM compiler inserts calls to __aeabi_idiv() and
1567 __aeabi_uidiv() when it needs to perform division on signed
1568 and unsigned integers. Some v7 CPUs have support for the sdiv
1569 and udiv instructions that can be used to implement those
1572 Enabling this option allows the kernel to modify itself to
1573 replace the first two instructions of these library functions
1574 with the sdiv or udiv plus "bx lr" instructions when the CPU
1575 it is running on supports them. Typically this will be faster
1576 and less power intensive than running the original library
1577 code to do integer division.
1580 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1581 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1583 This option allows for the kernel to be compiled using the latest
1584 ARM ABI (aka EABI). This is only useful if you are using a user
1585 space environment that is also compiled with EABI.
1587 Since there are major incompatibilities between the legacy ABI and
1588 EABI, especially with regard to structure member alignment, this
1589 option also changes the kernel syscall calling convention to
1590 disambiguate both ABIs and allow for backward compatibility support
1591 (selected with CONFIG_OABI_COMPAT).
1593 To use this you need GCC version 4.0.0 or later.
1596 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1597 depends on AEABI && !THUMB2_KERNEL
1599 This option preserves the old syscall interface along with the
1600 new (ARM EABI) one. It also provides a compatibility layer to
1601 intercept syscalls that have structure arguments which layout
1602 in memory differs between the legacy ABI and the new ARM EABI
1603 (only for non "thumb" binaries). This option adds a tiny
1604 overhead to all syscalls and produces a slightly larger kernel.
1606 The seccomp filter system will not be available when this is
1607 selected, since there is no way yet to sensibly distinguish
1608 between calling conventions during filtering.
1610 If you know you'll be using only pure EABI user space then you
1611 can say N here. If this option is not selected and you attempt
1612 to execute a legacy ABI binary then the result will be
1613 UNPREDICTABLE (in fact it can be predicted that it won't work
1614 at all). If in doubt say N.
1616 config ARCH_HAS_HOLES_MEMORYMODEL
1619 config ARCH_SPARSEMEM_ENABLE
1622 config ARCH_SPARSEMEM_DEFAULT
1623 def_bool ARCH_SPARSEMEM_ENABLE
1625 config ARCH_SELECT_MEMORY_MODEL
1626 def_bool ARCH_SPARSEMEM_ENABLE
1628 config HAVE_ARCH_PFN_VALID
1629 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1631 config HAVE_GENERIC_GUP
1636 bool "High Memory Support"
1639 The address space of ARM processors is only 4 Gigabytes large
1640 and it has to accommodate user address space, kernel address
1641 space as well as some memory mapped IO. That means that, if you
1642 have a large amount of physical memory and/or IO, not all of the
1643 memory can be "permanently mapped" by the kernel. The physical
1644 memory that is not permanently mapped is called "high memory".
1646 Depending on the selected kernel/user memory split, minimum
1647 vmalloc space and actual amount of RAM, you may not need this
1648 option which should result in a slightly faster kernel.
1653 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1657 The VM uses one page of physical memory for each page table.
1658 For systems with a lot of processes, this can use a lot of
1659 precious low memory, eventually leading to low memory being
1660 consumed by page tables. Setting this option will allow
1661 user-space 2nd level page tables to reside in high memory.
1663 config CPU_SW_DOMAIN_PAN
1664 bool "Enable use of CPU domains to implement privileged no-access"
1665 depends on MMU && !ARM_LPAE
1668 Increase kernel security by ensuring that normal kernel accesses
1669 are unable to access userspace addresses. This can help prevent
1670 use-after-free bugs becoming an exploitable privilege escalation
1671 by ensuring that magic values (such as LIST_POISON) will always
1672 fault when dereferenced.
1674 CPUs with low-vector mappings use a best-efforts implementation.
1675 Their lower 1MB needs to remain accessible for the vectors, but
1676 the remainder of userspace will become appropriately inaccessible.
1678 config HW_PERF_EVENTS
1682 config SYS_SUPPORTS_HUGETLBFS
1686 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1690 config ARCH_WANT_GENERAL_HUGETLB
1693 config ARM_MODULE_PLTS
1694 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1698 Allocate PLTs when loading modules so that jumps and calls whose
1699 targets are too far away for their relative offsets to be encoded
1700 in the instructions themselves can be bounced via veneers in the
1701 module's PLT. This allows modules to be allocated in the generic
1702 vmalloc area after the dedicated module memory area has been
1703 exhausted. The modules will use slightly more memory, but after
1704 rounding up to page size, the actual memory footprint is usually
1707 Disabling this is usually safe for small single-platform
1708 configurations. If unsure, say y.
1710 config FORCE_MAX_ZONEORDER
1711 int "Maximum zone order"
1712 default "12" if SOC_AM33XX
1713 default "9" if SA1111 || ARCH_EFM32
1716 The kernel memory allocator divides physically contiguous memory
1717 blocks into "zones", where each zone is a power of two number of
1718 pages. This option selects the largest power of two that the kernel
1719 keeps in the memory allocator. If you need to allocate very large
1720 blocks of physically contiguous memory, then you may need to
1721 increase this value.
1723 This config option is actually maximum order plus one. For example,
1724 a value of 11 means that the largest free memory block is 2^10 pages.
1726 config ALIGNMENT_TRAP
1728 depends on CPU_CP15_MMU
1729 default y if !ARCH_EBSA110
1730 select HAVE_PROC_CPU if PROC_FS
1732 ARM processors cannot fetch/store information which is not
1733 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1734 address divisible by 4. On 32-bit ARM processors, these non-aligned
1735 fetch/store instructions will be emulated in software if you say
1736 here, which has a severe performance impact. This is necessary for
1737 correct operation of some network protocols. With an IP-only
1738 configuration it is safe to say N, otherwise say Y.
1740 config UACCESS_WITH_MEMCPY
1741 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1743 default y if CPU_FEROCEON
1745 Implement faster copy_to_user and clear_user methods for CPU
1746 cores where a 8-word STM instruction give significantly higher
1747 memory write throughput than a sequence of individual 32bit stores.
1749 A possible side effect is a slight increase in scheduling latency
1750 between threads sharing the same address space if they invoke
1751 such copy operations with large buffers.
1753 However, if the CPU data cache is using a write-allocate mode,
1754 this option is unlikely to provide any performance gain.
1758 prompt "Enable seccomp to safely compute untrusted bytecode"
1760 This kernel feature is useful for number crunching applications
1761 that may need to compute untrusted bytecode during their
1762 execution. By using pipes or other transports made available to
1763 the process as file descriptors supporting the read/write
1764 syscalls, it's possible to isolate those applications in
1765 their own address space using seccomp. Once seccomp is
1766 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1767 and the task is only allowed to execute a few safe syscalls
1768 defined by each seccomp mode.
1771 bool "Enable paravirtualization code"
1773 This changes the kernel so it can modify itself when it is run
1774 under a hypervisor, potentially improving performance significantly
1775 over full virtualization.
1777 config PARAVIRT_TIME_ACCOUNTING
1778 bool "Paravirtual steal time accounting"
1781 Select this option to enable fine granularity task steal time
1782 accounting. Time spent executing other tasks in parallel with
1783 the current vCPU is discounted from the vCPU power. To account for
1784 that, there can be a small performance impact.
1786 If in doubt, say N here.
1793 bool "Xen guest support on ARM"
1794 depends on ARM && AEABI && OF
1795 depends on CPU_V7 && !CPU_V6
1796 depends on !GENERIC_ATOMIC64
1798 select ARCH_DMA_ADDR_T_64BIT
1804 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1806 config STACKPROTECTOR_PER_TASK
1807 bool "Use a unique stack canary value for each task"
1808 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1809 select GCC_PLUGIN_ARM_SSP_PER_TASK
1812 Due to the fact that GCC uses an ordinary symbol reference from
1813 which to load the value of the stack canary, this value can only
1814 change at reboot time on SMP systems, and all tasks running in the
1815 kernel's address space are forced to use the same canary value for
1816 the entire duration that the system is up.
1818 Enable this option to switch to a different method that uses a
1819 different canary value for each task.
1826 bool "Flattened Device Tree support"
1830 Include support for flattened device tree machine descriptions.
1833 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1836 This is the traditional way of passing data to the kernel at boot
1837 time. If you are solely relying on the flattened device tree (or
1838 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1839 to remove ATAGS support from your kernel binary. If unsure,
1842 config DEPRECATED_PARAM_STRUCT
1843 bool "Provide old way to pass kernel parameters"
1846 This was deprecated in 2001 and announced to live on for 5 years.
1847 Some old boot loaders still use this way.
1849 # Compressed boot loader in ROM. Yes, we really want to ask about
1850 # TEXT and BSS so we preserve their values in the config files.
1851 config ZBOOT_ROM_TEXT
1852 hex "Compressed ROM boot loader base address"
1855 The physical address at which the ROM-able zImage is to be
1856 placed in the target. Platforms which normally make use of
1857 ROM-able zImage formats normally set this to a suitable
1858 value in their defconfig file.
1860 If ZBOOT_ROM is not enabled, this has no effect.
1862 config ZBOOT_ROM_BSS
1863 hex "Compressed ROM boot loader BSS address"
1866 The base address of an area of read/write memory in the target
1867 for the ROM-able zImage which must be available while the
1868 decompressor is running. It must be large enough to hold the
1869 entire decompressed kernel plus an additional 128 KiB.
1870 Platforms which normally make use of ROM-able zImage formats
1871 normally set this to a suitable value in their defconfig file.
1873 If ZBOOT_ROM is not enabled, this has no effect.
1876 bool "Compressed boot loader in ROM/flash"
1877 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1878 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1880 Say Y here if you intend to execute your compressed kernel image
1881 (zImage) directly from ROM or flash. If unsure, say N.
1883 config ARM_APPENDED_DTB
1884 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1887 With this option, the boot code will look for a device tree binary
1888 (DTB) appended to zImage
1889 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1891 This is meant as a backward compatibility convenience for those
1892 systems with a bootloader that can't be upgraded to accommodate
1893 the documented boot protocol using a device tree.
1895 Beware that there is very little in terms of protection against
1896 this option being confused by leftover garbage in memory that might
1897 look like a DTB header after a reboot if no actual DTB is appended
1898 to zImage. Do not leave this option active in a production kernel
1899 if you don't intend to always append a DTB. Proper passing of the
1900 location into r2 of a bootloader provided DTB is always preferable
1903 config ARM_ATAG_DTB_COMPAT
1904 bool "Supplement the appended DTB with traditional ATAG information"
1905 depends on ARM_APPENDED_DTB
1907 Some old bootloaders can't be updated to a DTB capable one, yet
1908 they provide ATAGs with memory configuration, the ramdisk address,
1909 the kernel cmdline string, etc. Such information is dynamically
1910 provided by the bootloader and can't always be stored in a static
1911 DTB. To allow a device tree enabled kernel to be used with such
1912 bootloaders, this option allows zImage to extract the information
1913 from the ATAG list and store it at run time into the appended DTB.
1916 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1917 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1919 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1920 bool "Use bootloader kernel arguments if available"
1922 Uses the command-line options passed by the boot loader instead of
1923 the device tree bootargs property. If the boot loader doesn't provide
1924 any, the device tree bootargs property will be used.
1926 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1927 bool "Extend with bootloader kernel arguments"
1929 The command-line arguments provided by the boot loader will be
1930 appended to the the device tree bootargs property.
1935 string "Default kernel command string"
1938 On some architectures (EBSA110 and CATS), there is currently no way
1939 for the boot loader to pass arguments to the kernel. For these
1940 architectures, you should supply some command-line options at build
1941 time by entering them here. As a minimum, you should specify the
1942 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1945 prompt "Kernel command line type" if CMDLINE != ""
1946 default CMDLINE_FROM_BOOTLOADER
1949 config CMDLINE_FROM_BOOTLOADER
1950 bool "Use bootloader kernel arguments if available"
1952 Uses the command-line options passed by the boot loader. If
1953 the boot loader doesn't provide any, the default kernel command
1954 string provided in CMDLINE will be used.
1956 config CMDLINE_EXTEND
1957 bool "Extend bootloader kernel arguments"
1959 The command-line arguments provided by the boot loader will be
1960 appended to the default kernel command string.
1962 config CMDLINE_FORCE
1963 bool "Always use the default kernel command string"
1965 Always use the default kernel command string, even if the boot
1966 loader passes other arguments to the kernel.
1967 This is useful if you cannot or don't want to change the
1968 command-line options your boot loader passes to the kernel.
1972 bool "Kernel Execute-In-Place from ROM"
1973 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1975 Execute-In-Place allows the kernel to run from non-volatile storage
1976 directly addressable by the CPU, such as NOR flash. This saves RAM
1977 space since the text section of the kernel is not loaded from flash
1978 to RAM. Read-write sections, such as the data section and stack,
1979 are still copied to RAM. The XIP kernel is not compressed since
1980 it has to run directly from flash, so it will take more space to
1981 store it. The flash address used to link the kernel object files,
1982 and for storing it, is configuration dependent. Therefore, if you
1983 say Y here, you must know the proper physical address where to
1984 store the kernel image depending on your own flash memory usage.
1986 Also note that the make target becomes "make xipImage" rather than
1987 "make zImage" or "make Image". The final kernel binary to put in
1988 ROM memory will be arch/arm/boot/xipImage.
1992 config XIP_PHYS_ADDR
1993 hex "XIP Kernel Physical Location"
1994 depends on XIP_KERNEL
1995 default "0x00080000"
1997 This is the physical address in your flash memory the kernel will
1998 be linked for and stored to. This address is dependent on your
2001 config XIP_DEFLATED_DATA
2002 bool "Store kernel .data section compressed in ROM"
2003 depends on XIP_KERNEL
2006 Before the kernel is actually executed, its .data section has to be
2007 copied to RAM from ROM. This option allows for storing that data
2008 in compressed form and decompressed to RAM rather than merely being
2009 copied, saving some precious ROM space. A possible drawback is a
2010 slightly longer boot delay.
2013 bool "Kexec system call (EXPERIMENTAL)"
2014 depends on (!SMP || PM_SLEEP_SMP)
2018 kexec is a system call that implements the ability to shutdown your
2019 current kernel, and to start another kernel. It is like a reboot
2020 but it is independent of the system firmware. And like a reboot
2021 you can start any kernel with it, not just Linux.
2023 It is an ongoing process to be certain the hardware in a machine
2024 is properly shutdown, so do not be surprised if this code does not
2025 initially work for you.
2028 bool "Export atags in procfs"
2029 depends on ATAGS && KEXEC
2032 Should the atags used to boot the kernel be exported in an "atags"
2033 file in procfs. Useful with kexec.
2036 bool "Build kdump crash kernel (EXPERIMENTAL)"
2038 Generate crash dump after being started by kexec. This should
2039 be normally only set in special crash dump kernels which are
2040 loaded in the main kernel with kexec-tools into a specially
2041 reserved region and then later executed after a crash by
2042 kdump/kexec. The crash dump kernel must be compiled to a
2043 memory address not used by the main kernel
2045 For more details see Documentation/kdump/kdump.rst
2047 config AUTO_ZRELADDR
2048 bool "Auto calculation of the decompressed kernel image address"
2050 ZRELADDR is the physical address where the decompressed kernel
2051 image will be placed. If AUTO_ZRELADDR is selected, the address
2052 will be determined at run-time by masking the current IP with
2053 0xf8000000. This assumes the zImage being placed in the first 128MB
2054 from start of memory.
2060 bool "UEFI runtime support"
2061 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2063 select EFI_PARAMS_FROM_FDT
2066 select EFI_RUNTIME_WRAPPERS
2068 This option provides support for runtime services provided
2069 by UEFI firmware (such as non-volatile variables, realtime
2070 clock, and platform reset). A UEFI stub is also provided to
2071 allow the kernel to be booted as an EFI application. This
2072 is only useful for kernels that may run on systems that have
2076 bool "Enable support for SMBIOS (DMI) tables"
2080 This enables SMBIOS/DMI feature for systems.
2082 This option is only useful on systems that have UEFI firmware.
2083 However, even with this option, the resultant kernel should
2084 continue to boot on existing non-UEFI platforms.
2086 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2087 i.e., the the practice of identifying the platform via DMI to
2088 decide whether certain workarounds for buggy hardware and/or
2089 firmware need to be enabled. This would require the DMI subsystem
2090 to be enabled much earlier than we do on ARM, which is non-trivial.
2094 menu "CPU Power Management"
2096 source "drivers/cpufreq/Kconfig"
2098 source "drivers/cpuidle/Kconfig"
2102 menu "Floating point emulation"
2104 comment "At least one emulation must be selected"
2107 bool "NWFPE math emulation"
2108 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2110 Say Y to include the NWFPE floating point emulator in the kernel.
2111 This is necessary to run most binaries. Linux does not currently
2112 support floating point hardware so you need to say Y here even if
2113 your machine has an FPA or floating point co-processor podule.
2115 You may say N here if you are going to load the Acorn FPEmulator
2116 early in the bootup.
2119 bool "Support extended precision"
2120 depends on FPE_NWFPE
2122 Say Y to include 80-bit support in the kernel floating-point
2123 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2124 Note that gcc does not generate 80-bit operations by default,
2125 so in most cases this option only enlarges the size of the
2126 floating point emulator without any good reason.
2128 You almost surely want to say N here.
2131 bool "FastFPE math emulation (EXPERIMENTAL)"
2132 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2134 Say Y here to include the FAST floating point emulator in the kernel.
2135 This is an experimental much faster emulator which now also has full
2136 precision for the mantissa. It does not support any exceptions.
2137 It is very simple, and approximately 3-6 times faster than NWFPE.
2139 It should be sufficient for most programs. It may be not suitable
2140 for scientific calculations, but you have to check this for yourself.
2141 If you do not feel you need a faster FP emulation you should better
2145 bool "VFP-format floating point maths"
2146 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2148 Say Y to include VFP support code in the kernel. This is needed
2149 if your hardware includes a VFP unit.
2151 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2152 release notes and additional status information.
2154 Say N if your target does not have VFP hardware.
2162 bool "Advanced SIMD (NEON) Extension support"
2163 depends on VFPv3 && CPU_V7
2165 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2168 config KERNEL_MODE_NEON
2169 bool "Support for NEON in kernel mode"
2170 depends on NEON && AEABI
2172 Say Y to include support for NEON in kernel mode.
2176 menu "Power management options"
2178 source "kernel/power/Kconfig"
2180 config ARCH_SUSPEND_POSSIBLE
2181 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2182 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2185 config ARM_CPU_SUSPEND
2186 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2187 depends on ARCH_SUSPEND_POSSIBLE
2189 config ARCH_HIBERNATION_POSSIBLE
2192 default y if ARCH_SUSPEND_POSSIBLE
2196 source "drivers/firmware/Kconfig"
2199 source "arch/arm/crypto/Kconfig"
2202 source "arch/arm/kvm/Kconfig"