4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
29 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
30 select HAVE_ARCH_TRACEHOOK
32 select HAVE_CONTEXT_TRACKING
33 select HAVE_C_RECORDMCOUNT
34 select HAVE_CC_STACKPROTECTOR
35 select HAVE_DEBUG_KMEMLEAK
36 select HAVE_DMA_API_DEBUG
38 select HAVE_DMA_CONTIGUOUS if MMU
39 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
40 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
41 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
42 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
43 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
44 select HAVE_GENERIC_DMA_COHERENT
45 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
46 select HAVE_IDE if PCI || ISA || PCMCIA
47 select HAVE_IRQ_TIME_ACCOUNTING
48 select HAVE_KERNEL_GZIP
49 select HAVE_KERNEL_LZ4
50 select HAVE_KERNEL_LZMA
51 select HAVE_KERNEL_LZO
53 select HAVE_KPROBES if !XIP_KERNEL
54 select HAVE_KRETPROBES if (HAVE_KPROBES)
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
58 select HAVE_PERF_EVENTS
60 select HAVE_PERF_USER_STACK_DUMP
61 select HAVE_REGS_AND_STACK_ACCESS_API
62 select HAVE_SYSCALL_TRACEPOINTS
64 select HAVE_VIRT_CPU_ACCOUNTING_GEN
65 select IRQ_FORCED_THREADING
67 select MODULES_USE_ELF_REL
70 select OLD_SIGSUSPEND3
71 select PERF_USE_VMALLOC
73 select SYS_SUPPORTS_APM_EMULATION
74 # Above selects are sorted alphabetically; please add new ones
75 # according to that. Thanks.
77 The ARM series is a line of low-power-consumption RISC chip designs
78 licensed by ARM Ltd and targeted at embedded applications and
79 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
80 manufactured, but legacy ARM-based PC hardware remains popular in
81 Europe. There is an ARM Linux project with a web page at
82 <http://www.arm.linux.org.uk/>.
84 config ARM_HAS_SG_CHAIN
87 config NEED_SG_DMA_LENGTH
90 config ARM_DMA_USE_IOMMU
92 select ARM_HAS_SG_CHAIN
93 select NEED_SG_DMA_LENGTH
97 config ARM_DMA_IOMMU_ALIGNMENT
98 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
102 DMA mapping framework by default aligns all buffers to the smallest
103 PAGE_SIZE order which is greater than or equal to the requested buffer
104 size. This works well for buffers up to a few hundreds kilobytes, but
105 for larger buffers it just a waste of address space. Drivers which has
106 relatively small addressing window (like 64Mib) might run out of
107 virtual space with just a few allocations.
109 With this parameter you can specify the maximum PAGE_SIZE order for
110 DMA IOMMU buffers. Larger buffers will be aligned only to this
111 specified order. The order is expressed as a power of two multiplied
119 config MIGHT_HAVE_PCI
122 config SYS_SUPPORTS_APM_EMULATION
127 select GENERIC_ALLOCATOR
138 The Extended Industry Standard Architecture (EISA) bus was
139 developed as an open alternative to the IBM MicroChannel bus.
141 The EISA bus provided some of the features of the IBM MicroChannel
142 bus while maintaining backward compatibility with cards made for
143 the older ISA bus. The EISA bus saw limited use between 1988 and
144 1995 when it was made obsolete by the PCI bus.
146 Say Y here if you are building a kernel for an EISA-based machine.
153 config STACKTRACE_SUPPORT
157 config HAVE_LATENCYTOP_SUPPORT
162 config LOCKDEP_SUPPORT
166 config TRACE_IRQFLAGS_SUPPORT
170 config RWSEM_GENERIC_SPINLOCK
174 config RWSEM_XCHGADD_ALGORITHM
177 config ARCH_HAS_ILOG2_U32
180 config ARCH_HAS_ILOG2_U64
183 config ARCH_HAS_CPUFREQ
186 Internal node to signify that the ARCH has CPUFREQ support
187 and that the relevant menu configurations are displayed for
190 config ARCH_HAS_BANDGAP
193 config GENERIC_HWEIGHT
197 config GENERIC_CALIBRATE_DELAY
201 config ARCH_MAY_HAVE_PC_FDC
207 config NEED_DMA_MAP_STATE
210 config ARCH_HAS_DMA_SET_COHERENT_MASK
213 config GENERIC_ISA_DMA
219 config NEED_RET_TO_USER
227 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
228 default DRAM_BASE if REMAP_VECTORS_TO_RAM
231 The base address of exception vectors. This must be two pages
234 config ARM_PATCH_PHYS_VIRT
235 bool "Patch physical to virtual translations at runtime" if EMBEDDED
237 depends on !XIP_KERNEL && MMU
238 depends on !ARCH_REALVIEW || !SPARSEMEM
240 Patch phys-to-virt and virt-to-phys translation functions at
241 boot and module load time according to the position of the
242 kernel in system memory.
244 This can only be used with non-XIP MMU kernels where the base
245 of physical memory is at a 16MB boundary.
247 Only disable this option if you know that you do not require
248 this feature (eg, building a kernel for a single machine) and
249 you need to shrink the kernel to the minimal size.
251 config NEED_MACH_GPIO_H
254 Select this when mach/gpio.h is required to provide special
255 definitions for this platform. The need for mach/gpio.h should
256 be avoided when possible.
258 config NEED_MACH_IO_H
261 Select this when mach/io.h is required to provide special
262 definitions for this platform. The need for mach/io.h should
263 be avoided when possible.
265 config NEED_MACH_MEMORY_H
268 Select this when mach/memory.h is required to provide special
269 definitions for this platform. The need for mach/memory.h should
270 be avoided when possible.
273 hex "Physical address of main memory" if MMU
274 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
275 default DRAM_BASE if !MMU
277 Please provide the physical address corresponding to the
278 location of main memory in your system.
284 source "init/Kconfig"
286 source "kernel/Kconfig.freezer"
291 bool "MMU-based Paged Memory Management Support"
294 Select if you want MMU-based virtualised addressing space
295 support by paged memory management. If unsure, say 'Y'.
298 # The "ARM system type" choice list is ordered alphabetically by option
299 # text. Please add new entries in the option alphabetic order.
302 prompt "ARM system type"
303 default ARCH_VERSATILE if !MMU
304 default ARCH_MULTIPLATFORM if MMU
306 config ARCH_MULTIPLATFORM
307 bool "Allow multiple platforms to be selected"
309 select ARM_PATCH_PHYS_VIRT
312 select MULTI_IRQ_HANDLER
316 config ARCH_INTEGRATOR
317 bool "ARM Ltd. Integrator family"
318 select ARCH_HAS_CPUFREQ
321 select COMMON_CLK_VERSATILE
322 select GENERIC_CLOCKEVENTS
325 select MULTI_IRQ_HANDLER
326 select NEED_MACH_MEMORY_H
327 select PLAT_VERSATILE
330 select VERSATILE_FPGA_IRQ
332 Support for ARM's Integrator platform.
335 bool "ARM Ltd. RealView family"
336 select ARCH_WANT_OPTIONAL_GPIOLIB
338 select ARM_TIMER_SP804
340 select COMMON_CLK_VERSATILE
341 select GENERIC_CLOCKEVENTS
342 select GPIO_PL061 if GPIOLIB
344 select NEED_MACH_MEMORY_H
345 select PLAT_VERSATILE
346 select PLAT_VERSATILE_CLCD
348 This enables support for ARM Ltd RealView boards.
350 config ARCH_VERSATILE
351 bool "ARM Ltd. Versatile family"
352 select ARCH_WANT_OPTIONAL_GPIOLIB
354 select ARM_TIMER_SP804
357 select GENERIC_CLOCKEVENTS
358 select HAVE_MACH_CLKDEV
360 select PLAT_VERSATILE
361 select PLAT_VERSATILE_CLCD
362 select PLAT_VERSATILE_CLOCK
363 select VERSATILE_FPGA_IRQ
365 This enables support for ARM Ltd Versatile board.
369 select ARCH_REQUIRE_GPIOLIB
372 select NEED_MACH_GPIO_H
373 select NEED_MACH_IO_H if PCCARD
375 select PINCTRL_AT91 if USE_OF
377 This enables support for systems based on Atmel
378 AT91RM9200 and AT91SAM9* processors.
381 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
382 select ARCH_REQUIRE_GPIOLIB
387 select GENERIC_CLOCKEVENTS
389 select MULTI_IRQ_HANDLER
392 Support for Cirrus Logic 711x/721x/731x based boards.
395 bool "Cortina Systems Gemini"
396 select ARCH_REQUIRE_GPIOLIB
399 select GENERIC_CLOCKEVENTS
401 Support for the Cortina Systems Gemini family SoCs
405 select ARCH_USES_GETTIMEOFFSET
408 select NEED_MACH_IO_H
409 select NEED_MACH_MEMORY_H
412 This is an evaluation board for the StrongARM processor available
413 from Digital. It has limited hardware on-board, including an
414 Ethernet interface, two PCMCIA sockets, two serial ports and a
418 bool "Energy Micro efm32"
420 select ARCH_REQUIRE_GPIOLIB
422 # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged,
423 # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO
428 select GENERIC_CLOCKEVENTS
434 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
439 select ARCH_HAS_HOLES_MEMORYMODEL
440 select ARCH_REQUIRE_GPIOLIB
441 select ARCH_USES_GETTIMEOFFSET
446 select NEED_MACH_MEMORY_H
448 This enables support for the Cirrus EP93xx series of CPUs.
450 config ARCH_FOOTBRIDGE
454 select GENERIC_CLOCKEVENTS
456 select NEED_MACH_IO_H if !MMU
457 select NEED_MACH_MEMORY_H
459 Support for systems based on the DC21285 companion chip
460 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
463 bool "Hilscher NetX based"
467 select GENERIC_CLOCKEVENTS
469 This enables support for systems based on the Hilscher NetX Soc
475 select NEED_MACH_MEMORY_H
476 select NEED_RET_TO_USER
481 Support for Intel's IOP13XX (XScale) family of processors.
486 select ARCH_REQUIRE_GPIOLIB
489 select NEED_RET_TO_USER
493 Support for Intel's 80219 and IOP32X (XScale) family of
499 select ARCH_REQUIRE_GPIOLIB
502 select NEED_RET_TO_USER
506 Support for Intel's IOP33X (XScale) family of processors.
511 select ARCH_HAS_DMA_SET_COHERENT_MASK
512 select ARCH_SUPPORTS_BIG_ENDIAN
513 select ARCH_REQUIRE_GPIOLIB
516 select DMABOUNCE if PCI
517 select GENERIC_CLOCKEVENTS
518 select MIGHT_HAVE_PCI
519 select NEED_MACH_IO_H
520 select USB_EHCI_BIG_ENDIAN_DESC
521 select USB_EHCI_BIG_ENDIAN_MMIO
523 Support for Intel's IXP4XX (XScale) family of processors.
527 select ARCH_REQUIRE_GPIOLIB
529 select GENERIC_CLOCKEVENTS
530 select MIGHT_HAVE_PCI
534 select PLAT_ORION_LEGACY
535 select USB_ARCH_HAS_EHCI
537 Support for the Marvell Dove SoC 88AP510
540 bool "Marvell Kirkwood"
541 select ARCH_HAS_CPUFREQ
542 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
549 select PINCTRL_KIRKWOOD
550 select PLAT_ORION_LEGACY
552 Support for the following Marvell Kirkwood series SoCs:
553 88F6180, 88F6192 and 88F6281.
556 bool "Marvell MV78xx0"
557 select ARCH_REQUIRE_GPIOLIB
559 select GENERIC_CLOCKEVENTS
562 select PLAT_ORION_LEGACY
564 Support for the following Marvell MV78xx0 series SoCs:
570 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
575 select PLAT_ORION_LEGACY
577 Support for the following Marvell Orion 5x series SoCs:
578 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
579 Orion-2 (5281), Orion-1-90 (6183).
582 bool "Marvell PXA168/910/MMP2"
584 select ARCH_REQUIRE_GPIOLIB
586 select GENERIC_ALLOCATOR
587 select GENERIC_CLOCKEVENTS
590 select MULTI_IRQ_HANDLER
595 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
598 bool "Micrel/Kendin KS8695"
599 select ARCH_REQUIRE_GPIOLIB
602 select GENERIC_CLOCKEVENTS
603 select NEED_MACH_MEMORY_H
605 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
606 System-on-Chip devices.
609 bool "Nuvoton W90X900 CPU"
610 select ARCH_REQUIRE_GPIOLIB
614 select GENERIC_CLOCKEVENTS
616 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
617 At present, the w90x900 has been renamed nuc900, regarding
618 the ARM series product line, you can login the following
619 link address to know more.
621 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
622 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
626 select ARCH_REQUIRE_GPIOLIB
631 select GENERIC_CLOCKEVENTS
634 select USB_ARCH_HAS_OHCI
637 Support for the NXP LPC32XX family of processors
640 bool "PXA2xx/PXA3xx-based"
642 select ARCH_HAS_CPUFREQ
644 select ARCH_REQUIRE_GPIOLIB
645 select ARM_CPU_SUSPEND if PM
649 select GENERIC_CLOCKEVENTS
652 select MULTI_IRQ_HANDLER
656 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
661 select ARCH_REQUIRE_GPIOLIB
663 select GENERIC_CLOCKEVENTS
665 Support for Qualcomm MSM/QSD based systems. This runs on the
666 apps processor of the MSM/QSD and depends on a shared memory
667 interface to the modem processor which runs the baseband
668 stack and controls some vital subsystems
669 (clock and power control, etc).
671 config ARCH_SHMOBILE_LEGACY
672 bool "Renesas SH-Mobile / R-Mobile (non-multiplatform)"
674 select ARM_PATCH_PHYS_VIRT
676 select GENERIC_CLOCKEVENTS
677 select HAVE_ARM_SCU if SMP
678 select HAVE_ARM_TWD if SMP
679 select HAVE_MACH_CLKDEV
681 select MIGHT_HAVE_CACHE_L2X0
682 select MULTI_IRQ_HANDLER
685 select PM_GENERIC_DOMAINS if PM
688 Support for Renesas's SH-Mobile and R-Mobile ARM platforms using
689 a non-multiplatform kernel.
694 select ARCH_MAY_HAVE_PC_FDC
695 select ARCH_SPARSEMEM_ENABLE
696 select ARCH_USES_GETTIMEOFFSET
699 select HAVE_PATA_PLATFORM
701 select NEED_MACH_IO_H
702 select NEED_MACH_MEMORY_H
706 On the Acorn Risc-PC, Linux can support the internal IDE disk and
707 CD-ROM interface, serial and parallel port, and the floppy drive.
711 select ARCH_HAS_CPUFREQ
713 select ARCH_REQUIRE_GPIOLIB
714 select ARCH_SPARSEMEM_ENABLE
719 select GENERIC_CLOCKEVENTS
722 select NEED_MACH_MEMORY_H
725 Support for StrongARM 11x0 based boards.
728 bool "Samsung S3C24XX SoCs"
729 select ARCH_HAS_CPUFREQ
730 select ARCH_REQUIRE_GPIOLIB
732 select CLKSRC_SAMSUNG_PWM
733 select GENERIC_CLOCKEVENTS
735 select HAVE_S3C2410_I2C if I2C
736 select HAVE_S3C2410_WATCHDOG if WATCHDOG
737 select HAVE_S3C_RTC if RTC_CLASS
738 select MULTI_IRQ_HANDLER
739 select NEED_MACH_IO_H
742 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
743 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
744 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
745 Samsung SMDK2410 development board (and derivatives).
748 bool "Samsung S3C64XX"
749 select ARCH_HAS_CPUFREQ
750 select ARCH_REQUIRE_GPIOLIB
754 select CLKSRC_SAMSUNG_PWM
757 select GENERIC_CLOCKEVENTS
759 select HAVE_S3C2410_I2C if I2C
760 select HAVE_S3C2410_WATCHDOG if WATCHDOG
764 select PM_GENERIC_DOMAINS
766 select S3C_GPIO_TRACK
768 select SAMSUNG_WAKEMASK
769 select SAMSUNG_WDT_RESET
770 select USB_ARCH_HAS_OHCI
772 Samsung S3C64XX series based systems
775 bool "Samsung S5P6440 S5P6450"
777 select CLKSRC_SAMSUNG_PWM
779 select GENERIC_CLOCKEVENTS
781 select HAVE_S3C2410_I2C if I2C
782 select HAVE_S3C2410_WATCHDOG if WATCHDOG
783 select HAVE_S3C_RTC if RTC_CLASS
784 select NEED_MACH_GPIO_H
786 select SAMSUNG_WDT_RESET
788 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
792 bool "Samsung S5PC100"
793 select ARCH_REQUIRE_GPIOLIB
795 select CLKSRC_SAMSUNG_PWM
797 select GENERIC_CLOCKEVENTS
799 select HAVE_S3C2410_I2C if I2C
800 select HAVE_S3C2410_WATCHDOG if WATCHDOG
801 select HAVE_S3C_RTC if RTC_CLASS
802 select NEED_MACH_GPIO_H
804 select SAMSUNG_WDT_RESET
806 Samsung S5PC100 series based systems
809 bool "Samsung S5PV210/S5PC110"
810 select ARCH_HAS_CPUFREQ
811 select ARCH_HAS_HOLES_MEMORYMODEL
812 select ARCH_SPARSEMEM_ENABLE
814 select CLKSRC_SAMSUNG_PWM
816 select GENERIC_CLOCKEVENTS
818 select HAVE_S3C2410_I2C if I2C
819 select HAVE_S3C2410_WATCHDOG if WATCHDOG
820 select HAVE_S3C_RTC if RTC_CLASS
821 select NEED_MACH_GPIO_H
822 select NEED_MACH_MEMORY_H
825 Samsung S5PV210/S5PC110 series based systems
828 bool "Samsung EXYNOS"
829 select ARCH_HAS_CPUFREQ
830 select ARCH_HAS_HOLES_MEMORYMODEL
831 select ARCH_REQUIRE_GPIOLIB
832 select ARCH_SPARSEMEM_ENABLE
836 select GENERIC_CLOCKEVENTS
837 select HAVE_S3C2410_I2C if I2C
838 select HAVE_S3C2410_WATCHDOG if WATCHDOG
839 select HAVE_S3C_RTC if RTC_CLASS
840 select NEED_MACH_MEMORY_H
844 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
848 select ARCH_HAS_HOLES_MEMORYMODEL
849 select ARCH_REQUIRE_GPIOLIB
851 select GENERIC_ALLOCATOR
852 select GENERIC_CLOCKEVENTS
853 select GENERIC_IRQ_CHIP
859 Support for TI's DaVinci platform.
864 select ARCH_HAS_CPUFREQ
865 select ARCH_HAS_HOLES_MEMORYMODEL
867 select ARCH_REQUIRE_GPIOLIB
870 select GENERIC_CLOCKEVENTS
871 select GENERIC_IRQ_CHIP
874 select NEED_MACH_IO_H if PCCARD
875 select NEED_MACH_MEMORY_H
877 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
881 menu "Multiple platform selection"
882 depends on ARCH_MULTIPLATFORM
884 comment "CPU Core family selection"
886 config ARCH_MULTI_V4T
887 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
888 depends on !ARCH_MULTI_V6_V7
889 select ARCH_MULTI_V4_V5
890 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
891 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
892 CPU_ARM925T || CPU_ARM940T)
895 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
896 depends on !ARCH_MULTI_V6_V7
897 select ARCH_MULTI_V4_V5
898 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
899 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
900 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
902 config ARCH_MULTI_V4_V5
906 bool "ARMv6 based platforms (ARM11)"
907 select ARCH_MULTI_V6_V7
911 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
913 select ARCH_MULTI_V6_V7
916 config ARCH_MULTI_V6_V7
919 config ARCH_MULTI_CPU_AUTO
920 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
926 # This is sorted alphabetically by mach-* pathname. However, plat-*
927 # Kconfigs may be included either alphabetically (according to the
928 # plat- suffix) or along side the corresponding mach-* source.
930 source "arch/arm/mach-mvebu/Kconfig"
932 source "arch/arm/mach-at91/Kconfig"
934 source "arch/arm/mach-bcm/Kconfig"
936 source "arch/arm/mach-bcm2835/Kconfig"
938 source "arch/arm/mach-berlin/Kconfig"
940 source "arch/arm/mach-clps711x/Kconfig"
942 source "arch/arm/mach-cns3xxx/Kconfig"
944 source "arch/arm/mach-davinci/Kconfig"
946 source "arch/arm/mach-dove/Kconfig"
948 source "arch/arm/mach-ep93xx/Kconfig"
950 source "arch/arm/mach-footbridge/Kconfig"
952 source "arch/arm/mach-gemini/Kconfig"
954 source "arch/arm/mach-highbank/Kconfig"
956 source "arch/arm/mach-hisi/Kconfig"
958 source "arch/arm/mach-integrator/Kconfig"
960 source "arch/arm/mach-iop32x/Kconfig"
962 source "arch/arm/mach-iop33x/Kconfig"
964 source "arch/arm/mach-iop13xx/Kconfig"
966 source "arch/arm/mach-ixp4xx/Kconfig"
968 source "arch/arm/mach-keystone/Kconfig"
970 source "arch/arm/mach-kirkwood/Kconfig"
972 source "arch/arm/mach-ks8695/Kconfig"
974 source "arch/arm/mach-msm/Kconfig"
976 source "arch/arm/mach-moxart/Kconfig"
978 source "arch/arm/mach-mv78xx0/Kconfig"
980 source "arch/arm/mach-imx/Kconfig"
982 source "arch/arm/mach-mxs/Kconfig"
984 source "arch/arm/mach-netx/Kconfig"
986 source "arch/arm/mach-nomadik/Kconfig"
988 source "arch/arm/mach-nspire/Kconfig"
990 source "arch/arm/plat-omap/Kconfig"
992 source "arch/arm/mach-omap1/Kconfig"
994 source "arch/arm/mach-omap2/Kconfig"
996 source "arch/arm/mach-orion5x/Kconfig"
998 source "arch/arm/mach-picoxcell/Kconfig"
1000 source "arch/arm/mach-pxa/Kconfig"
1001 source "arch/arm/plat-pxa/Kconfig"
1003 source "arch/arm/mach-mmp/Kconfig"
1005 source "arch/arm/mach-realview/Kconfig"
1007 source "arch/arm/mach-rockchip/Kconfig"
1009 source "arch/arm/mach-sa1100/Kconfig"
1011 source "arch/arm/plat-samsung/Kconfig"
1013 source "arch/arm/mach-socfpga/Kconfig"
1015 source "arch/arm/mach-spear/Kconfig"
1017 source "arch/arm/mach-sti/Kconfig"
1019 source "arch/arm/mach-s3c24xx/Kconfig"
1021 source "arch/arm/mach-s3c64xx/Kconfig"
1023 source "arch/arm/mach-s5p64x0/Kconfig"
1025 source "arch/arm/mach-s5pc100/Kconfig"
1027 source "arch/arm/mach-s5pv210/Kconfig"
1029 source "arch/arm/mach-exynos/Kconfig"
1031 source "arch/arm/mach-shmobile/Kconfig"
1033 source "arch/arm/mach-sunxi/Kconfig"
1035 source "arch/arm/mach-prima2/Kconfig"
1037 source "arch/arm/mach-tegra/Kconfig"
1039 source "arch/arm/mach-u300/Kconfig"
1041 source "arch/arm/mach-ux500/Kconfig"
1043 source "arch/arm/mach-versatile/Kconfig"
1045 source "arch/arm/mach-vexpress/Kconfig"
1046 source "arch/arm/plat-versatile/Kconfig"
1048 source "arch/arm/mach-virt/Kconfig"
1050 source "arch/arm/mach-vt8500/Kconfig"
1052 source "arch/arm/mach-w90x900/Kconfig"
1054 source "arch/arm/mach-zynq/Kconfig"
1056 # Definitions to make life easier
1062 select GENERIC_CLOCKEVENTS
1068 select GENERIC_IRQ_CHIP
1071 config PLAT_ORION_LEGACY
1078 config PLAT_VERSATILE
1081 config ARM_TIMER_SP804
1084 select CLKSRC_OF if OF
1086 source arch/arm/mm/Kconfig
1090 default 16 if ARCH_EP93XX
1094 bool "Enable iWMMXt support" if !CPU_PJ4
1095 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1096 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1098 Enable support for iWMMXt context switching at run time if
1099 running on a CPU that supports it.
1101 config MULTI_IRQ_HANDLER
1104 Allow each machine to specify it's own IRQ handler at run time.
1107 source "arch/arm/Kconfig-nommu"
1110 config PJ4B_ERRATA_4742
1111 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1112 depends on CPU_PJ4B && MACH_ARMADA_370
1115 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1116 Event (WFE) IDLE states, a specific timing sensitivity exists between
1117 the retiring WFI/WFE instructions and the newly issued subsequent
1118 instructions. This sensitivity can result in a CPU hang scenario.
1120 The software must insert either a Data Synchronization Barrier (DSB)
1121 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1124 config ARM_ERRATA_326103
1125 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1128 Executing a SWP instruction to read-only memory does not set bit 11
1129 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1130 treat the access as a read, preventing a COW from occurring and
1131 causing the faulting task to livelock.
1133 config ARM_ERRATA_411920
1134 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1135 depends on CPU_V6 || CPU_V6K
1137 Invalidation of the Instruction Cache operation can
1138 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1139 It does not affect the MPCore. This option enables the ARM Ltd.
1140 recommended workaround.
1142 config ARM_ERRATA_430973
1143 bool "ARM errata: Stale prediction on replaced interworking branch"
1146 This option enables the workaround for the 430973 Cortex-A8
1147 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1148 interworking branch is replaced with another code sequence at the
1149 same virtual address, whether due to self-modifying code or virtual
1150 to physical address re-mapping, Cortex-A8 does not recover from the
1151 stale interworking branch prediction. This results in Cortex-A8
1152 executing the new code sequence in the incorrect ARM or Thumb state.
1153 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1154 and also flushes the branch target cache at every context switch.
1155 Note that setting specific bits in the ACTLR register may not be
1156 available in non-secure mode.
1158 config ARM_ERRATA_458693
1159 bool "ARM errata: Processor deadlock when a false hazard is created"
1161 depends on !ARCH_MULTIPLATFORM
1163 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1164 erratum. For very specific sequences of memory operations, it is
1165 possible for a hazard condition intended for a cache line to instead
1166 be incorrectly associated with a different cache line. This false
1167 hazard might then cause a processor deadlock. The workaround enables
1168 the L1 caching of the NEON accesses and disables the PLD instruction
1169 in the ACTLR register. Note that setting specific bits in the ACTLR
1170 register may not be available in non-secure mode.
1172 config ARM_ERRATA_460075
1173 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1175 depends on !ARCH_MULTIPLATFORM
1177 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1178 erratum. Any asynchronous access to the L2 cache may encounter a
1179 situation in which recent store transactions to the L2 cache are lost
1180 and overwritten with stale memory contents from external memory. The
1181 workaround disables the write-allocate mode for the L2 cache via the
1182 ACTLR register. Note that setting specific bits in the ACTLR register
1183 may not be available in non-secure mode.
1185 config ARM_ERRATA_742230
1186 bool "ARM errata: DMB operation may be faulty"
1187 depends on CPU_V7 && SMP
1188 depends on !ARCH_MULTIPLATFORM
1190 This option enables the workaround for the 742230 Cortex-A9
1191 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1192 between two write operations may not ensure the correct visibility
1193 ordering of the two writes. This workaround sets a specific bit in
1194 the diagnostic register of the Cortex-A9 which causes the DMB
1195 instruction to behave as a DSB, ensuring the correct behaviour of
1198 config ARM_ERRATA_742231
1199 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1200 depends on CPU_V7 && SMP
1201 depends on !ARCH_MULTIPLATFORM
1203 This option enables the workaround for the 742231 Cortex-A9
1204 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1205 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1206 accessing some data located in the same cache line, may get corrupted
1207 data due to bad handling of the address hazard when the line gets
1208 replaced from one of the CPUs at the same time as another CPU is
1209 accessing it. This workaround sets specific bits in the diagnostic
1210 register of the Cortex-A9 which reduces the linefill issuing
1211 capabilities of the processor.
1213 config PL310_ERRATA_588369
1214 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1215 depends on CACHE_L2X0
1217 The PL310 L2 cache controller implements three types of Clean &
1218 Invalidate maintenance operations: by Physical Address
1219 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1220 They are architecturally defined to behave as the execution of a
1221 clean operation followed immediately by an invalidate operation,
1222 both performing to the same memory location. This functionality
1223 is not correctly implemented in PL310 as clean lines are not
1224 invalidated as a result of these operations.
1226 config ARM_ERRATA_643719
1227 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1228 depends on CPU_V7 && SMP
1230 This option enables the workaround for the 643719 Cortex-A9 (prior to
1231 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1232 register returns zero when it should return one. The workaround
1233 corrects this value, ensuring cache maintenance operations which use
1234 it behave as intended and avoiding data corruption.
1236 config ARM_ERRATA_720789
1237 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1240 This option enables the workaround for the 720789 Cortex-A9 (prior to
1241 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1242 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1243 As a consequence of this erratum, some TLB entries which should be
1244 invalidated are not, resulting in an incoherency in the system page
1245 tables. The workaround changes the TLB flushing routines to invalidate
1246 entries regardless of the ASID.
1248 config PL310_ERRATA_727915
1249 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1250 depends on CACHE_L2X0
1252 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1253 operation (offset 0x7FC). This operation runs in background so that
1254 PL310 can handle normal accesses while it is in progress. Under very
1255 rare circumstances, due to this erratum, write data can be lost when
1256 PL310 treats a cacheable write transaction during a Clean &
1257 Invalidate by Way operation.
1259 config ARM_ERRATA_743622
1260 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1262 depends on !ARCH_MULTIPLATFORM
1264 This option enables the workaround for the 743622 Cortex-A9
1265 (r2p*) erratum. Under very rare conditions, a faulty
1266 optimisation in the Cortex-A9 Store Buffer may lead to data
1267 corruption. This workaround sets a specific bit in the diagnostic
1268 register of the Cortex-A9 which disables the Store Buffer
1269 optimisation, preventing the defect from occurring. This has no
1270 visible impact on the overall performance or power consumption of the
1273 config ARM_ERRATA_751472
1274 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1276 depends on !ARCH_MULTIPLATFORM
1278 This option enables the workaround for the 751472 Cortex-A9 (prior
1279 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1280 completion of a following broadcasted operation if the second
1281 operation is received by a CPU before the ICIALLUIS has completed,
1282 potentially leading to corrupted entries in the cache or TLB.
1284 config PL310_ERRATA_753970
1285 bool "PL310 errata: cache sync operation may be faulty"
1286 depends on CACHE_PL310
1288 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1290 Under some condition the effect of cache sync operation on
1291 the store buffer still remains when the operation completes.
1292 This means that the store buffer is always asked to drain and
1293 this prevents it from merging any further writes. The workaround
1294 is to replace the normal offset of cache sync operation (0x730)
1295 by another offset targeting an unmapped PL310 register 0x740.
1296 This has the same effect as the cache sync operation: store buffer
1297 drain and waiting for all buffers empty.
1299 config ARM_ERRATA_754322
1300 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1303 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1304 r3p*) erratum. A speculative memory access may cause a page table walk
1305 which starts prior to an ASID switch but completes afterwards. This
1306 can populate the micro-TLB with a stale entry which may be hit with
1307 the new ASID. This workaround places two dsb instructions in the mm
1308 switching code so that no page table walks can cross the ASID switch.
1310 config ARM_ERRATA_754327
1311 bool "ARM errata: no automatic Store Buffer drain"
1312 depends on CPU_V7 && SMP
1314 This option enables the workaround for the 754327 Cortex-A9 (prior to
1315 r2p0) erratum. The Store Buffer does not have any automatic draining
1316 mechanism and therefore a livelock may occur if an external agent
1317 continuously polls a memory location waiting to observe an update.
1318 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1319 written polling loops from denying visibility of updates to memory.
1321 config ARM_ERRATA_364296
1322 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1325 This options enables the workaround for the 364296 ARM1136
1326 r0p2 erratum (possible cache data corruption with
1327 hit-under-miss enabled). It sets the undocumented bit 31 in
1328 the auxiliary control register and the FI bit in the control
1329 register, thus disabling hit-under-miss without putting the
1330 processor into full low interrupt latency mode. ARM11MPCore
1333 config ARM_ERRATA_764369
1334 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1335 depends on CPU_V7 && SMP
1337 This option enables the workaround for erratum 764369
1338 affecting Cortex-A9 MPCore with two or more processors (all
1339 current revisions). Under certain timing circumstances, a data
1340 cache line maintenance operation by MVA targeting an Inner
1341 Shareable memory region may fail to proceed up to either the
1342 Point of Coherency or to the Point of Unification of the
1343 system. This workaround adds a DSB instruction before the
1344 relevant cache maintenance functions and sets a specific bit
1345 in the diagnostic control register of the SCU.
1347 config PL310_ERRATA_769419
1348 bool "PL310 errata: no automatic Store Buffer drain"
1349 depends on CACHE_L2X0
1351 On revisions of the PL310 prior to r3p2, the Store Buffer does
1352 not automatically drain. This can cause normal, non-cacheable
1353 writes to be retained when the memory system is idle, leading
1354 to suboptimal I/O performance for drivers using coherent DMA.
1355 This option adds a write barrier to the cpu_idle loop so that,
1356 on systems with an outer cache, the store buffer is drained
1359 config ARM_ERRATA_775420
1360 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1363 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1364 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1365 operation aborts with MMU exception, it might cause the processor
1366 to deadlock. This workaround puts DSB before executing ISB if
1367 an abort may occur on cache maintenance.
1369 config ARM_ERRATA_798181
1370 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1371 depends on CPU_V7 && SMP
1373 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1374 adequately shooting down all use of the old entries. This
1375 option enables the Linux kernel workaround for this erratum
1376 which sends an IPI to the CPUs that are running the same ASID
1377 as the one being invalidated.
1379 config ARM_ERRATA_773022
1380 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1383 This option enables the workaround for the 773022 Cortex-A15
1384 (up to r0p4) erratum. In certain rare sequences of code, the
1385 loop buffer may deliver incorrect instructions. This
1386 workaround disables the loop buffer to avoid the erratum.
1390 source "arch/arm/common/Kconfig"
1400 Find out whether you have ISA slots on your motherboard. ISA is the
1401 name of a bus system, i.e. the way the CPU talks to the other stuff
1402 inside your box. Other bus systems are PCI, EISA, MicroChannel
1403 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1404 newer boards don't support it. If you have ISA, say Y, otherwise N.
1406 # Select ISA DMA controller support
1411 # Select ISA DMA interface
1416 bool "PCI support" if MIGHT_HAVE_PCI
1418 Find out whether you have a PCI motherboard. PCI is the name of a
1419 bus system, i.e. the way the CPU talks to the other stuff inside
1420 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1421 VESA. If you have PCI, say Y, otherwise N.
1427 config PCI_NANOENGINE
1428 bool "BSE nanoEngine PCI support"
1429 depends on SA1100_NANOENGINE
1431 Enable PCI on the BSE nanoEngine board.
1436 config PCI_HOST_ITE8152
1438 depends on PCI && MACH_ARMCORE
1442 source "drivers/pci/Kconfig"
1443 source "drivers/pci/pcie/Kconfig"
1445 source "drivers/pcmcia/Kconfig"
1449 menu "Kernel Features"
1454 This option should be selected by machines which have an SMP-
1457 The only effect of this option is to make the SMP-related
1458 options available to the user for configuration.
1461 bool "Symmetric Multi-Processing"
1462 depends on CPU_V6K || CPU_V7
1463 depends on GENERIC_CLOCKEVENTS
1465 depends on MMU || ARM_MPU
1467 This enables support for systems with more than one CPU. If you have
1468 a system with only one CPU, like most personal computers, say N. If
1469 you have a system with more than one CPU, say Y.
1471 If you say N here, the kernel will run on single and multiprocessor
1472 machines, but will use only one CPU of a multiprocessor machine. If
1473 you say Y here, the kernel will run on many, but not all, single
1474 processor machines. On a single processor machine, the kernel will
1475 run faster if you say N here.
1477 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1478 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1479 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1481 If you don't know what to do here, say N.
1484 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1485 depends on SMP && !XIP_KERNEL && MMU
1488 SMP kernels contain instructions which fail on non-SMP processors.
1489 Enabling this option allows the kernel to modify itself to make
1490 these instructions safe. Disabling it allows about 1K of space
1493 If you don't know what to do here, say Y.
1495 config ARM_CPU_TOPOLOGY
1496 bool "Support cpu topology definition"
1497 depends on SMP && CPU_V7
1500 Support ARM cpu topology definition. The MPIDR register defines
1501 affinity between processors which is then used to describe the cpu
1502 topology of an ARM System.
1505 bool "Multi-core scheduler support"
1506 depends on ARM_CPU_TOPOLOGY
1508 Multi-core scheduler support improves the CPU scheduler's decision
1509 making when dealing with multi-core CPU chips at a cost of slightly
1510 increased overhead in some places. If unsure say N here.
1513 bool "SMT scheduler support"
1514 depends on ARM_CPU_TOPOLOGY
1516 Improves the CPU scheduler's decision making when dealing with
1517 MultiThreading at a cost of slightly increased overhead in some
1518 places. If unsure say N here.
1523 This option enables support for the ARM system coherency unit
1525 config HAVE_ARM_ARCH_TIMER
1526 bool "Architected timer support"
1528 select ARM_ARCH_TIMER
1529 select GENERIC_CLOCKEVENTS
1531 This option enables support for the ARM architected timer
1536 select CLKSRC_OF if OF
1538 This options enables support for the ARM timer and watchdog unit
1541 bool "Multi-Cluster Power Management"
1542 depends on CPU_V7 && SMP
1544 This option provides the common power management infrastructure
1545 for (multi-)cluster based systems, such as big.LITTLE based
1549 bool "big.LITTLE support (Experimental)"
1550 depends on CPU_V7 && SMP
1553 This option enables support selections for the big.LITTLE
1554 system architecture.
1557 bool "big.LITTLE switcher support"
1558 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1560 select ARM_CPU_SUSPEND
1562 The big.LITTLE "switcher" provides the core functionality to
1563 transparently handle transition between a cluster of A15's
1564 and a cluster of A7's in a big.LITTLE system.
1566 config BL_SWITCHER_DUMMY_IF
1567 tristate "Simple big.LITTLE switcher user interface"
1568 depends on BL_SWITCHER && DEBUG_KERNEL
1570 This is a simple and dummy char dev interface to control
1571 the big.LITTLE switcher core code. It is meant for
1572 debugging purposes only.
1575 prompt "Memory split"
1578 Select the desired split between kernel and user memory.
1580 If you are not absolutely sure what you are doing, leave this
1584 bool "3G/1G user/kernel split"
1586 bool "2G/2G user/kernel split"
1588 bool "1G/3G user/kernel split"
1593 default 0x40000000 if VMSPLIT_1G
1594 default 0x80000000 if VMSPLIT_2G
1598 int "Maximum number of CPUs (2-32)"
1604 bool "Support for hot-pluggable CPUs"
1607 Say Y here to experiment with turning CPUs off and on. CPUs
1608 can be controlled through /sys/devices/system/cpu.
1611 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1614 Say Y here if you want Linux to communicate with system firmware
1615 implementing the PSCI specification for CPU-centric power
1616 management operations described in ARM document number ARM DEN
1617 0022A ("Power State Coordination Interface System Software on
1620 # The GPIO number here must be sorted by descending number. In case of
1621 # a multiplatform kernel, we just want the highest value required by the
1622 # selected platforms.
1625 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1626 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1627 default 392 if ARCH_U8500
1628 default 352 if ARCH_VT8500
1629 default 288 if ARCH_SUNXI
1630 default 264 if MACH_H4700
1633 Maximum number of GPIOs in the system.
1635 If unsure, leave the default value.
1637 source kernel/Kconfig.preempt
1641 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1642 ARCH_S5PV210 || ARCH_EXYNOS4
1643 default AT91_TIMER_HZ if ARCH_AT91
1644 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1648 depends on HZ_FIXED = 0
1649 prompt "Timer frequency"
1673 default HZ_FIXED if HZ_FIXED != 0
1674 default 100 if HZ_100
1675 default 200 if HZ_200
1676 default 250 if HZ_250
1677 default 300 if HZ_300
1678 default 500 if HZ_500
1682 def_bool HIGH_RES_TIMERS
1684 config THUMB2_KERNEL
1685 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1686 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1687 default y if CPU_THUMBONLY
1689 select ARM_ASM_UNIFIED
1692 By enabling this option, the kernel will be compiled in
1693 Thumb-2 mode. A compiler/assembler that understand the unified
1694 ARM-Thumb syntax is needed.
1698 config THUMB2_AVOID_R_ARM_THM_JUMP11
1699 bool "Work around buggy Thumb-2 short branch relocations in gas"
1700 depends on THUMB2_KERNEL && MODULES
1703 Various binutils versions can resolve Thumb-2 branches to
1704 locally-defined, preemptible global symbols as short-range "b.n"
1705 branch instructions.
1707 This is a problem, because there's no guarantee the final
1708 destination of the symbol, or any candidate locations for a
1709 trampoline, are within range of the branch. For this reason, the
1710 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1711 relocation in modules at all, and it makes little sense to add
1714 The symptom is that the kernel fails with an "unsupported
1715 relocation" error when loading some modules.
1717 Until fixed tools are available, passing
1718 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1719 code which hits this problem, at the cost of a bit of extra runtime
1720 stack usage in some cases.
1722 The problem is described in more detail at:
1723 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1725 Only Thumb-2 kernels are affected.
1727 Unless you are sure your tools don't have this problem, say Y.
1729 config ARM_ASM_UNIFIED
1733 bool "Use the ARM EABI to compile the kernel"
1735 This option allows for the kernel to be compiled using the latest
1736 ARM ABI (aka EABI). This is only useful if you are using a user
1737 space environment that is also compiled with EABI.
1739 Since there are major incompatibilities between the legacy ABI and
1740 EABI, especially with regard to structure member alignment, this
1741 option also changes the kernel syscall calling convention to
1742 disambiguate both ABIs and allow for backward compatibility support
1743 (selected with CONFIG_OABI_COMPAT).
1745 To use this you need GCC version 4.0.0 or later.
1748 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1749 depends on AEABI && !THUMB2_KERNEL
1751 This option preserves the old syscall interface along with the
1752 new (ARM EABI) one. It also provides a compatibility layer to
1753 intercept syscalls that have structure arguments which layout
1754 in memory differs between the legacy ABI and the new ARM EABI
1755 (only for non "thumb" binaries). This option adds a tiny
1756 overhead to all syscalls and produces a slightly larger kernel.
1758 The seccomp filter system will not be available when this is
1759 selected, since there is no way yet to sensibly distinguish
1760 between calling conventions during filtering.
1762 If you know you'll be using only pure EABI user space then you
1763 can say N here. If this option is not selected and you attempt
1764 to execute a legacy ABI binary then the result will be
1765 UNPREDICTABLE (in fact it can be predicted that it won't work
1766 at all). If in doubt say N.
1768 config ARCH_HAS_HOLES_MEMORYMODEL
1771 config ARCH_SPARSEMEM_ENABLE
1774 config ARCH_SPARSEMEM_DEFAULT
1775 def_bool ARCH_SPARSEMEM_ENABLE
1777 config ARCH_SELECT_MEMORY_MODEL
1778 def_bool ARCH_SPARSEMEM_ENABLE
1780 config HAVE_ARCH_PFN_VALID
1781 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1784 bool "High Memory Support"
1787 The address space of ARM processors is only 4 Gigabytes large
1788 and it has to accommodate user address space, kernel address
1789 space as well as some memory mapped IO. That means that, if you
1790 have a large amount of physical memory and/or IO, not all of the
1791 memory can be "permanently mapped" by the kernel. The physical
1792 memory that is not permanently mapped is called "high memory".
1794 Depending on the selected kernel/user memory split, minimum
1795 vmalloc space and actual amount of RAM, you may not need this
1796 option which should result in a slightly faster kernel.
1801 bool "Allocate 2nd-level pagetables from highmem"
1804 config HW_PERF_EVENTS
1805 bool "Enable hardware performance counter support for perf events"
1806 depends on PERF_EVENTS
1809 Enable hardware performance counter support for perf events. If
1810 disabled, perf events will use software events only.
1812 config SYS_SUPPORTS_HUGETLBFS
1816 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1820 config ARCH_WANT_GENERAL_HUGETLB
1825 config FORCE_MAX_ZONEORDER
1826 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1827 range 11 64 if ARCH_SHMOBILE_LEGACY
1828 default "12" if SOC_AM33XX
1829 default "9" if SA1111 || ARCH_EFM32
1832 The kernel memory allocator divides physically contiguous memory
1833 blocks into "zones", where each zone is a power of two number of
1834 pages. This option selects the largest power of two that the kernel
1835 keeps in the memory allocator. If you need to allocate very large
1836 blocks of physically contiguous memory, then you may need to
1837 increase this value.
1839 This config option is actually maximum order plus one. For example,
1840 a value of 11 means that the largest free memory block is 2^10 pages.
1842 config ALIGNMENT_TRAP
1844 depends on CPU_CP15_MMU
1845 default y if !ARCH_EBSA110
1846 select HAVE_PROC_CPU if PROC_FS
1848 ARM processors cannot fetch/store information which is not
1849 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1850 address divisible by 4. On 32-bit ARM processors, these non-aligned
1851 fetch/store instructions will be emulated in software if you say
1852 here, which has a severe performance impact. This is necessary for
1853 correct operation of some network protocols. With an IP-only
1854 configuration it is safe to say N, otherwise say Y.
1856 config UACCESS_WITH_MEMCPY
1857 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1859 default y if CPU_FEROCEON
1861 Implement faster copy_to_user and clear_user methods for CPU
1862 cores where a 8-word STM instruction give significantly higher
1863 memory write throughput than a sequence of individual 32bit stores.
1865 A possible side effect is a slight increase in scheduling latency
1866 between threads sharing the same address space if they invoke
1867 such copy operations with large buffers.
1869 However, if the CPU data cache is using a write-allocate mode,
1870 this option is unlikely to provide any performance gain.
1874 prompt "Enable seccomp to safely compute untrusted bytecode"
1876 This kernel feature is useful for number crunching applications
1877 that may need to compute untrusted bytecode during their
1878 execution. By using pipes or other transports made available to
1879 the process as file descriptors supporting the read/write
1880 syscalls, it's possible to isolate those applications in
1881 their own address space using seccomp. Once seccomp is
1882 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1883 and the task is only allowed to execute a few safe syscalls
1884 defined by each seccomp mode.
1897 bool "Xen guest support on ARM (EXPERIMENTAL)"
1898 depends on ARM && AEABI && OF
1899 depends on CPU_V7 && !CPU_V6
1900 depends on !GENERIC_ATOMIC64
1904 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1911 bool "Flattened Device Tree support"
1914 select OF_EARLY_FLATTREE
1916 Include support for flattened device tree machine descriptions.
1919 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1922 This is the traditional way of passing data to the kernel at boot
1923 time. If you are solely relying on the flattened device tree (or
1924 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1925 to remove ATAGS support from your kernel binary. If unsure,
1928 config DEPRECATED_PARAM_STRUCT
1929 bool "Provide old way to pass kernel parameters"
1932 This was deprecated in 2001 and announced to live on for 5 years.
1933 Some old boot loaders still use this way.
1935 # Compressed boot loader in ROM. Yes, we really want to ask about
1936 # TEXT and BSS so we preserve their values in the config files.
1937 config ZBOOT_ROM_TEXT
1938 hex "Compressed ROM boot loader base address"
1941 The physical address at which the ROM-able zImage is to be
1942 placed in the target. Platforms which normally make use of
1943 ROM-able zImage formats normally set this to a suitable
1944 value in their defconfig file.
1946 If ZBOOT_ROM is not enabled, this has no effect.
1948 config ZBOOT_ROM_BSS
1949 hex "Compressed ROM boot loader BSS address"
1952 The base address of an area of read/write memory in the target
1953 for the ROM-able zImage which must be available while the
1954 decompressor is running. It must be large enough to hold the
1955 entire decompressed kernel plus an additional 128 KiB.
1956 Platforms which normally make use of ROM-able zImage formats
1957 normally set this to a suitable value in their defconfig file.
1959 If ZBOOT_ROM is not enabled, this has no effect.
1962 bool "Compressed boot loader in ROM/flash"
1963 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1964 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1966 Say Y here if you intend to execute your compressed kernel image
1967 (zImage) directly from ROM or flash. If unsure, say N.
1970 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1971 depends on ZBOOT_ROM && ARCH_SH7372
1972 default ZBOOT_ROM_NONE
1974 Include experimental SD/MMC loading code in the ROM-able zImage.
1975 With this enabled it is possible to write the ROM-able zImage
1976 kernel image to an MMC or SD card and boot the kernel straight
1977 from the reset vector. At reset the processor Mask ROM will load
1978 the first part of the ROM-able zImage which in turn loads the
1979 rest the kernel image to RAM.
1981 config ZBOOT_ROM_NONE
1982 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1984 Do not load image from SD or MMC
1986 config ZBOOT_ROM_MMCIF
1987 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1989 Load image from MMCIF hardware block.
1991 config ZBOOT_ROM_SH_MOBILE_SDHI
1992 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1994 Load image from SDHI hardware block
1998 config ARM_APPENDED_DTB
1999 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2002 With this option, the boot code will look for a device tree binary
2003 (DTB) appended to zImage
2004 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2006 This is meant as a backward compatibility convenience for those
2007 systems with a bootloader that can't be upgraded to accommodate
2008 the documented boot protocol using a device tree.
2010 Beware that there is very little in terms of protection against
2011 this option being confused by leftover garbage in memory that might
2012 look like a DTB header after a reboot if no actual DTB is appended
2013 to zImage. Do not leave this option active in a production kernel
2014 if you don't intend to always append a DTB. Proper passing of the
2015 location into r2 of a bootloader provided DTB is always preferable
2018 config ARM_ATAG_DTB_COMPAT
2019 bool "Supplement the appended DTB with traditional ATAG information"
2020 depends on ARM_APPENDED_DTB
2022 Some old bootloaders can't be updated to a DTB capable one, yet
2023 they provide ATAGs with memory configuration, the ramdisk address,
2024 the kernel cmdline string, etc. Such information is dynamically
2025 provided by the bootloader and can't always be stored in a static
2026 DTB. To allow a device tree enabled kernel to be used with such
2027 bootloaders, this option allows zImage to extract the information
2028 from the ATAG list and store it at run time into the appended DTB.
2031 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2032 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2034 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2035 bool "Use bootloader kernel arguments if available"
2037 Uses the command-line options passed by the boot loader instead of
2038 the device tree bootargs property. If the boot loader doesn't provide
2039 any, the device tree bootargs property will be used.
2041 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2042 bool "Extend with bootloader kernel arguments"
2044 The command-line arguments provided by the boot loader will be
2045 appended to the the device tree bootargs property.
2050 string "Default kernel command string"
2053 On some architectures (EBSA110 and CATS), there is currently no way
2054 for the boot loader to pass arguments to the kernel. For these
2055 architectures, you should supply some command-line options at build
2056 time by entering them here. As a minimum, you should specify the
2057 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2060 prompt "Kernel command line type" if CMDLINE != ""
2061 default CMDLINE_FROM_BOOTLOADER
2064 config CMDLINE_FROM_BOOTLOADER
2065 bool "Use bootloader kernel arguments if available"
2067 Uses the command-line options passed by the boot loader. If
2068 the boot loader doesn't provide any, the default kernel command
2069 string provided in CMDLINE will be used.
2071 config CMDLINE_EXTEND
2072 bool "Extend bootloader kernel arguments"
2074 The command-line arguments provided by the boot loader will be
2075 appended to the default kernel command string.
2077 config CMDLINE_FORCE
2078 bool "Always use the default kernel command string"
2080 Always use the default kernel command string, even if the boot
2081 loader passes other arguments to the kernel.
2082 This is useful if you cannot or don't want to change the
2083 command-line options your boot loader passes to the kernel.
2087 bool "Kernel Execute-In-Place from ROM"
2088 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2090 Execute-In-Place allows the kernel to run from non-volatile storage
2091 directly addressable by the CPU, such as NOR flash. This saves RAM
2092 space since the text section of the kernel is not loaded from flash
2093 to RAM. Read-write sections, such as the data section and stack,
2094 are still copied to RAM. The XIP kernel is not compressed since
2095 it has to run directly from flash, so it will take more space to
2096 store it. The flash address used to link the kernel object files,
2097 and for storing it, is configuration dependent. Therefore, if you
2098 say Y here, you must know the proper physical address where to
2099 store the kernel image depending on your own flash memory usage.
2101 Also note that the make target becomes "make xipImage" rather than
2102 "make zImage" or "make Image". The final kernel binary to put in
2103 ROM memory will be arch/arm/boot/xipImage.
2107 config XIP_PHYS_ADDR
2108 hex "XIP Kernel Physical Location"
2109 depends on XIP_KERNEL
2110 default "0x00080000"
2112 This is the physical address in your flash memory the kernel will
2113 be linked for and stored to. This address is dependent on your
2117 bool "Kexec system call (EXPERIMENTAL)"
2118 depends on (!SMP || PM_SLEEP_SMP)
2120 kexec is a system call that implements the ability to shutdown your
2121 current kernel, and to start another kernel. It is like a reboot
2122 but it is independent of the system firmware. And like a reboot
2123 you can start any kernel with it, not just Linux.
2125 It is an ongoing process to be certain the hardware in a machine
2126 is properly shutdown, so do not be surprised if this code does not
2127 initially work for you.
2130 bool "Export atags in procfs"
2131 depends on ATAGS && KEXEC
2134 Should the atags used to boot the kernel be exported in an "atags"
2135 file in procfs. Useful with kexec.
2138 bool "Build kdump crash kernel (EXPERIMENTAL)"
2140 Generate crash dump after being started by kexec. This should
2141 be normally only set in special crash dump kernels which are
2142 loaded in the main kernel with kexec-tools into a specially
2143 reserved region and then later executed after a crash by
2144 kdump/kexec. The crash dump kernel must be compiled to a
2145 memory address not used by the main kernel
2147 For more details see Documentation/kdump/kdump.txt
2149 config AUTO_ZRELADDR
2150 bool "Auto calculation of the decompressed kernel image address"
2152 ZRELADDR is the physical address where the decompressed kernel
2153 image will be placed. If AUTO_ZRELADDR is selected, the address
2154 will be determined at run-time by masking the current IP with
2155 0xf8000000. This assumes the zImage being placed in the first 128MB
2156 from start of memory.
2160 menu "CPU Power Management"
2163 source "drivers/cpufreq/Kconfig"
2166 source "drivers/cpuidle/Kconfig"
2170 menu "Floating point emulation"
2172 comment "At least one emulation must be selected"
2175 bool "NWFPE math emulation"
2176 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2178 Say Y to include the NWFPE floating point emulator in the kernel.
2179 This is necessary to run most binaries. Linux does not currently
2180 support floating point hardware so you need to say Y here even if
2181 your machine has an FPA or floating point co-processor podule.
2183 You may say N here if you are going to load the Acorn FPEmulator
2184 early in the bootup.
2187 bool "Support extended precision"
2188 depends on FPE_NWFPE
2190 Say Y to include 80-bit support in the kernel floating-point
2191 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2192 Note that gcc does not generate 80-bit operations by default,
2193 so in most cases this option only enlarges the size of the
2194 floating point emulator without any good reason.
2196 You almost surely want to say N here.
2199 bool "FastFPE math emulation (EXPERIMENTAL)"
2200 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2202 Say Y here to include the FAST floating point emulator in the kernel.
2203 This is an experimental much faster emulator which now also has full
2204 precision for the mantissa. It does not support any exceptions.
2205 It is very simple, and approximately 3-6 times faster than NWFPE.
2207 It should be sufficient for most programs. It may be not suitable
2208 for scientific calculations, but you have to check this for yourself.
2209 If you do not feel you need a faster FP emulation you should better
2213 bool "VFP-format floating point maths"
2214 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2216 Say Y to include VFP support code in the kernel. This is needed
2217 if your hardware includes a VFP unit.
2219 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2220 release notes and additional status information.
2222 Say N if your target does not have VFP hardware.
2230 bool "Advanced SIMD (NEON) Extension support"
2231 depends on VFPv3 && CPU_V7
2233 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2236 config KERNEL_MODE_NEON
2237 bool "Support for NEON in kernel mode"
2238 depends on NEON && AEABI
2240 Say Y to include support for NEON in kernel mode.
2244 menu "Userspace binary formats"
2246 source "fs/Kconfig.binfmt"
2249 tristate "RISC OS personality"
2252 Say Y here to include the kernel code necessary if you want to run
2253 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2254 experimental; if this sounds frightening, say N and sleep in peace.
2255 You can also say M here to compile this support as a module (which
2256 will be called arthur).
2260 menu "Power management options"
2262 source "kernel/power/Kconfig"
2264 config ARCH_SUSPEND_POSSIBLE
2265 depends on !ARCH_S5PC100
2266 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2267 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2270 config ARM_CPU_SUSPEND
2275 source "net/Kconfig"
2277 source "drivers/Kconfig"
2281 source "arch/arm/Kconfig.debug"
2283 source "security/Kconfig"
2285 source "crypto/Kconfig"
2287 source "lib/Kconfig"
2289 source "arch/arm/kvm/Kconfig"