1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_CLOCKSOURCE_DATA
6 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DEVMEM_IS_ALLOWED
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_FORTIFY_SOURCE
11 select ARCH_HAS_SET_MEMORY
12 select ARCH_HAS_PHYS_TO_DMA
13 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
14 select ARCH_HAS_STRICT_MODULE_RWX if MMU
15 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
16 select ARCH_HAVE_CUSTOM_GPIO_H
17 select ARCH_HAS_GCOV_PROFILE_ALL
18 select ARCH_MIGHT_HAVE_PC_PARPORT
19 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
20 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
21 select ARCH_SUPPORTS_ATOMIC_RMW
22 select ARCH_USE_BUILTIN_BSWAP
23 select ARCH_USE_CMPXCHG_LOCKREF
24 select ARCH_WANT_IPC_PARSE_VERSION
25 select BUILDTIME_EXTABLE_SORT if MMU
26 select CLONE_BACKWARDS
27 select CPU_PM if (SUSPEND || CPU_IDLE)
28 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
29 select DMA_DIRECT_OPS if !MMU
31 select EDAC_ATOMIC_SCRUB
32 select GENERIC_ALLOCATOR
33 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
34 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
35 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
36 select GENERIC_CPU_AUTOPROBE
37 select GENERIC_EARLY_IOREMAP
38 select GENERIC_IDLE_POLL_SETUP
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select GENERIC_IRQ_SHOW_LEVEL
42 select GENERIC_PCI_IOMAP
43 select GENERIC_SCHED_CLOCK
44 select GENERIC_SMP_IDLE_THREAD
45 select GENERIC_STRNCPY_FROM_USER
46 select GENERIC_STRNLEN_USER
47 select HANDLE_DOMAIN_IRQ
48 select HARDIRQS_SW_RESEND
49 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
50 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
51 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
52 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
53 select HAVE_ARCH_MMAP_RND_BITS if MMU
54 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
55 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
56 select HAVE_ARCH_TRACEHOOK
57 select HAVE_ARM_SMCCC if CPU_V7
58 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
59 select HAVE_CC_STACKPROTECTOR
60 select HAVE_CONTEXT_TRACKING
61 select HAVE_C_RECORDMCOUNT
62 select HAVE_DEBUG_KMEMLEAK
63 select HAVE_DMA_API_DEBUG
64 select HAVE_DMA_CONTIGUOUS if MMU
65 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
66 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
67 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
68 select HAVE_EXIT_THREAD
69 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
70 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
71 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
72 select HAVE_GCC_PLUGINS
73 select HAVE_GENERIC_DMA_COHERENT
74 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
75 select HAVE_IDE if PCI || ISA || PCMCIA
76 select HAVE_IRQ_TIME_ACCOUNTING
77 select HAVE_KERNEL_GZIP
78 select HAVE_KERNEL_LZ4
79 select HAVE_KERNEL_LZMA
80 select HAVE_KERNEL_LZO
82 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
83 select HAVE_KRETPROBES if (HAVE_KPROBES)
85 select HAVE_MOD_ARCH_SPECIFIC
87 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
88 select HAVE_OPTPROBES if !THUMB2_KERNEL
89 select HAVE_PERF_EVENTS
91 select HAVE_PERF_USER_STACK_DUMP
92 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
93 select HAVE_REGS_AND_STACK_ACCESS_API
94 select HAVE_SYSCALL_TRACEPOINTS
96 select HAVE_VIRT_CPU_ACCOUNTING_GEN
97 select IRQ_FORCED_THREADING
98 select MODULES_USE_ELF_REL
100 select OF_EARLY_FLATTREE if OF
101 select OF_RESERVED_MEM if OF
103 select OLD_SIGSUSPEND3
104 select PERF_USE_VMALLOC
107 select SYS_SUPPORTS_APM_EMULATION
108 # Above selects are sorted alphabetically; please add new ones
109 # according to that. Thanks.
111 The ARM series is a line of low-power-consumption RISC chip designs
112 licensed by ARM Ltd and targeted at embedded applications and
113 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
114 manufactured, but legacy ARM-based PC hardware remains popular in
115 Europe. There is an ARM Linux project with a web page at
116 <http://www.arm.linux.org.uk/>.
118 config ARM_HAS_SG_CHAIN
119 select ARCH_HAS_SG_CHAIN
122 config NEED_SG_DMA_LENGTH
125 config ARM_DMA_USE_IOMMU
127 select ARM_HAS_SG_CHAIN
128 select NEED_SG_DMA_LENGTH
132 config ARM_DMA_IOMMU_ALIGNMENT
133 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
137 DMA mapping framework by default aligns all buffers to the smallest
138 PAGE_SIZE order which is greater than or equal to the requested buffer
139 size. This works well for buffers up to a few hundreds kilobytes, but
140 for larger buffers it just a waste of address space. Drivers which has
141 relatively small addressing window (like 64Mib) might run out of
142 virtual space with just a few allocations.
144 With this parameter you can specify the maximum PAGE_SIZE order for
145 DMA IOMMU buffers. Larger buffers will be aligned only to this
146 specified order. The order is expressed as a power of two multiplied
151 config MIGHT_HAVE_PCI
154 config SYS_SUPPORTS_APM_EMULATION
159 select GENERIC_ALLOCATOR
170 The Extended Industry Standard Architecture (EISA) bus was
171 developed as an open alternative to the IBM MicroChannel bus.
173 The EISA bus provided some of the features of the IBM MicroChannel
174 bus while maintaining backward compatibility with cards made for
175 the older ISA bus. The EISA bus saw limited use between 1988 and
176 1995 when it was made obsolete by the PCI bus.
178 Say Y here if you are building a kernel for an EISA-based machine.
185 config STACKTRACE_SUPPORT
189 config LOCKDEP_SUPPORT
193 config TRACE_IRQFLAGS_SUPPORT
197 config RWSEM_XCHGADD_ALGORITHM
201 config ARCH_HAS_ILOG2_U32
204 config ARCH_HAS_ILOG2_U64
207 config ARCH_HAS_BANDGAP
210 config FIX_EARLYCON_MEM
213 config GENERIC_HWEIGHT
217 config GENERIC_CALIBRATE_DELAY
221 config ARCH_MAY_HAVE_PC_FDC
227 config NEED_DMA_MAP_STATE
230 config ARCH_SUPPORTS_UPROBES
233 config ARCH_HAS_DMA_SET_COHERENT_MASK
236 config GENERIC_ISA_DMA
242 config NEED_RET_TO_USER
248 config ARM_PATCH_PHYS_VIRT
249 bool "Patch physical to virtual translations at runtime" if EMBEDDED
251 depends on !XIP_KERNEL && MMU
253 Patch phys-to-virt and virt-to-phys translation functions at
254 boot and module load time according to the position of the
255 kernel in system memory.
257 This can only be used with non-XIP MMU kernels where the base
258 of physical memory is at a 16MB boundary.
260 Only disable this option if you know that you do not require
261 this feature (eg, building a kernel for a single machine) and
262 you need to shrink the kernel to the minimal size.
264 config NEED_MACH_IO_H
267 Select this when mach/io.h is required to provide special
268 definitions for this platform. The need for mach/io.h should
269 be avoided when possible.
271 config NEED_MACH_MEMORY_H
274 Select this when mach/memory.h is required to provide special
275 definitions for this platform. The need for mach/memory.h should
276 be avoided when possible.
279 hex "Physical address of main memory" if MMU
280 depends on !ARM_PATCH_PHYS_VIRT
281 default DRAM_BASE if !MMU
282 default 0x00000000 if ARCH_EBSA110 || \
288 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
289 default 0x20000000 if ARCH_S5PV210
290 default 0xc0000000 if ARCH_SA1100
292 Please provide the physical address corresponding to the
293 location of main memory in your system.
299 config PGTABLE_LEVELS
301 default 3 if ARM_LPAE
304 source "init/Kconfig"
306 source "kernel/Kconfig.freezer"
311 bool "MMU-based Paged Memory Management Support"
314 Select if you want MMU-based virtualised addressing space
315 support by paged memory management. If unsure, say 'Y'.
317 config ARCH_MMAP_RND_BITS_MIN
320 config ARCH_MMAP_RND_BITS_MAX
321 default 14 if PAGE_OFFSET=0x40000000
322 default 15 if PAGE_OFFSET=0x80000000
326 # The "ARM system type" choice list is ordered alphabetically by option
327 # text. Please add new entries in the option alphabetic order.
330 prompt "ARM system type"
331 default ARM_SINGLE_ARMV7M if !MMU
332 default ARCH_MULTIPLATFORM if MMU
334 config ARCH_MULTIPLATFORM
335 bool "Allow multiple platforms to be selected"
337 select ARM_HAS_SG_CHAIN
338 select ARM_PATCH_PHYS_VIRT
342 select GENERIC_CLOCKEVENTS
343 select MIGHT_HAVE_PCI
344 select MULTI_IRQ_HANDLER
345 select PCI_DOMAINS if PCI
349 config ARM_SINGLE_ARMV7M
350 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
357 select GENERIC_CLOCKEVENTS
364 select ARCH_USES_GETTIMEOFFSET
367 select NEED_MACH_IO_H
368 select NEED_MACH_MEMORY_H
371 This is an evaluation board for the StrongARM processor available
372 from Digital. It has limited hardware on-board, including an
373 Ethernet interface, two PCMCIA sockets, two serial ports and a
378 select ARCH_SPARSEMEM_ENABLE
380 imply ARM_PATCH_PHYS_VIRT
386 select GENERIC_CLOCKEVENTS
389 This enables support for the Cirrus EP93xx series of CPUs.
391 config ARCH_FOOTBRIDGE
395 select GENERIC_CLOCKEVENTS
397 select NEED_MACH_IO_H if !MMU
398 select NEED_MACH_MEMORY_H
400 Support for systems based on the DC21285 companion chip
401 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
404 bool "Hilscher NetX based"
408 select GENERIC_CLOCKEVENTS
410 This enables support for systems based on the Hilscher NetX Soc
416 select NEED_MACH_MEMORY_H
417 select NEED_RET_TO_USER
423 Support for Intel's IOP13XX (XScale) family of processors.
431 select NEED_RET_TO_USER
435 Support for Intel's 80219 and IOP32X (XScale) family of
444 select NEED_RET_TO_USER
448 Support for Intel's IOP33X (XScale) family of processors.
453 select ARCH_HAS_DMA_SET_COHERENT_MASK
454 select ARCH_SUPPORTS_BIG_ENDIAN
457 select DMABOUNCE if PCI
458 select GENERIC_CLOCKEVENTS
460 select MIGHT_HAVE_PCI
461 select NEED_MACH_IO_H
462 select USB_EHCI_BIG_ENDIAN_DESC
463 select USB_EHCI_BIG_ENDIAN_MMIO
465 Support for Intel's IXP4XX (XScale) family of processors.
470 select GENERIC_CLOCKEVENTS
472 select MIGHT_HAVE_PCI
473 select MULTI_IRQ_HANDLER
477 select PLAT_ORION_LEGACY
479 select PM_GENERIC_DOMAINS if PM
481 Support for the Marvell Dove SoC 88AP510
484 bool "Micrel/Kendin KS8695"
487 select GENERIC_CLOCKEVENTS
489 select NEED_MACH_MEMORY_H
491 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
492 System-on-Chip devices.
495 bool "Nuvoton W90X900 CPU"
499 select GENERIC_CLOCKEVENTS
502 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
503 At present, the w90x900 has been renamed nuc900, regarding
504 the ARM series product line, you can login the following
505 link address to know more.
507 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
508 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
514 select CLKSRC_LPC32XX
517 select GENERIC_CLOCKEVENTS
519 select MULTI_IRQ_HANDLER
523 Support for the NXP LPC32XX family of processors
526 bool "PXA2xx/PXA3xx-based"
529 select ARM_CPU_SUSPEND if PM
536 select CPU_XSCALE if !CPU_XSC3
537 select GENERIC_CLOCKEVENTS
542 select MULTI_IRQ_HANDLER
546 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
552 select ARCH_MAY_HAVE_PC_FDC
553 select ARCH_SPARSEMEM_ENABLE
554 select ARCH_USES_GETTIMEOFFSET
558 select HAVE_PATA_PLATFORM
560 select NEED_MACH_IO_H
561 select NEED_MACH_MEMORY_H
564 On the Acorn Risc-PC, Linux can support the internal IDE disk and
565 CD-ROM interface, serial and parallel port, and the floppy drive.
570 select ARCH_SPARSEMEM_ENABLE
574 select TIMER_OF if OF
577 select GENERIC_CLOCKEVENTS
582 select MULTI_IRQ_HANDLER
583 select NEED_MACH_MEMORY_H
586 Support for StrongARM 11x0 based boards.
589 bool "Samsung S3C24XX SoCs"
592 select CLKSRC_SAMSUNG_PWM
593 select GENERIC_CLOCKEVENTS
596 select HAVE_S3C2410_I2C if I2C
597 select HAVE_S3C2410_WATCHDOG if WATCHDOG
598 select HAVE_S3C_RTC if RTC_CLASS
599 select MULTI_IRQ_HANDLER
600 select NEED_MACH_IO_H
604 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
605 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
606 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
607 Samsung SMDK2410 development board (and derivatives).
611 select ARCH_HAS_HOLES_MEMORYMODEL
614 select GENERIC_ALLOCATOR
615 select GENERIC_CLOCKEVENTS
616 select GENERIC_IRQ_CHIP
622 Support for TI's DaVinci platform.
627 select ARCH_HAS_HOLES_MEMORYMODEL
631 select GENERIC_CLOCKEVENTS
632 select GENERIC_IRQ_CHIP
636 select MULTI_IRQ_HANDLER
637 select NEED_MACH_IO_H if PCCARD
638 select NEED_MACH_MEMORY_H
641 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
645 menu "Multiple platform selection"
646 depends on ARCH_MULTIPLATFORM
648 comment "CPU Core family selection"
651 bool "ARMv4 based platforms (FA526)"
652 depends on !ARCH_MULTI_V6_V7
653 select ARCH_MULTI_V4_V5
656 config ARCH_MULTI_V4T
657 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
658 depends on !ARCH_MULTI_V6_V7
659 select ARCH_MULTI_V4_V5
660 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
661 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
662 CPU_ARM925T || CPU_ARM940T)
665 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
666 depends on !ARCH_MULTI_V6_V7
667 select ARCH_MULTI_V4_V5
668 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
669 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
670 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
672 config ARCH_MULTI_V4_V5
676 bool "ARMv6 based platforms (ARM11)"
677 select ARCH_MULTI_V6_V7
681 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
683 select ARCH_MULTI_V6_V7
687 config ARCH_MULTI_V6_V7
689 select MIGHT_HAVE_CACHE_L2X0
691 config ARCH_MULTI_CPU_AUTO
692 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
698 bool "Dummy Virtual Machine"
699 depends on ARCH_MULTI_V7
702 select ARM_GIC_V2M if PCI
704 select ARM_GIC_V3_ITS if PCI
706 select HAVE_ARM_ARCH_TIMER
709 # This is sorted alphabetically by mach-* pathname. However, plat-*
710 # Kconfigs may be included either alphabetically (according to the
711 # plat- suffix) or along side the corresponding mach-* source.
713 source "arch/arm/mach-actions/Kconfig"
715 source "arch/arm/mach-alpine/Kconfig"
717 source "arch/arm/mach-artpec/Kconfig"
719 source "arch/arm/mach-asm9260/Kconfig"
721 source "arch/arm/mach-aspeed/Kconfig"
723 source "arch/arm/mach-at91/Kconfig"
725 source "arch/arm/mach-axxia/Kconfig"
727 source "arch/arm/mach-bcm/Kconfig"
729 source "arch/arm/mach-berlin/Kconfig"
731 source "arch/arm/mach-clps711x/Kconfig"
733 source "arch/arm/mach-cns3xxx/Kconfig"
735 source "arch/arm/mach-davinci/Kconfig"
737 source "arch/arm/mach-digicolor/Kconfig"
739 source "arch/arm/mach-dove/Kconfig"
741 source "arch/arm/mach-ep93xx/Kconfig"
743 source "arch/arm/mach-exynos/Kconfig"
744 source "arch/arm/plat-samsung/Kconfig"
746 source "arch/arm/mach-footbridge/Kconfig"
748 source "arch/arm/mach-gemini/Kconfig"
750 source "arch/arm/mach-highbank/Kconfig"
752 source "arch/arm/mach-hisi/Kconfig"
754 source "arch/arm/mach-imx/Kconfig"
756 source "arch/arm/mach-integrator/Kconfig"
758 source "arch/arm/mach-iop13xx/Kconfig"
760 source "arch/arm/mach-iop32x/Kconfig"
762 source "arch/arm/mach-iop33x/Kconfig"
764 source "arch/arm/mach-ixp4xx/Kconfig"
766 source "arch/arm/mach-keystone/Kconfig"
768 source "arch/arm/mach-ks8695/Kconfig"
770 source "arch/arm/mach-mediatek/Kconfig"
772 source "arch/arm/mach-meson/Kconfig"
774 source "arch/arm/mach-mmp/Kconfig"
776 source "arch/arm/mach-moxart/Kconfig"
778 source "arch/arm/mach-mv78xx0/Kconfig"
780 source "arch/arm/mach-mvebu/Kconfig"
782 source "arch/arm/mach-mxs/Kconfig"
784 source "arch/arm/mach-netx/Kconfig"
786 source "arch/arm/mach-nomadik/Kconfig"
788 source "arch/arm/mach-npcm/Kconfig"
790 source "arch/arm/mach-nspire/Kconfig"
792 source "arch/arm/plat-omap/Kconfig"
794 source "arch/arm/mach-omap1/Kconfig"
796 source "arch/arm/mach-omap2/Kconfig"
798 source "arch/arm/mach-orion5x/Kconfig"
800 source "arch/arm/mach-oxnas/Kconfig"
802 source "arch/arm/mach-picoxcell/Kconfig"
804 source "arch/arm/mach-prima2/Kconfig"
806 source "arch/arm/mach-pxa/Kconfig"
807 source "arch/arm/plat-pxa/Kconfig"
809 source "arch/arm/mach-qcom/Kconfig"
811 source "arch/arm/mach-realview/Kconfig"
813 source "arch/arm/mach-rockchip/Kconfig"
815 source "arch/arm/mach-s3c24xx/Kconfig"
817 source "arch/arm/mach-s3c64xx/Kconfig"
819 source "arch/arm/mach-s5pv210/Kconfig"
821 source "arch/arm/mach-sa1100/Kconfig"
823 source "arch/arm/mach-shmobile/Kconfig"
825 source "arch/arm/mach-socfpga/Kconfig"
827 source "arch/arm/mach-spear/Kconfig"
829 source "arch/arm/mach-sti/Kconfig"
831 source "arch/arm/mach-stm32/Kconfig"
833 source "arch/arm/mach-sunxi/Kconfig"
835 source "arch/arm/mach-tango/Kconfig"
837 source "arch/arm/mach-tegra/Kconfig"
839 source "arch/arm/mach-u300/Kconfig"
841 source "arch/arm/mach-uniphier/Kconfig"
843 source "arch/arm/mach-ux500/Kconfig"
845 source "arch/arm/mach-versatile/Kconfig"
847 source "arch/arm/mach-vexpress/Kconfig"
848 source "arch/arm/plat-versatile/Kconfig"
850 source "arch/arm/mach-vt8500/Kconfig"
852 source "arch/arm/mach-w90x900/Kconfig"
854 source "arch/arm/mach-zx/Kconfig"
856 source "arch/arm/mach-zynq/Kconfig"
858 # ARMv7-M architecture
860 bool "Energy Micro efm32"
861 depends on ARM_SINGLE_ARMV7M
864 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
868 bool "NXP LPC18xx/LPC43xx"
869 depends on ARM_SINGLE_ARMV7M
870 select ARCH_HAS_RESET_CONTROLLER
872 select CLKSRC_LPC32XX
875 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
876 high performance microcontrollers.
879 bool "ARM MPS2 platform"
880 depends on ARM_SINGLE_ARMV7M
884 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
885 with a range of available cores like Cortex-M3/M4/M7.
887 Please, note that depends which Application Note is used memory map
888 for the platform may vary, so adjustment of RAM base might be needed.
890 # Definitions to make life easier
896 select GENERIC_CLOCKEVENTS
902 select GENERIC_IRQ_CHIP
905 config PLAT_ORION_LEGACY
912 config PLAT_VERSATILE
915 source "arch/arm/firmware/Kconfig"
917 source arch/arm/mm/Kconfig
920 bool "Enable iWMMXt support"
921 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
922 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
924 Enable support for iWMMXt context switching at run time if
925 running on a CPU that supports it.
927 config MULTI_IRQ_HANDLER
930 Allow each machine to specify it's own IRQ handler at run time.
933 source "arch/arm/Kconfig-nommu"
936 config PJ4B_ERRATA_4742
937 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
938 depends on CPU_PJ4B && MACH_ARMADA_370
941 When coming out of either a Wait for Interrupt (WFI) or a Wait for
942 Event (WFE) IDLE states, a specific timing sensitivity exists between
943 the retiring WFI/WFE instructions and the newly issued subsequent
944 instructions. This sensitivity can result in a CPU hang scenario.
946 The software must insert either a Data Synchronization Barrier (DSB)
947 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
950 config ARM_ERRATA_326103
951 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
954 Executing a SWP instruction to read-only memory does not set bit 11
955 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
956 treat the access as a read, preventing a COW from occurring and
957 causing the faulting task to livelock.
959 config ARM_ERRATA_411920
960 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
961 depends on CPU_V6 || CPU_V6K
963 Invalidation of the Instruction Cache operation can
964 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
965 It does not affect the MPCore. This option enables the ARM Ltd.
966 recommended workaround.
968 config ARM_ERRATA_430973
969 bool "ARM errata: Stale prediction on replaced interworking branch"
972 This option enables the workaround for the 430973 Cortex-A8
973 r1p* erratum. If a code sequence containing an ARM/Thumb
974 interworking branch is replaced with another code sequence at the
975 same virtual address, whether due to self-modifying code or virtual
976 to physical address re-mapping, Cortex-A8 does not recover from the
977 stale interworking branch prediction. This results in Cortex-A8
978 executing the new code sequence in the incorrect ARM or Thumb state.
979 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
980 and also flushes the branch target cache at every context switch.
981 Note that setting specific bits in the ACTLR register may not be
982 available in non-secure mode.
984 config ARM_ERRATA_458693
985 bool "ARM errata: Processor deadlock when a false hazard is created"
987 depends on !ARCH_MULTIPLATFORM
989 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
990 erratum. For very specific sequences of memory operations, it is
991 possible for a hazard condition intended for a cache line to instead
992 be incorrectly associated with a different cache line. This false
993 hazard might then cause a processor deadlock. The workaround enables
994 the L1 caching of the NEON accesses and disables the PLD instruction
995 in the ACTLR register. Note that setting specific bits in the ACTLR
996 register may not be available in non-secure mode.
998 config ARM_ERRATA_460075
999 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1001 depends on !ARCH_MULTIPLATFORM
1003 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1004 erratum. Any asynchronous access to the L2 cache may encounter a
1005 situation in which recent store transactions to the L2 cache are lost
1006 and overwritten with stale memory contents from external memory. The
1007 workaround disables the write-allocate mode for the L2 cache via the
1008 ACTLR register. Note that setting specific bits in the ACTLR register
1009 may not be available in non-secure mode.
1011 config ARM_ERRATA_742230
1012 bool "ARM errata: DMB operation may be faulty"
1013 depends on CPU_V7 && SMP
1014 depends on !ARCH_MULTIPLATFORM
1016 This option enables the workaround for the 742230 Cortex-A9
1017 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1018 between two write operations may not ensure the correct visibility
1019 ordering of the two writes. This workaround sets a specific bit in
1020 the diagnostic register of the Cortex-A9 which causes the DMB
1021 instruction to behave as a DSB, ensuring the correct behaviour of
1024 config ARM_ERRATA_742231
1025 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1026 depends on CPU_V7 && SMP
1027 depends on !ARCH_MULTIPLATFORM
1029 This option enables the workaround for the 742231 Cortex-A9
1030 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1031 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1032 accessing some data located in the same cache line, may get corrupted
1033 data due to bad handling of the address hazard when the line gets
1034 replaced from one of the CPUs at the same time as another CPU is
1035 accessing it. This workaround sets specific bits in the diagnostic
1036 register of the Cortex-A9 which reduces the linefill issuing
1037 capabilities of the processor.
1039 config ARM_ERRATA_643719
1040 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1041 depends on CPU_V7 && SMP
1044 This option enables the workaround for the 643719 Cortex-A9 (prior to
1045 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1046 register returns zero when it should return one. The workaround
1047 corrects this value, ensuring cache maintenance operations which use
1048 it behave as intended and avoiding data corruption.
1050 config ARM_ERRATA_720789
1051 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1054 This option enables the workaround for the 720789 Cortex-A9 (prior to
1055 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1056 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1057 As a consequence of this erratum, some TLB entries which should be
1058 invalidated are not, resulting in an incoherency in the system page
1059 tables. The workaround changes the TLB flushing routines to invalidate
1060 entries regardless of the ASID.
1062 config ARM_ERRATA_743622
1063 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1065 depends on !ARCH_MULTIPLATFORM
1067 This option enables the workaround for the 743622 Cortex-A9
1068 (r2p*) erratum. Under very rare conditions, a faulty
1069 optimisation in the Cortex-A9 Store Buffer may lead to data
1070 corruption. This workaround sets a specific bit in the diagnostic
1071 register of the Cortex-A9 which disables the Store Buffer
1072 optimisation, preventing the defect from occurring. This has no
1073 visible impact on the overall performance or power consumption of the
1076 config ARM_ERRATA_751472
1077 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1079 depends on !ARCH_MULTIPLATFORM
1081 This option enables the workaround for the 751472 Cortex-A9 (prior
1082 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1083 completion of a following broadcasted operation if the second
1084 operation is received by a CPU before the ICIALLUIS has completed,
1085 potentially leading to corrupted entries in the cache or TLB.
1087 config ARM_ERRATA_754322
1088 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1091 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1092 r3p*) erratum. A speculative memory access may cause a page table walk
1093 which starts prior to an ASID switch but completes afterwards. This
1094 can populate the micro-TLB with a stale entry which may be hit with
1095 the new ASID. This workaround places two dsb instructions in the mm
1096 switching code so that no page table walks can cross the ASID switch.
1098 config ARM_ERRATA_754327
1099 bool "ARM errata: no automatic Store Buffer drain"
1100 depends on CPU_V7 && SMP
1102 This option enables the workaround for the 754327 Cortex-A9 (prior to
1103 r2p0) erratum. The Store Buffer does not have any automatic draining
1104 mechanism and therefore a livelock may occur if an external agent
1105 continuously polls a memory location waiting to observe an update.
1106 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1107 written polling loops from denying visibility of updates to memory.
1109 config ARM_ERRATA_364296
1110 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1113 This options enables the workaround for the 364296 ARM1136
1114 r0p2 erratum (possible cache data corruption with
1115 hit-under-miss enabled). It sets the undocumented bit 31 in
1116 the auxiliary control register and the FI bit in the control
1117 register, thus disabling hit-under-miss without putting the
1118 processor into full low interrupt latency mode. ARM11MPCore
1121 config ARM_ERRATA_764369
1122 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1123 depends on CPU_V7 && SMP
1125 This option enables the workaround for erratum 764369
1126 affecting Cortex-A9 MPCore with two or more processors (all
1127 current revisions). Under certain timing circumstances, a data
1128 cache line maintenance operation by MVA targeting an Inner
1129 Shareable memory region may fail to proceed up to either the
1130 Point of Coherency or to the Point of Unification of the
1131 system. This workaround adds a DSB instruction before the
1132 relevant cache maintenance functions and sets a specific bit
1133 in the diagnostic control register of the SCU.
1135 config ARM_ERRATA_775420
1136 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1139 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1140 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1141 operation aborts with MMU exception, it might cause the processor
1142 to deadlock. This workaround puts DSB before executing ISB if
1143 an abort may occur on cache maintenance.
1145 config ARM_ERRATA_798181
1146 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1147 depends on CPU_V7 && SMP
1149 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1150 adequately shooting down all use of the old entries. This
1151 option enables the Linux kernel workaround for this erratum
1152 which sends an IPI to the CPUs that are running the same ASID
1153 as the one being invalidated.
1155 config ARM_ERRATA_773022
1156 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1159 This option enables the workaround for the 773022 Cortex-A15
1160 (up to r0p4) erratum. In certain rare sequences of code, the
1161 loop buffer may deliver incorrect instructions. This
1162 workaround disables the loop buffer to avoid the erratum.
1164 config ARM_ERRATA_818325_852422
1165 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1168 This option enables the workaround for:
1169 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1170 instruction might deadlock. Fixed in r0p1.
1171 - Cortex-A12 852422: Execution of a sequence of instructions might
1172 lead to either a data corruption or a CPU deadlock. Not fixed in
1173 any Cortex-A12 cores yet.
1174 This workaround for all both errata involves setting bit[12] of the
1175 Feature Register. This bit disables an optimisation applied to a
1176 sequence of 2 instructions that use opposing condition codes.
1178 config ARM_ERRATA_821420
1179 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1182 This option enables the workaround for the 821420 Cortex-A12
1183 (all revs) erratum. In very rare timing conditions, a sequence
1184 of VMOV to Core registers instructions, for which the second
1185 one is in the shadow of a branch or abort, can lead to a
1186 deadlock when the VMOV instructions are issued out-of-order.
1188 config ARM_ERRATA_825619
1189 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1192 This option enables the workaround for the 825619 Cortex-A12
1193 (all revs) erratum. Within rare timing constraints, executing a
1194 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1195 and Device/Strongly-Ordered loads and stores might cause deadlock
1197 config ARM_ERRATA_852421
1198 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1201 This option enables the workaround for the 852421 Cortex-A17
1202 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1203 execution of a DMB ST instruction might fail to properly order
1204 stores from GroupA and stores from GroupB.
1206 config ARM_ERRATA_852423
1207 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1210 This option enables the workaround for:
1211 - Cortex-A17 852423: Execution of a sequence of instructions might
1212 lead to either a data corruption or a CPU deadlock. Not fixed in
1213 any Cortex-A17 cores yet.
1214 This is identical to Cortex-A12 erratum 852422. It is a separate
1215 config option from the A12 erratum due to the way errata are checked
1220 source "arch/arm/common/Kconfig"
1227 Find out whether you have ISA slots on your motherboard. ISA is the
1228 name of a bus system, i.e. the way the CPU talks to the other stuff
1229 inside your box. Other bus systems are PCI, EISA, MicroChannel
1230 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1231 newer boards don't support it. If you have ISA, say Y, otherwise N.
1233 # Select ISA DMA controller support
1238 # Select ISA DMA interface
1243 bool "PCI support" if MIGHT_HAVE_PCI
1245 Find out whether you have a PCI motherboard. PCI is the name of a
1246 bus system, i.e. the way the CPU talks to the other stuff inside
1247 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1248 VESA. If you have PCI, say Y, otherwise N.
1254 config PCI_DOMAINS_GENERIC
1255 def_bool PCI_DOMAINS
1257 config PCI_NANOENGINE
1258 bool "BSE nanoEngine PCI support"
1259 depends on SA1100_NANOENGINE
1261 Enable PCI on the BSE nanoEngine board.
1266 config PCI_HOST_ITE8152
1268 depends on PCI && MACH_ARMCORE
1272 source "drivers/pci/Kconfig"
1274 source "drivers/pcmcia/Kconfig"
1278 menu "Kernel Features"
1283 This option should be selected by machines which have an SMP-
1286 The only effect of this option is to make the SMP-related
1287 options available to the user for configuration.
1290 bool "Symmetric Multi-Processing"
1291 depends on CPU_V6K || CPU_V7
1292 depends on GENERIC_CLOCKEVENTS
1294 depends on MMU || ARM_MPU
1297 This enables support for systems with more than one CPU. If you have
1298 a system with only one CPU, say N. If you have a system with more
1299 than one CPU, say Y.
1301 If you say N here, the kernel will run on uni- and multiprocessor
1302 machines, but will use only one CPU of a multiprocessor machine. If
1303 you say Y here, the kernel will run on many, but not all,
1304 uniprocessor machines. On a uniprocessor machine, the kernel
1305 will run faster if you say N here.
1307 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1308 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1309 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1311 If you don't know what to do here, say N.
1314 bool "Allow booting SMP kernel on uniprocessor systems"
1315 depends on SMP && !XIP_KERNEL && MMU
1318 SMP kernels contain instructions which fail on non-SMP processors.
1319 Enabling this option allows the kernel to modify itself to make
1320 these instructions safe. Disabling it allows about 1K of space
1323 If you don't know what to do here, say Y.
1325 config ARM_CPU_TOPOLOGY
1326 bool "Support cpu topology definition"
1327 depends on SMP && CPU_V7
1330 Support ARM cpu topology definition. The MPIDR register defines
1331 affinity between processors which is then used to describe the cpu
1332 topology of an ARM System.
1335 bool "Multi-core scheduler support"
1336 depends on ARM_CPU_TOPOLOGY
1338 Multi-core scheduler support improves the CPU scheduler's decision
1339 making when dealing with multi-core CPU chips at a cost of slightly
1340 increased overhead in some places. If unsure say N here.
1343 bool "SMT scheduler support"
1344 depends on ARM_CPU_TOPOLOGY
1346 Improves the CPU scheduler's decision making when dealing with
1347 MultiThreading at a cost of slightly increased overhead in some
1348 places. If unsure say N here.
1353 This option enables support for the ARM system coherency unit
1355 config HAVE_ARM_ARCH_TIMER
1356 bool "Architected timer support"
1358 select ARM_ARCH_TIMER
1359 select GENERIC_CLOCKEVENTS
1361 This option enables support for the ARM architected timer
1365 select TIMER_OF if OF
1367 This options enables support for the ARM timer and watchdog unit
1370 bool "Multi-Cluster Power Management"
1371 depends on CPU_V7 && SMP
1373 This option provides the common power management infrastructure
1374 for (multi-)cluster based systems, such as big.LITTLE based
1377 config MCPM_QUAD_CLUSTER
1381 To avoid wasting resources unnecessarily, MCPM only supports up
1382 to 2 clusters by default.
1383 Platforms with 3 or 4 clusters that use MCPM must select this
1384 option to allow the additional clusters to be managed.
1387 bool "big.LITTLE support (Experimental)"
1388 depends on CPU_V7 && SMP
1391 This option enables support selections for the big.LITTLE
1392 system architecture.
1395 bool "big.LITTLE switcher support"
1396 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1399 The big.LITTLE "switcher" provides the core functionality to
1400 transparently handle transition between a cluster of A15's
1401 and a cluster of A7's in a big.LITTLE system.
1403 config BL_SWITCHER_DUMMY_IF
1404 tristate "Simple big.LITTLE switcher user interface"
1405 depends on BL_SWITCHER && DEBUG_KERNEL
1407 This is a simple and dummy char dev interface to control
1408 the big.LITTLE switcher core code. It is meant for
1409 debugging purposes only.
1412 prompt "Memory split"
1416 Select the desired split between kernel and user memory.
1418 If you are not absolutely sure what you are doing, leave this
1422 bool "3G/1G user/kernel split"
1423 config VMSPLIT_3G_OPT
1424 depends on !ARM_LPAE
1425 bool "3G/1G user/kernel split (for full 1G low memory)"
1427 bool "2G/2G user/kernel split"
1429 bool "1G/3G user/kernel split"
1434 default PHYS_OFFSET if !MMU
1435 default 0x40000000 if VMSPLIT_1G
1436 default 0x80000000 if VMSPLIT_2G
1437 default 0xB0000000 if VMSPLIT_3G_OPT
1441 int "Maximum number of CPUs (2-32)"
1447 bool "Support for hot-pluggable CPUs"
1450 Say Y here to experiment with turning CPUs off and on. CPUs
1451 can be controlled through /sys/devices/system/cpu.
1454 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1455 depends on HAVE_ARM_SMCCC
1458 Say Y here if you want Linux to communicate with system firmware
1459 implementing the PSCI specification for CPU-centric power
1460 management operations described in ARM document number ARM DEN
1461 0022A ("Power State Coordination Interface System Software on
1464 # The GPIO number here must be sorted by descending number. In case of
1465 # a multiplatform kernel, we just want the highest value required by the
1466 # selected platforms.
1469 default 2048 if ARCH_SOCFPGA
1470 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1472 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1473 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1474 default 416 if ARCH_SUNXI
1475 default 392 if ARCH_U8500
1476 default 352 if ARCH_VT8500
1477 default 288 if ARCH_ROCKCHIP
1478 default 264 if MACH_H4700
1481 Maximum number of GPIOs in the system.
1483 If unsure, leave the default value.
1485 source kernel/Kconfig.preempt
1489 default 200 if ARCH_EBSA110
1490 default 128 if SOC_AT91RM9200
1494 depends on HZ_FIXED = 0
1495 prompt "Timer frequency"
1519 default HZ_FIXED if HZ_FIXED != 0
1520 default 100 if HZ_100
1521 default 200 if HZ_200
1522 default 250 if HZ_250
1523 default 300 if HZ_300
1524 default 500 if HZ_500
1528 def_bool HIGH_RES_TIMERS
1530 config THUMB2_KERNEL
1531 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1532 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1533 default y if CPU_THUMBONLY
1536 By enabling this option, the kernel will be compiled in
1541 config THUMB2_AVOID_R_ARM_THM_JUMP11
1542 bool "Work around buggy Thumb-2 short branch relocations in gas"
1543 depends on THUMB2_KERNEL && MODULES
1546 Various binutils versions can resolve Thumb-2 branches to
1547 locally-defined, preemptible global symbols as short-range "b.n"
1548 branch instructions.
1550 This is a problem, because there's no guarantee the final
1551 destination of the symbol, or any candidate locations for a
1552 trampoline, are within range of the branch. For this reason, the
1553 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1554 relocation in modules at all, and it makes little sense to add
1557 The symptom is that the kernel fails with an "unsupported
1558 relocation" error when loading some modules.
1560 Until fixed tools are available, passing
1561 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1562 code which hits this problem, at the cost of a bit of extra runtime
1563 stack usage in some cases.
1565 The problem is described in more detail at:
1566 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1568 Only Thumb-2 kernels are affected.
1570 Unless you are sure your tools don't have this problem, say Y.
1572 config ARM_PATCH_IDIV
1573 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1574 depends on CPU_32v7 && !XIP_KERNEL
1577 The ARM compiler inserts calls to __aeabi_idiv() and
1578 __aeabi_uidiv() when it needs to perform division on signed
1579 and unsigned integers. Some v7 CPUs have support for the sdiv
1580 and udiv instructions that can be used to implement those
1583 Enabling this option allows the kernel to modify itself to
1584 replace the first two instructions of these library functions
1585 with the sdiv or udiv plus "bx lr" instructions when the CPU
1586 it is running on supports them. Typically this will be faster
1587 and less power intensive than running the original library
1588 code to do integer division.
1591 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1592 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1594 This option allows for the kernel to be compiled using the latest
1595 ARM ABI (aka EABI). This is only useful if you are using a user
1596 space environment that is also compiled with EABI.
1598 Since there are major incompatibilities between the legacy ABI and
1599 EABI, especially with regard to structure member alignment, this
1600 option also changes the kernel syscall calling convention to
1601 disambiguate both ABIs and allow for backward compatibility support
1602 (selected with CONFIG_OABI_COMPAT).
1604 To use this you need GCC version 4.0.0 or later.
1607 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1608 depends on AEABI && !THUMB2_KERNEL
1610 This option preserves the old syscall interface along with the
1611 new (ARM EABI) one. It also provides a compatibility layer to
1612 intercept syscalls that have structure arguments which layout
1613 in memory differs between the legacy ABI and the new ARM EABI
1614 (only for non "thumb" binaries). This option adds a tiny
1615 overhead to all syscalls and produces a slightly larger kernel.
1617 The seccomp filter system will not be available when this is
1618 selected, since there is no way yet to sensibly distinguish
1619 between calling conventions during filtering.
1621 If you know you'll be using only pure EABI user space then you
1622 can say N here. If this option is not selected and you attempt
1623 to execute a legacy ABI binary then the result will be
1624 UNPREDICTABLE (in fact it can be predicted that it won't work
1625 at all). If in doubt say N.
1627 config ARCH_HAS_HOLES_MEMORYMODEL
1630 config ARCH_SPARSEMEM_ENABLE
1633 config ARCH_SPARSEMEM_DEFAULT
1634 def_bool ARCH_SPARSEMEM_ENABLE
1636 config ARCH_SELECT_MEMORY_MODEL
1637 def_bool ARCH_SPARSEMEM_ENABLE
1639 config HAVE_ARCH_PFN_VALID
1640 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1642 config HAVE_GENERIC_GUP
1647 bool "High Memory Support"
1650 The address space of ARM processors is only 4 Gigabytes large
1651 and it has to accommodate user address space, kernel address
1652 space as well as some memory mapped IO. That means that, if you
1653 have a large amount of physical memory and/or IO, not all of the
1654 memory can be "permanently mapped" by the kernel. The physical
1655 memory that is not permanently mapped is called "high memory".
1657 Depending on the selected kernel/user memory split, minimum
1658 vmalloc space and actual amount of RAM, you may not need this
1659 option which should result in a slightly faster kernel.
1664 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1668 The VM uses one page of physical memory for each page table.
1669 For systems with a lot of processes, this can use a lot of
1670 precious low memory, eventually leading to low memory being
1671 consumed by page tables. Setting this option will allow
1672 user-space 2nd level page tables to reside in high memory.
1674 config CPU_SW_DOMAIN_PAN
1675 bool "Enable use of CPU domains to implement privileged no-access"
1676 depends on MMU && !ARM_LPAE
1679 Increase kernel security by ensuring that normal kernel accesses
1680 are unable to access userspace addresses. This can help prevent
1681 use-after-free bugs becoming an exploitable privilege escalation
1682 by ensuring that magic values (such as LIST_POISON) will always
1683 fault when dereferenced.
1685 CPUs with low-vector mappings use a best-efforts implementation.
1686 Their lower 1MB needs to remain accessible for the vectors, but
1687 the remainder of userspace will become appropriately inaccessible.
1689 config HW_PERF_EVENTS
1693 config SYS_SUPPORTS_HUGETLBFS
1697 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1701 config ARCH_WANT_GENERAL_HUGETLB
1704 config ARM_MODULE_PLTS
1705 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1708 Allocate PLTs when loading modules so that jumps and calls whose
1709 targets are too far away for their relative offsets to be encoded
1710 in the instructions themselves can be bounced via veneers in the
1711 module's PLT. This allows modules to be allocated in the generic
1712 vmalloc area after the dedicated module memory area has been
1713 exhausted. The modules will use slightly more memory, but after
1714 rounding up to page size, the actual memory footprint is usually
1717 Say y if you are getting out of memory errors while loading modules
1721 config FORCE_MAX_ZONEORDER
1722 int "Maximum zone order"
1723 default "12" if SOC_AM33XX
1724 default "9" if SA1111 || ARCH_EFM32
1727 The kernel memory allocator divides physically contiguous memory
1728 blocks into "zones", where each zone is a power of two number of
1729 pages. This option selects the largest power of two that the kernel
1730 keeps in the memory allocator. If you need to allocate very large
1731 blocks of physically contiguous memory, then you may need to
1732 increase this value.
1734 This config option is actually maximum order plus one. For example,
1735 a value of 11 means that the largest free memory block is 2^10 pages.
1737 config ALIGNMENT_TRAP
1739 depends on CPU_CP15_MMU
1740 default y if !ARCH_EBSA110
1741 select HAVE_PROC_CPU if PROC_FS
1743 ARM processors cannot fetch/store information which is not
1744 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1745 address divisible by 4. On 32-bit ARM processors, these non-aligned
1746 fetch/store instructions will be emulated in software if you say
1747 here, which has a severe performance impact. This is necessary for
1748 correct operation of some network protocols. With an IP-only
1749 configuration it is safe to say N, otherwise say Y.
1751 config UACCESS_WITH_MEMCPY
1752 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1754 default y if CPU_FEROCEON
1756 Implement faster copy_to_user and clear_user methods for CPU
1757 cores where a 8-word STM instruction give significantly higher
1758 memory write throughput than a sequence of individual 32bit stores.
1760 A possible side effect is a slight increase in scheduling latency
1761 between threads sharing the same address space if they invoke
1762 such copy operations with large buffers.
1764 However, if the CPU data cache is using a write-allocate mode,
1765 this option is unlikely to provide any performance gain.
1769 prompt "Enable seccomp to safely compute untrusted bytecode"
1771 This kernel feature is useful for number crunching applications
1772 that may need to compute untrusted bytecode during their
1773 execution. By using pipes or other transports made available to
1774 the process as file descriptors supporting the read/write
1775 syscalls, it's possible to isolate those applications in
1776 their own address space using seccomp. Once seccomp is
1777 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1778 and the task is only allowed to execute a few safe syscalls
1779 defined by each seccomp mode.
1788 bool "Enable paravirtualization code"
1790 This changes the kernel so it can modify itself when it is run
1791 under a hypervisor, potentially improving performance significantly
1792 over full virtualization.
1794 config PARAVIRT_TIME_ACCOUNTING
1795 bool "Paravirtual steal time accounting"
1799 Select this option to enable fine granularity task steal time
1800 accounting. Time spent executing other tasks in parallel with
1801 the current vCPU is discounted from the vCPU power. To account for
1802 that, there can be a small performance impact.
1804 If in doubt, say N here.
1811 bool "Xen guest support on ARM"
1812 depends on ARM && AEABI && OF
1813 depends on CPU_V7 && !CPU_V6
1814 depends on !GENERIC_ATOMIC64
1816 select ARCH_DMA_ADDR_T_64BIT
1821 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1828 bool "Flattened Device Tree support"
1832 Include support for flattened device tree machine descriptions.
1835 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1838 This is the traditional way of passing data to the kernel at boot
1839 time. If you are solely relying on the flattened device tree (or
1840 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1841 to remove ATAGS support from your kernel binary. If unsure,
1844 config DEPRECATED_PARAM_STRUCT
1845 bool "Provide old way to pass kernel parameters"
1848 This was deprecated in 2001 and announced to live on for 5 years.
1849 Some old boot loaders still use this way.
1851 # Compressed boot loader in ROM. Yes, we really want to ask about
1852 # TEXT and BSS so we preserve their values in the config files.
1853 config ZBOOT_ROM_TEXT
1854 hex "Compressed ROM boot loader base address"
1857 The physical address at which the ROM-able zImage is to be
1858 placed in the target. Platforms which normally make use of
1859 ROM-able zImage formats normally set this to a suitable
1860 value in their defconfig file.
1862 If ZBOOT_ROM is not enabled, this has no effect.
1864 config ZBOOT_ROM_BSS
1865 hex "Compressed ROM boot loader BSS address"
1868 The base address of an area of read/write memory in the target
1869 for the ROM-able zImage which must be available while the
1870 decompressor is running. It must be large enough to hold the
1871 entire decompressed kernel plus an additional 128 KiB.
1872 Platforms which normally make use of ROM-able zImage formats
1873 normally set this to a suitable value in their defconfig file.
1875 If ZBOOT_ROM is not enabled, this has no effect.
1878 bool "Compressed boot loader in ROM/flash"
1879 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1880 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1882 Say Y here if you intend to execute your compressed kernel image
1883 (zImage) directly from ROM or flash. If unsure, say N.
1885 config ARM_APPENDED_DTB
1886 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1889 With this option, the boot code will look for a device tree binary
1890 (DTB) appended to zImage
1891 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1893 This is meant as a backward compatibility convenience for those
1894 systems with a bootloader that can't be upgraded to accommodate
1895 the documented boot protocol using a device tree.
1897 Beware that there is very little in terms of protection against
1898 this option being confused by leftover garbage in memory that might
1899 look like a DTB header after a reboot if no actual DTB is appended
1900 to zImage. Do not leave this option active in a production kernel
1901 if you don't intend to always append a DTB. Proper passing of the
1902 location into r2 of a bootloader provided DTB is always preferable
1905 config ARM_ATAG_DTB_COMPAT
1906 bool "Supplement the appended DTB with traditional ATAG information"
1907 depends on ARM_APPENDED_DTB
1909 Some old bootloaders can't be updated to a DTB capable one, yet
1910 they provide ATAGs with memory configuration, the ramdisk address,
1911 the kernel cmdline string, etc. Such information is dynamically
1912 provided by the bootloader and can't always be stored in a static
1913 DTB. To allow a device tree enabled kernel to be used with such
1914 bootloaders, this option allows zImage to extract the information
1915 from the ATAG list and store it at run time into the appended DTB.
1918 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1919 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1921 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1922 bool "Use bootloader kernel arguments if available"
1924 Uses the command-line options passed by the boot loader instead of
1925 the device tree bootargs property. If the boot loader doesn't provide
1926 any, the device tree bootargs property will be used.
1928 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1929 bool "Extend with bootloader kernel arguments"
1931 The command-line arguments provided by the boot loader will be
1932 appended to the the device tree bootargs property.
1937 string "Default kernel command string"
1940 On some architectures (EBSA110 and CATS), there is currently no way
1941 for the boot loader to pass arguments to the kernel. For these
1942 architectures, you should supply some command-line options at build
1943 time by entering them here. As a minimum, you should specify the
1944 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1947 prompt "Kernel command line type" if CMDLINE != ""
1948 default CMDLINE_FROM_BOOTLOADER
1951 config CMDLINE_FROM_BOOTLOADER
1952 bool "Use bootloader kernel arguments if available"
1954 Uses the command-line options passed by the boot loader. If
1955 the boot loader doesn't provide any, the default kernel command
1956 string provided in CMDLINE will be used.
1958 config CMDLINE_EXTEND
1959 bool "Extend bootloader kernel arguments"
1961 The command-line arguments provided by the boot loader will be
1962 appended to the default kernel command string.
1964 config CMDLINE_FORCE
1965 bool "Always use the default kernel command string"
1967 Always use the default kernel command string, even if the boot
1968 loader passes other arguments to the kernel.
1969 This is useful if you cannot or don't want to change the
1970 command-line options your boot loader passes to the kernel.
1974 bool "Kernel Execute-In-Place from ROM"
1975 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1977 Execute-In-Place allows the kernel to run from non-volatile storage
1978 directly addressable by the CPU, such as NOR flash. This saves RAM
1979 space since the text section of the kernel is not loaded from flash
1980 to RAM. Read-write sections, such as the data section and stack,
1981 are still copied to RAM. The XIP kernel is not compressed since
1982 it has to run directly from flash, so it will take more space to
1983 store it. The flash address used to link the kernel object files,
1984 and for storing it, is configuration dependent. Therefore, if you
1985 say Y here, you must know the proper physical address where to
1986 store the kernel image depending on your own flash memory usage.
1988 Also note that the make target becomes "make xipImage" rather than
1989 "make zImage" or "make Image". The final kernel binary to put in
1990 ROM memory will be arch/arm/boot/xipImage.
1994 config XIP_PHYS_ADDR
1995 hex "XIP Kernel Physical Location"
1996 depends on XIP_KERNEL
1997 default "0x00080000"
1999 This is the physical address in your flash memory the kernel will
2000 be linked for and stored to. This address is dependent on your
2003 config XIP_DEFLATED_DATA
2004 bool "Store kernel .data section compressed in ROM"
2005 depends on XIP_KERNEL
2008 Before the kernel is actually executed, its .data section has to be
2009 copied to RAM from ROM. This option allows for storing that data
2010 in compressed form and decompressed to RAM rather than merely being
2011 copied, saving some precious ROM space. A possible drawback is a
2012 slightly longer boot delay.
2015 bool "Kexec system call (EXPERIMENTAL)"
2016 depends on (!SMP || PM_SLEEP_SMP)
2020 kexec is a system call that implements the ability to shutdown your
2021 current kernel, and to start another kernel. It is like a reboot
2022 but it is independent of the system firmware. And like a reboot
2023 you can start any kernel with it, not just Linux.
2025 It is an ongoing process to be certain the hardware in a machine
2026 is properly shutdown, so do not be surprised if this code does not
2027 initially work for you.
2030 bool "Export atags in procfs"
2031 depends on ATAGS && KEXEC
2034 Should the atags used to boot the kernel be exported in an "atags"
2035 file in procfs. Useful with kexec.
2038 bool "Build kdump crash kernel (EXPERIMENTAL)"
2040 Generate crash dump after being started by kexec. This should
2041 be normally only set in special crash dump kernels which are
2042 loaded in the main kernel with kexec-tools into a specially
2043 reserved region and then later executed after a crash by
2044 kdump/kexec. The crash dump kernel must be compiled to a
2045 memory address not used by the main kernel
2047 For more details see Documentation/kdump/kdump.txt
2049 config AUTO_ZRELADDR
2050 bool "Auto calculation of the decompressed kernel image address"
2052 ZRELADDR is the physical address where the decompressed kernel
2053 image will be placed. If AUTO_ZRELADDR is selected, the address
2054 will be determined at run-time by masking the current IP with
2055 0xf8000000. This assumes the zImage being placed in the first 128MB
2056 from start of memory.
2062 bool "UEFI runtime support"
2063 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2065 select EFI_PARAMS_FROM_FDT
2068 select EFI_RUNTIME_WRAPPERS
2070 This option provides support for runtime services provided
2071 by UEFI firmware (such as non-volatile variables, realtime
2072 clock, and platform reset). A UEFI stub is also provided to
2073 allow the kernel to be booted as an EFI application. This
2074 is only useful for kernels that may run on systems that have
2078 bool "Enable support for SMBIOS (DMI) tables"
2082 This enables SMBIOS/DMI feature for systems.
2084 This option is only useful on systems that have UEFI firmware.
2085 However, even with this option, the resultant kernel should
2086 continue to boot on existing non-UEFI platforms.
2088 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2089 i.e., the the practice of identifying the platform via DMI to
2090 decide whether certain workarounds for buggy hardware and/or
2091 firmware need to be enabled. This would require the DMI subsystem
2092 to be enabled much earlier than we do on ARM, which is non-trivial.
2096 menu "CPU Power Management"
2098 source "drivers/cpufreq/Kconfig"
2100 source "drivers/cpuidle/Kconfig"
2104 menu "Floating point emulation"
2106 comment "At least one emulation must be selected"
2109 bool "NWFPE math emulation"
2110 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2112 Say Y to include the NWFPE floating point emulator in the kernel.
2113 This is necessary to run most binaries. Linux does not currently
2114 support floating point hardware so you need to say Y here even if
2115 your machine has an FPA or floating point co-processor podule.
2117 You may say N here if you are going to load the Acorn FPEmulator
2118 early in the bootup.
2121 bool "Support extended precision"
2122 depends on FPE_NWFPE
2124 Say Y to include 80-bit support in the kernel floating-point
2125 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2126 Note that gcc does not generate 80-bit operations by default,
2127 so in most cases this option only enlarges the size of the
2128 floating point emulator without any good reason.
2130 You almost surely want to say N here.
2133 bool "FastFPE math emulation (EXPERIMENTAL)"
2134 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2136 Say Y here to include the FAST floating point emulator in the kernel.
2137 This is an experimental much faster emulator which now also has full
2138 precision for the mantissa. It does not support any exceptions.
2139 It is very simple, and approximately 3-6 times faster than NWFPE.
2141 It should be sufficient for most programs. It may be not suitable
2142 for scientific calculations, but you have to check this for yourself.
2143 If you do not feel you need a faster FP emulation you should better
2147 bool "VFP-format floating point maths"
2148 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2150 Say Y to include VFP support code in the kernel. This is needed
2151 if your hardware includes a VFP unit.
2153 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2154 release notes and additional status information.
2156 Say N if your target does not have VFP hardware.
2164 bool "Advanced SIMD (NEON) Extension support"
2165 depends on VFPv3 && CPU_V7
2167 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2170 config KERNEL_MODE_NEON
2171 bool "Support for NEON in kernel mode"
2172 depends on NEON && AEABI
2174 Say Y to include support for NEON in kernel mode.
2178 menu "Userspace binary formats"
2180 source "fs/Kconfig.binfmt"
2184 menu "Power management options"
2186 source "kernel/power/Kconfig"
2188 config ARCH_SUSPEND_POSSIBLE
2189 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2190 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2193 config ARM_CPU_SUSPEND
2194 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2195 depends on ARCH_SUSPEND_POSSIBLE
2197 config ARCH_HIBERNATION_POSSIBLE
2200 default y if ARCH_SUSPEND_POSSIBLE
2204 source "net/Kconfig"
2206 source "drivers/Kconfig"
2208 source "drivers/firmware/Kconfig"
2212 source "arch/arm/Kconfig.debug"
2214 source "security/Kconfig"
2216 source "crypto/Kconfig"
2218 source "arch/arm/crypto/Kconfig"
2221 source "lib/Kconfig"
2223 source "arch/arm/kvm/Kconfig"