1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND
7 select ARCH_HAS_BINFMT_FLAT
8 select ARCH_HAS_CURRENT_STACK_POINTER
9 select ARCH_HAS_DEBUG_VIRTUAL if MMU
10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
11 select ARCH_HAS_ELF_RANDOMIZE
12 select ARCH_HAS_FORTIFY_SOURCE
13 select ARCH_HAS_KEEPINITRD
15 select ARCH_HAS_MEMBARRIER_SYNC_CORE
16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
18 select ARCH_HAS_PHYS_TO_DMA
19 select ARCH_HAS_SETUP_DMA_OPS
20 select ARCH_HAS_SET_MEMORY
21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
22 select ARCH_HAS_STRICT_MODULE_RWX if MMU
23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU
24 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU
25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
27 select ARCH_HAVE_CUSTOM_GPIO_H
28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
29 select ARCH_HAS_GCOV_PROFILE_ALL
30 select ARCH_KEEP_MEMBLOCK
31 select ARCH_MIGHT_HAVE_PC_PARPORT
32 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
35 select ARCH_SUPPORTS_ATOMIC_RMW
36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
37 select ARCH_USE_BUILTIN_BSWAP
38 select ARCH_USE_CMPXCHG_LOCKREF
39 select ARCH_USE_MEMTEST
40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
41 select ARCH_WANT_GENERAL_HUGETLB
42 select ARCH_WANT_IPC_PARSE_VERSION
43 select ARCH_WANT_LD_ORPHAN_WARN
44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
45 select BUILDTIME_TABLE_SORT if MMU
46 select CLONE_BACKWARDS
47 select CPU_PM if SUSPEND || CPU_IDLE
48 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
49 select DMA_DECLARE_COHERENT
50 select DMA_GLOBAL_POOL if !MMU
52 select DMA_NONCOHERENT_MMAP if MMU
54 select EDAC_ATOMIC_SCRUB
55 select GENERIC_ALLOCATOR
56 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
57 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
58 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
59 select GENERIC_IRQ_IPI if SMP
60 select GENERIC_CPU_AUTOPROBE
61 select GENERIC_EARLY_IOREMAP
62 select GENERIC_IDLE_POLL_SETUP
63 select GENERIC_IRQ_MULTI_HANDLER
64 select GENERIC_IRQ_PROBE
65 select GENERIC_IRQ_SHOW
66 select GENERIC_IRQ_SHOW_LEVEL
67 select GENERIC_LIB_DEVMEM_IS_ALLOWED
68 select GENERIC_PCI_IOMAP
69 select GENERIC_SCHED_CLOCK
70 select GENERIC_SMP_IDLE_THREAD
71 select HARDIRQS_SW_RESEND
72 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
73 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
74 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
75 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL
76 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
77 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
78 select HAVE_ARCH_MMAP_RND_BITS if MMU
79 select HAVE_ARCH_PFN_VALID
80 select HAVE_ARCH_SECCOMP
81 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
82 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
83 select HAVE_ARCH_TRACEHOOK
84 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
85 select HAVE_ARM_SMCCC if CPU_V7
86 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
87 select HAVE_CONTEXT_TRACKING
88 select HAVE_C_RECORDMCOUNT
89 select HAVE_BUILDTIME_MCOUNT_SORT
90 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
91 select HAVE_DMA_CONTIGUOUS if MMU
92 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
93 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
94 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
95 select HAVE_EXIT_THREAD
96 select HAVE_FAST_GUP if ARM_LPAE
97 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
98 select HAVE_FUNCTION_GRAPH_TRACER
99 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
100 select HAVE_GCC_PLUGINS
101 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
102 select HAVE_IRQ_TIME_ACCOUNTING
103 select HAVE_KERNEL_GZIP
104 select HAVE_KERNEL_LZ4
105 select HAVE_KERNEL_LZMA
106 select HAVE_KERNEL_LZO
107 select HAVE_KERNEL_XZ
108 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
109 select HAVE_KRETPROBES if HAVE_KPROBES
110 select HAVE_MOD_ARCH_SPECIFIC
112 select HAVE_OPTPROBES if !THUMB2_KERNEL
113 select HAVE_PERF_EVENTS
114 select HAVE_PERF_REGS
115 select HAVE_PERF_USER_STACK_DUMP
116 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
117 select HAVE_REGS_AND_STACK_ACCESS_API
119 select HAVE_STACKPROTECTOR
120 select HAVE_SYSCALL_TRACEPOINTS
122 select HAVE_VIRT_CPU_ACCOUNTING_GEN
123 select IRQ_FORCED_THREADING
124 select MODULES_USE_ELF_REL
125 select NEED_DMA_MAP_STATE
126 select OF_EARLY_FLATTREE if OF
128 select OLD_SIGSUSPEND3
129 select PCI_SYSCALL if PCI
130 select PERF_USE_VMALLOC
132 select SYS_SUPPORTS_APM_EMULATION
133 select THREAD_INFO_IN_TASK
134 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
135 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
136 # Above selects are sorted alphabetically; please add new ones
137 # according to that. Thanks.
139 The ARM series is a line of low-power-consumption RISC chip designs
140 licensed by ARM Ltd and targeted at embedded applications and
141 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
142 manufactured, but legacy ARM-based PC hardware remains popular in
143 Europe. There is an ARM Linux project with a web page at
144 <http://www.arm.linux.org.uk/>.
146 config ARM_HAS_GROUP_RELOCS
148 depends on !LD_IS_LLD || LLD_VERSION >= 140000
149 depends on !COMPILE_TEST
151 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group
152 relocations, which have been around for a long time, but were not
153 supported in LLD until version 14. The combined range is -/+ 256 MiB,
154 which is usually sufficient, but not for allyesconfig, so we disable
155 this feature when doing compile testing.
157 config ARM_HAS_SG_CHAIN
160 config ARM_DMA_USE_IOMMU
162 select ARM_HAS_SG_CHAIN
163 select NEED_SG_DMA_LENGTH
167 config ARM_DMA_IOMMU_ALIGNMENT
168 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
172 DMA mapping framework by default aligns all buffers to the smallest
173 PAGE_SIZE order which is greater than or equal to the requested buffer
174 size. This works well for buffers up to a few hundreds kilobytes, but
175 for larger buffers it just a waste of address space. Drivers which has
176 relatively small addressing window (like 64Mib) might run out of
177 virtual space with just a few allocations.
179 With this parameter you can specify the maximum PAGE_SIZE order for
180 DMA IOMMU buffers. Larger buffers will be aligned only to this
181 specified order. The order is expressed as a power of two multiplied
186 config SYS_SUPPORTS_APM_EMULATION
191 select GENERIC_ALLOCATOR
202 config STACKTRACE_SUPPORT
206 config LOCKDEP_SUPPORT
210 config ARCH_HAS_ILOG2_U32
213 config ARCH_HAS_ILOG2_U64
216 config ARCH_HAS_BANDGAP
219 config FIX_EARLYCON_MEM
222 config GENERIC_HWEIGHT
226 config GENERIC_CALIBRATE_DELAY
230 config ARCH_MAY_HAVE_PC_FDC
233 config ARCH_SUPPORTS_UPROBES
236 config GENERIC_ISA_DMA
245 config ARM_PATCH_PHYS_VIRT
246 bool "Patch physical to virtual translations at runtime" if EMBEDDED
248 depends on !XIP_KERNEL && MMU
250 Patch phys-to-virt and virt-to-phys translation functions at
251 boot and module load time according to the position of the
252 kernel in system memory.
254 This can only be used with non-XIP MMU kernels where the base
255 of physical memory is at a 2 MiB boundary.
257 Only disable this option if you know that you do not require
258 this feature (eg, building a kernel for a single machine) and
259 you need to shrink the kernel to the minimal size.
261 config NEED_MACH_IO_H
264 Select this when mach/io.h is required to provide special
265 definitions for this platform. The need for mach/io.h should
266 be avoided when possible.
268 config NEED_MACH_MEMORY_H
271 Select this when mach/memory.h is required to provide special
272 definitions for this platform. The need for mach/memory.h should
273 be avoided when possible.
276 hex "Physical address of main memory" if MMU
277 depends on !ARM_PATCH_PHYS_VIRT
278 default DRAM_BASE if !MMU
279 default 0x00000000 if ARCH_FOOTBRIDGE
280 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
281 default 0x30000000 if ARCH_S3C24XX
282 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA
283 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
286 Please provide the physical address corresponding to the
287 location of main memory in your system.
293 config PGTABLE_LEVELS
295 default 3 if ARM_LPAE
301 bool "MMU-based Paged Memory Management Support"
304 Select if you want MMU-based virtualised addressing space
305 support by paged memory management. If unsure, say 'Y'.
307 config ARM_SINGLE_ARMV7M
318 config ARCH_MMAP_RND_BITS_MIN
321 config ARCH_MMAP_RND_BITS_MAX
322 default 14 if PAGE_OFFSET=0x40000000
323 default 15 if PAGE_OFFSET=0x80000000
327 # The "ARM system type" choice list is ordered alphabetically by option
328 # text. Please add new entries in the option alphabetic order.
331 prompt "ARM system type"
333 default ARCH_MULTIPLATFORM
335 config ARCH_MULTIPLATFORM
336 bool "Allow multiple platforms to be selected"
337 select ARCH_FLATMEM_ENABLE
338 select ARCH_SPARSEMEM_ENABLE
339 select ARCH_SELECT_MEMORY_MODEL
340 select ARM_HAS_SG_CHAIN
341 select ARM_PATCH_PHYS_VIRT
346 select PCI_DOMAINS_GENERIC if PCI
350 config ARCH_FOOTBRIDGE
352 depends on CPU_LITTLE_ENDIAN
355 select NEED_MACH_MEMORY_H
357 Support for systems based on the DC21285 companion chip
358 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
361 bool "PXA2xx/PXA3xx-based"
362 depends on CPU_LITTLE_ENDIAN
364 select ARM_CPU_SUSPEND if PM
370 select CPU_XSCALE if !CPU_XSC3
377 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
381 depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000
382 depends on CPU_LITTLE_ENDIAN
384 select ARCH_MAY_HAVE_PC_FDC
385 select ARCH_SPARSEMEM_ENABLE
386 select ARM_HAS_SG_CHAIN
389 select HAVE_PATA_PLATFORM
391 select LEGACY_TIMER_TICK
392 select NEED_MACH_IO_H
393 select NEED_MACH_MEMORY_H
396 On the Acorn Risc-PC, Linux can support the internal IDE disk and
397 CD-ROM interface, serial and parallel port, and the floppy drive.
401 depends on CPU_LITTLE_ENDIAN
403 select ARCH_SPARSEMEM_ENABLE
406 select TIMER_OF if OF
413 select NEED_MACH_MEMORY_H
416 Support for StrongARM 11x0 based boards.
420 depends on CPU_LITTLE_ENDIAN
422 select FORCE_PCI if PCCARD
423 select GENERIC_IRQ_CHIP
425 select HAVE_LEGACY_CLK
429 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
433 menu "Multiple platform selection"
434 depends on ARCH_MULTIPLATFORM
436 comment "CPU Core family selection"
439 bool "ARMv4 based platforms (FA526)"
440 depends on !ARCH_MULTI_V6_V7
441 select ARCH_MULTI_V4_V5
444 config ARCH_MULTI_V4T
445 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
446 depends on !ARCH_MULTI_V6_V7
447 select ARCH_MULTI_V4_V5
448 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
449 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
450 CPU_ARM925T || CPU_ARM940T)
453 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
454 depends on !ARCH_MULTI_V6_V7
455 select ARCH_MULTI_V4_V5
456 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
457 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
458 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
460 config ARCH_MULTI_V4_V5
464 bool "ARMv6 based platforms (ARM11)"
465 select ARCH_MULTI_V6_V7
469 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
471 select ARCH_MULTI_V6_V7
475 config ARCH_MULTI_V6_V7
477 select MIGHT_HAVE_CACHE_L2X0
479 config ARCH_MULTI_CPU_AUTO
480 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
486 bool "Dummy Virtual Machine"
487 depends on ARCH_MULTI_V7
490 select ARM_GIC_V2M if PCI
492 select ARM_GIC_V3_ITS if PCI
494 select HAVE_ARM_ARCH_TIMER
497 bool "Airoha SoC Support"
498 depends on ARCH_MULTI_V7
503 select HAVE_ARM_ARCH_TIMER
506 Support for Airoha EN7523 SoCs
509 # This is sorted alphabetically by mach-* pathname. However, plat-*
510 # Kconfigs may be included either alphabetically (according to the
511 # plat- suffix) or along side the corresponding mach-* source.
513 source "arch/arm/mach-actions/Kconfig"
515 source "arch/arm/mach-alpine/Kconfig"
517 source "arch/arm/mach-artpec/Kconfig"
519 source "arch/arm/mach-asm9260/Kconfig"
521 source "arch/arm/mach-aspeed/Kconfig"
523 source "arch/arm/mach-at91/Kconfig"
525 source "arch/arm/mach-axxia/Kconfig"
527 source "arch/arm/mach-bcm/Kconfig"
529 source "arch/arm/mach-berlin/Kconfig"
531 source "arch/arm/mach-clps711x/Kconfig"
533 source "arch/arm/mach-cns3xxx/Kconfig"
535 source "arch/arm/mach-davinci/Kconfig"
537 source "arch/arm/mach-digicolor/Kconfig"
539 source "arch/arm/mach-dove/Kconfig"
541 source "arch/arm/mach-ep93xx/Kconfig"
543 source "arch/arm/mach-exynos/Kconfig"
545 source "arch/arm/mach-footbridge/Kconfig"
547 source "arch/arm/mach-gemini/Kconfig"
549 source "arch/arm/mach-highbank/Kconfig"
551 source "arch/arm/mach-hisi/Kconfig"
553 source "arch/arm/mach-imx/Kconfig"
555 source "arch/arm/mach-iop32x/Kconfig"
557 source "arch/arm/mach-ixp4xx/Kconfig"
559 source "arch/arm/mach-keystone/Kconfig"
561 source "arch/arm/mach-lpc32xx/Kconfig"
563 source "arch/arm/mach-mediatek/Kconfig"
565 source "arch/arm/mach-meson/Kconfig"
567 source "arch/arm/mach-milbeaut/Kconfig"
569 source "arch/arm/mach-mmp/Kconfig"
571 source "arch/arm/mach-moxart/Kconfig"
573 source "arch/arm/mach-mstar/Kconfig"
575 source "arch/arm/mach-mv78xx0/Kconfig"
577 source "arch/arm/mach-mvebu/Kconfig"
579 source "arch/arm/mach-mxs/Kconfig"
581 source "arch/arm/mach-nomadik/Kconfig"
583 source "arch/arm/mach-npcm/Kconfig"
585 source "arch/arm/mach-nspire/Kconfig"
587 source "arch/arm/mach-omap1/Kconfig"
589 source "arch/arm/mach-omap2/Kconfig"
591 source "arch/arm/mach-orion5x/Kconfig"
593 source "arch/arm/mach-oxnas/Kconfig"
595 source "arch/arm/mach-pxa/Kconfig"
596 source "arch/arm/plat-pxa/Kconfig"
598 source "arch/arm/mach-qcom/Kconfig"
600 source "arch/arm/mach-rda/Kconfig"
602 source "arch/arm/mach-realtek/Kconfig"
604 source "arch/arm/mach-rockchip/Kconfig"
606 source "arch/arm/mach-s3c/Kconfig"
608 source "arch/arm/mach-s5pv210/Kconfig"
610 source "arch/arm/mach-sa1100/Kconfig"
612 source "arch/arm/mach-shmobile/Kconfig"
614 source "arch/arm/mach-socfpga/Kconfig"
616 source "arch/arm/mach-spear/Kconfig"
618 source "arch/arm/mach-sti/Kconfig"
620 source "arch/arm/mach-stm32/Kconfig"
622 source "arch/arm/mach-sunxi/Kconfig"
624 source "arch/arm/mach-tegra/Kconfig"
626 source "arch/arm/mach-uniphier/Kconfig"
628 source "arch/arm/mach-ux500/Kconfig"
630 source "arch/arm/mach-versatile/Kconfig"
632 source "arch/arm/mach-vt8500/Kconfig"
634 source "arch/arm/mach-zynq/Kconfig"
636 # ARMv7-M architecture
638 bool "NXP LPC18xx/LPC43xx"
639 depends on ARM_SINGLE_ARMV7M
640 select ARCH_HAS_RESET_CONTROLLER
642 select CLKSRC_LPC32XX
645 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
646 high performance microcontrollers.
649 bool "ARM MPS2 platform"
650 depends on ARM_SINGLE_ARMV7M
654 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
655 with a range of available cores like Cortex-M3/M4/M7.
657 Please, note that depends which Application Note is used memory map
658 for the platform may vary, so adjustment of RAM base might be needed.
660 # Definitions to make life easier
668 select GENERIC_IRQ_CHIP
671 config PLAT_ORION_LEGACY
678 config PLAT_VERSATILE
681 source "arch/arm/mm/Kconfig"
684 bool "Enable iWMMXt support"
685 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
686 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
688 Enable support for iWMMXt context switching at run time if
689 running on a CPU that supports it.
692 source "arch/arm/Kconfig-nommu"
695 config PJ4B_ERRATA_4742
696 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
697 depends on CPU_PJ4B && MACH_ARMADA_370
700 When coming out of either a Wait for Interrupt (WFI) or a Wait for
701 Event (WFE) IDLE states, a specific timing sensitivity exists between
702 the retiring WFI/WFE instructions and the newly issued subsequent
703 instructions. This sensitivity can result in a CPU hang scenario.
705 The software must insert either a Data Synchronization Barrier (DSB)
706 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
709 config ARM_ERRATA_326103
710 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
713 Executing a SWP instruction to read-only memory does not set bit 11
714 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
715 treat the access as a read, preventing a COW from occurring and
716 causing the faulting task to livelock.
718 config ARM_ERRATA_411920
719 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
720 depends on CPU_V6 || CPU_V6K
722 Invalidation of the Instruction Cache operation can
723 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
724 It does not affect the MPCore. This option enables the ARM Ltd.
725 recommended workaround.
727 config ARM_ERRATA_430973
728 bool "ARM errata: Stale prediction on replaced interworking branch"
731 This option enables the workaround for the 430973 Cortex-A8
732 r1p* erratum. If a code sequence containing an ARM/Thumb
733 interworking branch is replaced with another code sequence at the
734 same virtual address, whether due to self-modifying code or virtual
735 to physical address re-mapping, Cortex-A8 does not recover from the
736 stale interworking branch prediction. This results in Cortex-A8
737 executing the new code sequence in the incorrect ARM or Thumb state.
738 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
739 and also flushes the branch target cache at every context switch.
740 Note that setting specific bits in the ACTLR register may not be
741 available in non-secure mode.
743 config ARM_ERRATA_458693
744 bool "ARM errata: Processor deadlock when a false hazard is created"
746 depends on !ARCH_MULTIPLATFORM
748 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
749 erratum. For very specific sequences of memory operations, it is
750 possible for a hazard condition intended for a cache line to instead
751 be incorrectly associated with a different cache line. This false
752 hazard might then cause a processor deadlock. The workaround enables
753 the L1 caching of the NEON accesses and disables the PLD instruction
754 in the ACTLR register. Note that setting specific bits in the ACTLR
755 register may not be available in non-secure mode.
757 config ARM_ERRATA_460075
758 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
760 depends on !ARCH_MULTIPLATFORM
762 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
763 erratum. Any asynchronous access to the L2 cache may encounter a
764 situation in which recent store transactions to the L2 cache are lost
765 and overwritten with stale memory contents from external memory. The
766 workaround disables the write-allocate mode for the L2 cache via the
767 ACTLR register. Note that setting specific bits in the ACTLR register
768 may not be available in non-secure mode.
770 config ARM_ERRATA_742230
771 bool "ARM errata: DMB operation may be faulty"
772 depends on CPU_V7 && SMP
773 depends on !ARCH_MULTIPLATFORM
775 This option enables the workaround for the 742230 Cortex-A9
776 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
777 between two write operations may not ensure the correct visibility
778 ordering of the two writes. This workaround sets a specific bit in
779 the diagnostic register of the Cortex-A9 which causes the DMB
780 instruction to behave as a DSB, ensuring the correct behaviour of
783 config ARM_ERRATA_742231
784 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
785 depends on CPU_V7 && SMP
786 depends on !ARCH_MULTIPLATFORM
788 This option enables the workaround for the 742231 Cortex-A9
789 (r2p0..r2p2) erratum. Under certain conditions, specific to the
790 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
791 accessing some data located in the same cache line, may get corrupted
792 data due to bad handling of the address hazard when the line gets
793 replaced from one of the CPUs at the same time as another CPU is
794 accessing it. This workaround sets specific bits in the diagnostic
795 register of the Cortex-A9 which reduces the linefill issuing
796 capabilities of the processor.
798 config ARM_ERRATA_643719
799 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
800 depends on CPU_V7 && SMP
803 This option enables the workaround for the 643719 Cortex-A9 (prior to
804 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
805 register returns zero when it should return one. The workaround
806 corrects this value, ensuring cache maintenance operations which use
807 it behave as intended and avoiding data corruption.
809 config ARM_ERRATA_720789
810 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
813 This option enables the workaround for the 720789 Cortex-A9 (prior to
814 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
815 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
816 As a consequence of this erratum, some TLB entries which should be
817 invalidated are not, resulting in an incoherency in the system page
818 tables. The workaround changes the TLB flushing routines to invalidate
819 entries regardless of the ASID.
821 config ARM_ERRATA_743622
822 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
824 depends on !ARCH_MULTIPLATFORM
826 This option enables the workaround for the 743622 Cortex-A9
827 (r2p*) erratum. Under very rare conditions, a faulty
828 optimisation in the Cortex-A9 Store Buffer may lead to data
829 corruption. This workaround sets a specific bit in the diagnostic
830 register of the Cortex-A9 which disables the Store Buffer
831 optimisation, preventing the defect from occurring. This has no
832 visible impact on the overall performance or power consumption of the
835 config ARM_ERRATA_751472
836 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
838 depends on !ARCH_MULTIPLATFORM
840 This option enables the workaround for the 751472 Cortex-A9 (prior
841 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
842 completion of a following broadcasted operation if the second
843 operation is received by a CPU before the ICIALLUIS has completed,
844 potentially leading to corrupted entries in the cache or TLB.
846 config ARM_ERRATA_754322
847 bool "ARM errata: possible faulty MMU translations following an ASID switch"
850 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
851 r3p*) erratum. A speculative memory access may cause a page table walk
852 which starts prior to an ASID switch but completes afterwards. This
853 can populate the micro-TLB with a stale entry which may be hit with
854 the new ASID. This workaround places two dsb instructions in the mm
855 switching code so that no page table walks can cross the ASID switch.
857 config ARM_ERRATA_754327
858 bool "ARM errata: no automatic Store Buffer drain"
859 depends on CPU_V7 && SMP
861 This option enables the workaround for the 754327 Cortex-A9 (prior to
862 r2p0) erratum. The Store Buffer does not have any automatic draining
863 mechanism and therefore a livelock may occur if an external agent
864 continuously polls a memory location waiting to observe an update.
865 This workaround defines cpu_relax() as smp_mb(), preventing correctly
866 written polling loops from denying visibility of updates to memory.
868 config ARM_ERRATA_364296
869 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
872 This options enables the workaround for the 364296 ARM1136
873 r0p2 erratum (possible cache data corruption with
874 hit-under-miss enabled). It sets the undocumented bit 31 in
875 the auxiliary control register and the FI bit in the control
876 register, thus disabling hit-under-miss without putting the
877 processor into full low interrupt latency mode. ARM11MPCore
880 config ARM_ERRATA_764369
881 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
882 depends on CPU_V7 && SMP
884 This option enables the workaround for erratum 764369
885 affecting Cortex-A9 MPCore with two or more processors (all
886 current revisions). Under certain timing circumstances, a data
887 cache line maintenance operation by MVA targeting an Inner
888 Shareable memory region may fail to proceed up to either the
889 Point of Coherency or to the Point of Unification of the
890 system. This workaround adds a DSB instruction before the
891 relevant cache maintenance functions and sets a specific bit
892 in the diagnostic control register of the SCU.
894 config ARM_ERRATA_764319
895 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"
898 This option enables the workaround for the 764319 Cortex A-9 erratum.
899 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an
900 unexpected Undefined Instruction exception when the DBGSWENABLE
901 external pin is set to 0, even when the CP14 accesses are performed
902 from a privileged mode. This work around catches the exception in a
903 way the kernel does not stop execution.
905 config ARM_ERRATA_775420
906 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
909 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
910 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
911 operation aborts with MMU exception, it might cause the processor
912 to deadlock. This workaround puts DSB before executing ISB if
913 an abort may occur on cache maintenance.
915 config ARM_ERRATA_798181
916 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
917 depends on CPU_V7 && SMP
919 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
920 adequately shooting down all use of the old entries. This
921 option enables the Linux kernel workaround for this erratum
922 which sends an IPI to the CPUs that are running the same ASID
923 as the one being invalidated.
925 config ARM_ERRATA_773022
926 bool "ARM errata: incorrect instructions may be executed from loop buffer"
929 This option enables the workaround for the 773022 Cortex-A15
930 (up to r0p4) erratum. In certain rare sequences of code, the
931 loop buffer may deliver incorrect instructions. This
932 workaround disables the loop buffer to avoid the erratum.
934 config ARM_ERRATA_818325_852422
935 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
938 This option enables the workaround for:
939 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
940 instruction might deadlock. Fixed in r0p1.
941 - Cortex-A12 852422: Execution of a sequence of instructions might
942 lead to either a data corruption or a CPU deadlock. Not fixed in
943 any Cortex-A12 cores yet.
944 This workaround for all both errata involves setting bit[12] of the
945 Feature Register. This bit disables an optimisation applied to a
946 sequence of 2 instructions that use opposing condition codes.
948 config ARM_ERRATA_821420
949 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
952 This option enables the workaround for the 821420 Cortex-A12
953 (all revs) erratum. In very rare timing conditions, a sequence
954 of VMOV to Core registers instructions, for which the second
955 one is in the shadow of a branch or abort, can lead to a
956 deadlock when the VMOV instructions are issued out-of-order.
958 config ARM_ERRATA_825619
959 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
962 This option enables the workaround for the 825619 Cortex-A12
963 (all revs) erratum. Within rare timing constraints, executing a
964 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
965 and Device/Strongly-Ordered loads and stores might cause deadlock
967 config ARM_ERRATA_857271
968 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
971 This option enables the workaround for the 857271 Cortex-A12
972 (all revs) erratum. Under very rare timing conditions, the CPU might
973 hang. The workaround is expected to have a < 1% performance impact.
975 config ARM_ERRATA_852421
976 bool "ARM errata: A17: DMB ST might fail to create order between stores"
979 This option enables the workaround for the 852421 Cortex-A17
980 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
981 execution of a DMB ST instruction might fail to properly order
982 stores from GroupA and stores from GroupB.
984 config ARM_ERRATA_852423
985 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
988 This option enables the workaround for:
989 - Cortex-A17 852423: Execution of a sequence of instructions might
990 lead to either a data corruption or a CPU deadlock. Not fixed in
991 any Cortex-A17 cores yet.
992 This is identical to Cortex-A12 erratum 852422. It is a separate
993 config option from the A12 erratum due to the way errata are checked
996 config ARM_ERRATA_857272
997 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1000 This option enables the workaround for the 857272 Cortex-A17 erratum.
1001 This erratum is not known to be fixed in any A17 revision.
1002 This is identical to Cortex-A12 erratum 857271. It is a separate
1003 config option from the A12 erratum due to the way errata are checked
1008 source "arch/arm/common/Kconfig"
1015 Find out whether you have ISA slots on your motherboard. ISA is the
1016 name of a bus system, i.e. the way the CPU talks to the other stuff
1017 inside your box. Other bus systems are PCI, EISA, MicroChannel
1018 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1019 newer boards don't support it. If you have ISA, say Y, otherwise N.
1021 # Select ISA DMA controller support
1026 # Select ISA DMA interface
1030 config PCI_NANOENGINE
1031 bool "BSE nanoEngine PCI support"
1032 depends on SA1100_NANOENGINE
1034 Enable PCI on the BSE nanoEngine board.
1036 config ARM_ERRATA_814220
1037 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1040 The v7 ARM states that all cache and branch predictor maintenance
1041 operations that do not specify an address execute, relative to
1042 each other, in program order.
1043 However, because of this erratum, an L2 set/way cache maintenance
1044 operation can overtake an L1 set/way cache maintenance operation.
1045 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1050 menu "Kernel Features"
1055 This option should be selected by machines which have an SMP-
1058 The only effect of this option is to make the SMP-related
1059 options available to the user for configuration.
1062 bool "Symmetric Multi-Processing"
1063 depends on CPU_V6K || CPU_V7
1065 depends on MMU || ARM_MPU
1068 This enables support for systems with more than one CPU. If you have
1069 a system with only one CPU, say N. If you have a system with more
1070 than one CPU, say Y.
1072 If you say N here, the kernel will run on uni- and multiprocessor
1073 machines, but will use only one CPU of a multiprocessor machine. If
1074 you say Y here, the kernel will run on many, but not all,
1075 uniprocessor machines. On a uniprocessor machine, the kernel
1076 will run faster if you say N here.
1078 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1079 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1080 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1082 If you don't know what to do here, say N.
1085 bool "Allow booting SMP kernel on uniprocessor systems"
1086 depends on SMP && !XIP_KERNEL && MMU
1089 SMP kernels contain instructions which fail on non-SMP processors.
1090 Enabling this option allows the kernel to modify itself to make
1091 these instructions safe. Disabling it allows about 1K of space
1094 If you don't know what to do here, say Y.
1097 config CURRENT_POINTER_IN_TPIDRURO
1099 depends on CPU_32v6K && !CPU_V6
1103 select HAVE_IRQ_EXIT_ON_IRQ_STACK
1104 select HAVE_SOFTIRQ_ON_OWN_STACK
1106 config ARM_CPU_TOPOLOGY
1107 bool "Support cpu topology definition"
1108 depends on SMP && CPU_V7
1111 Support ARM cpu topology definition. The MPIDR register defines
1112 affinity between processors which is then used to describe the cpu
1113 topology of an ARM System.
1116 bool "Multi-core scheduler support"
1117 depends on ARM_CPU_TOPOLOGY
1119 Multi-core scheduler support improves the CPU scheduler's decision
1120 making when dealing with multi-core CPU chips at a cost of slightly
1121 increased overhead in some places. If unsure say N here.
1124 bool "SMT scheduler support"
1125 depends on ARM_CPU_TOPOLOGY
1127 Improves the CPU scheduler's decision making when dealing with
1128 MultiThreading at a cost of slightly increased overhead in some
1129 places. If unsure say N here.
1134 This option enables support for the ARM snoop control unit
1136 config HAVE_ARM_ARCH_TIMER
1137 bool "Architected timer support"
1139 select ARM_ARCH_TIMER
1141 This option enables support for the ARM architected timer
1146 This options enables support for the ARM timer and watchdog unit
1149 bool "Multi-Cluster Power Management"
1150 depends on CPU_V7 && SMP
1152 This option provides the common power management infrastructure
1153 for (multi-)cluster based systems, such as big.LITTLE based
1156 config MCPM_QUAD_CLUSTER
1160 To avoid wasting resources unnecessarily, MCPM only supports up
1161 to 2 clusters by default.
1162 Platforms with 3 or 4 clusters that use MCPM must select this
1163 option to allow the additional clusters to be managed.
1166 bool "big.LITTLE support (Experimental)"
1167 depends on CPU_V7 && SMP
1170 This option enables support selections for the big.LITTLE
1171 system architecture.
1174 bool "big.LITTLE switcher support"
1175 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1178 The big.LITTLE "switcher" provides the core functionality to
1179 transparently handle transition between a cluster of A15's
1180 and a cluster of A7's in a big.LITTLE system.
1182 config BL_SWITCHER_DUMMY_IF
1183 tristate "Simple big.LITTLE switcher user interface"
1184 depends on BL_SWITCHER && DEBUG_KERNEL
1186 This is a simple and dummy char dev interface to control
1187 the big.LITTLE switcher core code. It is meant for
1188 debugging purposes only.
1191 prompt "Memory split"
1195 Select the desired split between kernel and user memory.
1197 If you are not absolutely sure what you are doing, leave this
1201 bool "3G/1G user/kernel split"
1202 config VMSPLIT_3G_OPT
1203 depends on !ARM_LPAE
1204 bool "3G/1G user/kernel split (for full 1G low memory)"
1206 bool "2G/2G user/kernel split"
1208 bool "1G/3G user/kernel split"
1213 default PHYS_OFFSET if !MMU
1214 default 0x40000000 if VMSPLIT_1G
1215 default 0x80000000 if VMSPLIT_2G
1216 default 0xB0000000 if VMSPLIT_3G_OPT
1219 config KASAN_SHADOW_OFFSET
1222 default 0x1f000000 if PAGE_OFFSET=0x40000000
1223 default 0x5f000000 if PAGE_OFFSET=0x80000000
1224 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1225 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1229 int "Maximum number of CPUs (2-32)"
1230 range 2 16 if DEBUG_KMAP_LOCAL
1231 range 2 32 if !DEBUG_KMAP_LOCAL
1235 The maximum number of CPUs that the kernel can support.
1236 Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1237 debugging is enabled, which uses half of the per-CPU fixmap
1238 slots as guard regions.
1241 bool "Support for hot-pluggable CPUs"
1243 select GENERIC_IRQ_MIGRATION
1245 Say Y here to experiment with turning CPUs off and on. CPUs
1246 can be controlled through /sys/devices/system/cpu.
1249 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1250 depends on HAVE_ARM_SMCCC
1253 Say Y here if you want Linux to communicate with system firmware
1254 implementing the PSCI specification for CPU-centric power
1255 management operations described in ARM document number ARM DEN
1256 0022A ("Power State Coordination Interface System Software on
1259 # The GPIO number here must be sorted by descending number. In case of
1260 # a multiplatform kernel, we just want the highest value required by the
1261 # selected platforms.
1264 default 2048 if ARCH_INTEL_SOCFPGA
1265 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1266 ARCH_ZYNQ || ARCH_ASPEED
1267 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1268 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1269 default 416 if ARCH_SUNXI
1270 default 392 if ARCH_U8500
1271 default 352 if ARCH_VT8500
1272 default 288 if ARCH_ROCKCHIP
1273 default 264 if MACH_H4700
1276 Maximum number of GPIOs in the system.
1278 If unsure, leave the default value.
1282 default 128 if SOC_AT91RM9200
1286 depends on HZ_FIXED = 0
1287 prompt "Timer frequency"
1311 default HZ_FIXED if HZ_FIXED != 0
1312 default 100 if HZ_100
1313 default 200 if HZ_200
1314 default 250 if HZ_250
1315 default 300 if HZ_300
1316 default 500 if HZ_500
1320 def_bool HIGH_RES_TIMERS
1322 config THUMB2_KERNEL
1323 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1324 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1325 default y if CPU_THUMBONLY
1328 By enabling this option, the kernel will be compiled in
1333 config ARM_PATCH_IDIV
1334 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1335 depends on CPU_32v7 && !XIP_KERNEL
1338 The ARM compiler inserts calls to __aeabi_idiv() and
1339 __aeabi_uidiv() when it needs to perform division on signed
1340 and unsigned integers. Some v7 CPUs have support for the sdiv
1341 and udiv instructions that can be used to implement those
1344 Enabling this option allows the kernel to modify itself to
1345 replace the first two instructions of these library functions
1346 with the sdiv or udiv plus "bx lr" instructions when the CPU
1347 it is running on supports them. Typically this will be faster
1348 and less power intensive than running the original library
1349 code to do integer division.
1352 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1353 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1354 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1356 This option allows for the kernel to be compiled using the latest
1357 ARM ABI (aka EABI). This is only useful if you are using a user
1358 space environment that is also compiled with EABI.
1360 Since there are major incompatibilities between the legacy ABI and
1361 EABI, especially with regard to structure member alignment, this
1362 option also changes the kernel syscall calling convention to
1363 disambiguate both ABIs and allow for backward compatibility support
1364 (selected with CONFIG_OABI_COMPAT).
1366 To use this you need GCC version 4.0.0 or later.
1369 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1370 depends on AEABI && !THUMB2_KERNEL
1372 This option preserves the old syscall interface along with the
1373 new (ARM EABI) one. It also provides a compatibility layer to
1374 intercept syscalls that have structure arguments which layout
1375 in memory differs between the legacy ABI and the new ARM EABI
1376 (only for non "thumb" binaries). This option adds a tiny
1377 overhead to all syscalls and produces a slightly larger kernel.
1379 The seccomp filter system will not be available when this is
1380 selected, since there is no way yet to sensibly distinguish
1381 between calling conventions during filtering.
1383 If you know you'll be using only pure EABI user space then you
1384 can say N here. If this option is not selected and you attempt
1385 to execute a legacy ABI binary then the result will be
1386 UNPREDICTABLE (in fact it can be predicted that it won't work
1387 at all). If in doubt say N.
1389 config ARCH_SELECT_MEMORY_MODEL
1392 config ARCH_FLATMEM_ENABLE
1395 config ARCH_SPARSEMEM_ENABLE
1397 select SPARSEMEM_STATIC if SPARSEMEM
1400 bool "High Memory Support"
1403 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY
1405 The address space of ARM processors is only 4 Gigabytes large
1406 and it has to accommodate user address space, kernel address
1407 space as well as some memory mapped IO. That means that, if you
1408 have a large amount of physical memory and/or IO, not all of the
1409 memory can be "permanently mapped" by the kernel. The physical
1410 memory that is not permanently mapped is called "high memory".
1412 Depending on the selected kernel/user memory split, minimum
1413 vmalloc space and actual amount of RAM, you may not need this
1414 option which should result in a slightly faster kernel.
1419 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1423 The VM uses one page of physical memory for each page table.
1424 For systems with a lot of processes, this can use a lot of
1425 precious low memory, eventually leading to low memory being
1426 consumed by page tables. Setting this option will allow
1427 user-space 2nd level page tables to reside in high memory.
1429 config CPU_SW_DOMAIN_PAN
1430 bool "Enable use of CPU domains to implement privileged no-access"
1431 depends on MMU && !ARM_LPAE
1434 Increase kernel security by ensuring that normal kernel accesses
1435 are unable to access userspace addresses. This can help prevent
1436 use-after-free bugs becoming an exploitable privilege escalation
1437 by ensuring that magic values (such as LIST_POISON) will always
1438 fault when dereferenced.
1440 CPUs with low-vector mappings use a best-efforts implementation.
1441 Their lower 1MB needs to remain accessible for the vectors, but
1442 the remainder of userspace will become appropriately inaccessible.
1444 config HW_PERF_EVENTS
1448 config ARM_MODULE_PLTS
1449 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1453 Allocate PLTs when loading modules so that jumps and calls whose
1454 targets are too far away for their relative offsets to be encoded
1455 in the instructions themselves can be bounced via veneers in the
1456 module's PLT. This allows modules to be allocated in the generic
1457 vmalloc area after the dedicated module memory area has been
1458 exhausted. The modules will use slightly more memory, but after
1459 rounding up to page size, the actual memory footprint is usually
1462 Disabling this is usually safe for small single-platform
1463 configurations. If unsure, say y.
1465 config FORCE_MAX_ZONEORDER
1466 int "Maximum zone order"
1467 default "12" if SOC_AM33XX
1468 default "9" if SA1111
1471 The kernel memory allocator divides physically contiguous memory
1472 blocks into "zones", where each zone is a power of two number of
1473 pages. This option selects the largest power of two that the kernel
1474 keeps in the memory allocator. If you need to allocate very large
1475 blocks of physically contiguous memory, then you may need to
1476 increase this value.
1478 This config option is actually maximum order plus one. For example,
1479 a value of 11 means that the largest free memory block is 2^10 pages.
1481 config ALIGNMENT_TRAP
1482 def_bool CPU_CP15_MMU
1483 select HAVE_PROC_CPU if PROC_FS
1485 ARM processors cannot fetch/store information which is not
1486 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1487 address divisible by 4. On 32-bit ARM processors, these non-aligned
1488 fetch/store instructions will be emulated in software if you say
1489 here, which has a severe performance impact. This is necessary for
1490 correct operation of some network protocols. With an IP-only
1491 configuration it is safe to say N, otherwise say Y.
1493 config UACCESS_WITH_MEMCPY
1494 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1496 default y if CPU_FEROCEON
1498 Implement faster copy_to_user and clear_user methods for CPU
1499 cores where a 8-word STM instruction give significantly higher
1500 memory write throughput than a sequence of individual 32bit stores.
1502 A possible side effect is a slight increase in scheduling latency
1503 between threads sharing the same address space if they invoke
1504 such copy operations with large buffers.
1506 However, if the CPU data cache is using a write-allocate mode,
1507 this option is unlikely to provide any performance gain.
1510 bool "Enable paravirtualization code"
1512 This changes the kernel so it can modify itself when it is run
1513 under a hypervisor, potentially improving performance significantly
1514 over full virtualization.
1516 config PARAVIRT_TIME_ACCOUNTING
1517 bool "Paravirtual steal time accounting"
1520 Select this option to enable fine granularity task steal time
1521 accounting. Time spent executing other tasks in parallel with
1522 the current vCPU is discounted from the vCPU power. To account for
1523 that, there can be a small performance impact.
1525 If in doubt, say N here.
1532 bool "Xen guest support on ARM"
1533 depends on ARM && AEABI && OF
1534 depends on CPU_V7 && !CPU_V6
1535 depends on !GENERIC_ATOMIC64
1537 select ARCH_DMA_ADDR_T_64BIT
1543 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1545 config CC_HAVE_STACKPROTECTOR_TLS
1546 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1548 config STACKPROTECTOR_PER_TASK
1549 bool "Use a unique stack canary value for each task"
1550 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA
1551 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS
1552 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS
1555 Due to the fact that GCC uses an ordinary symbol reference from
1556 which to load the value of the stack canary, this value can only
1557 change at reboot time on SMP systems, and all tasks running in the
1558 kernel's address space are forced to use the same canary value for
1559 the entire duration that the system is up.
1561 Enable this option to switch to a different method that uses a
1562 different canary value for each task.
1569 bool "Flattened Device Tree support"
1573 Include support for flattened device tree machine descriptions.
1576 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1579 This is the traditional way of passing data to the kernel at boot
1580 time. If you are solely relying on the flattened device tree (or
1581 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1582 to remove ATAGS support from your kernel binary. If unsure,
1585 config DEPRECATED_PARAM_STRUCT
1586 bool "Provide old way to pass kernel parameters"
1589 This was deprecated in 2001 and announced to live on for 5 years.
1590 Some old boot loaders still use this way.
1592 # Compressed boot loader in ROM. Yes, we really want to ask about
1593 # TEXT and BSS so we preserve their values in the config files.
1594 config ZBOOT_ROM_TEXT
1595 hex "Compressed ROM boot loader base address"
1598 The physical address at which the ROM-able zImage is to be
1599 placed in the target. Platforms which normally make use of
1600 ROM-able zImage formats normally set this to a suitable
1601 value in their defconfig file.
1603 If ZBOOT_ROM is not enabled, this has no effect.
1605 config ZBOOT_ROM_BSS
1606 hex "Compressed ROM boot loader BSS address"
1609 The base address of an area of read/write memory in the target
1610 for the ROM-able zImage which must be available while the
1611 decompressor is running. It must be large enough to hold the
1612 entire decompressed kernel plus an additional 128 KiB.
1613 Platforms which normally make use of ROM-able zImage formats
1614 normally set this to a suitable value in their defconfig file.
1616 If ZBOOT_ROM is not enabled, this has no effect.
1619 bool "Compressed boot loader in ROM/flash"
1620 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1621 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1623 Say Y here if you intend to execute your compressed kernel image
1624 (zImage) directly from ROM or flash. If unsure, say N.
1626 config ARM_APPENDED_DTB
1627 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1630 With this option, the boot code will look for a device tree binary
1631 (DTB) appended to zImage
1632 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1634 This is meant as a backward compatibility convenience for those
1635 systems with a bootloader that can't be upgraded to accommodate
1636 the documented boot protocol using a device tree.
1638 Beware that there is very little in terms of protection against
1639 this option being confused by leftover garbage in memory that might
1640 look like a DTB header after a reboot if no actual DTB is appended
1641 to zImage. Do not leave this option active in a production kernel
1642 if you don't intend to always append a DTB. Proper passing of the
1643 location into r2 of a bootloader provided DTB is always preferable
1646 config ARM_ATAG_DTB_COMPAT
1647 bool "Supplement the appended DTB with traditional ATAG information"
1648 depends on ARM_APPENDED_DTB
1650 Some old bootloaders can't be updated to a DTB capable one, yet
1651 they provide ATAGs with memory configuration, the ramdisk address,
1652 the kernel cmdline string, etc. Such information is dynamically
1653 provided by the bootloader and can't always be stored in a static
1654 DTB. To allow a device tree enabled kernel to be used with such
1655 bootloaders, this option allows zImage to extract the information
1656 from the ATAG list and store it at run time into the appended DTB.
1659 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1660 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1662 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1663 bool "Use bootloader kernel arguments if available"
1665 Uses the command-line options passed by the boot loader instead of
1666 the device tree bootargs property. If the boot loader doesn't provide
1667 any, the device tree bootargs property will be used.
1669 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1670 bool "Extend with bootloader kernel arguments"
1672 The command-line arguments provided by the boot loader will be
1673 appended to the the device tree bootargs property.
1678 string "Default kernel command string"
1681 On some architectures (e.g. CATS), there is currently no way
1682 for the boot loader to pass arguments to the kernel. For these
1683 architectures, you should supply some command-line options at build
1684 time by entering them here. As a minimum, you should specify the
1685 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1688 prompt "Kernel command line type" if CMDLINE != ""
1689 default CMDLINE_FROM_BOOTLOADER
1692 config CMDLINE_FROM_BOOTLOADER
1693 bool "Use bootloader kernel arguments if available"
1695 Uses the command-line options passed by the boot loader. If
1696 the boot loader doesn't provide any, the default kernel command
1697 string provided in CMDLINE will be used.
1699 config CMDLINE_EXTEND
1700 bool "Extend bootloader kernel arguments"
1702 The command-line arguments provided by the boot loader will be
1703 appended to the default kernel command string.
1705 config CMDLINE_FORCE
1706 bool "Always use the default kernel command string"
1708 Always use the default kernel command string, even if the boot
1709 loader passes other arguments to the kernel.
1710 This is useful if you cannot or don't want to change the
1711 command-line options your boot loader passes to the kernel.
1715 bool "Kernel Execute-In-Place from ROM"
1716 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1718 Execute-In-Place allows the kernel to run from non-volatile storage
1719 directly addressable by the CPU, such as NOR flash. This saves RAM
1720 space since the text section of the kernel is not loaded from flash
1721 to RAM. Read-write sections, such as the data section and stack,
1722 are still copied to RAM. The XIP kernel is not compressed since
1723 it has to run directly from flash, so it will take more space to
1724 store it. The flash address used to link the kernel object files,
1725 and for storing it, is configuration dependent. Therefore, if you
1726 say Y here, you must know the proper physical address where to
1727 store the kernel image depending on your own flash memory usage.
1729 Also note that the make target becomes "make xipImage" rather than
1730 "make zImage" or "make Image". The final kernel binary to put in
1731 ROM memory will be arch/arm/boot/xipImage.
1735 config XIP_PHYS_ADDR
1736 hex "XIP Kernel Physical Location"
1737 depends on XIP_KERNEL
1738 default "0x00080000"
1740 This is the physical address in your flash memory the kernel will
1741 be linked for and stored to. This address is dependent on your
1744 config XIP_DEFLATED_DATA
1745 bool "Store kernel .data section compressed in ROM"
1746 depends on XIP_KERNEL
1749 Before the kernel is actually executed, its .data section has to be
1750 copied to RAM from ROM. This option allows for storing that data
1751 in compressed form and decompressed to RAM rather than merely being
1752 copied, saving some precious ROM space. A possible drawback is a
1753 slightly longer boot delay.
1756 bool "Kexec system call (EXPERIMENTAL)"
1757 depends on (!SMP || PM_SLEEP_SMP)
1761 kexec is a system call that implements the ability to shutdown your
1762 current kernel, and to start another kernel. It is like a reboot
1763 but it is independent of the system firmware. And like a reboot
1764 you can start any kernel with it, not just Linux.
1766 It is an ongoing process to be certain the hardware in a machine
1767 is properly shutdown, so do not be surprised if this code does not
1768 initially work for you.
1771 bool "Export atags in procfs"
1772 depends on ATAGS && KEXEC
1775 Should the atags used to boot the kernel be exported in an "atags"
1776 file in procfs. Useful with kexec.
1779 bool "Build kdump crash kernel (EXPERIMENTAL)"
1781 Generate crash dump after being started by kexec. This should
1782 be normally only set in special crash dump kernels which are
1783 loaded in the main kernel with kexec-tools into a specially
1784 reserved region and then later executed after a crash by
1785 kdump/kexec. The crash dump kernel must be compiled to a
1786 memory address not used by the main kernel
1788 For more details see Documentation/admin-guide/kdump/kdump.rst
1790 config AUTO_ZRELADDR
1791 bool "Auto calculation of the decompressed kernel image address"
1793 ZRELADDR is the physical address where the decompressed kernel
1794 image will be placed. If AUTO_ZRELADDR is selected, the address
1795 will be determined at run-time, either by masking the current IP
1796 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1797 This assumes the zImage being placed in the first 128MB from
1804 bool "UEFI runtime support"
1805 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1807 select EFI_PARAMS_FROM_FDT
1809 select EFI_GENERIC_STUB
1810 select EFI_RUNTIME_WRAPPERS
1812 This option provides support for runtime services provided
1813 by UEFI firmware (such as non-volatile variables, realtime
1814 clock, and platform reset). A UEFI stub is also provided to
1815 allow the kernel to be booted as an EFI application. This
1816 is only useful for kernels that may run on systems that have
1820 bool "Enable support for SMBIOS (DMI) tables"
1824 This enables SMBIOS/DMI feature for systems.
1826 This option is only useful on systems that have UEFI firmware.
1827 However, even with this option, the resultant kernel should
1828 continue to boot on existing non-UEFI platforms.
1830 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1831 i.e., the the practice of identifying the platform via DMI to
1832 decide whether certain workarounds for buggy hardware and/or
1833 firmware need to be enabled. This would require the DMI subsystem
1834 to be enabled much earlier than we do on ARM, which is non-trivial.
1838 menu "CPU Power Management"
1840 source "drivers/cpufreq/Kconfig"
1842 source "drivers/cpuidle/Kconfig"
1846 menu "Floating point emulation"
1848 comment "At least one emulation must be selected"
1851 bool "NWFPE math emulation"
1852 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1854 Say Y to include the NWFPE floating point emulator in the kernel.
1855 This is necessary to run most binaries. Linux does not currently
1856 support floating point hardware so you need to say Y here even if
1857 your machine has an FPA or floating point co-processor podule.
1859 You may say N here if you are going to load the Acorn FPEmulator
1860 early in the bootup.
1863 bool "Support extended precision"
1864 depends on FPE_NWFPE
1866 Say Y to include 80-bit support in the kernel floating-point
1867 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1868 Note that gcc does not generate 80-bit operations by default,
1869 so in most cases this option only enlarges the size of the
1870 floating point emulator without any good reason.
1872 You almost surely want to say N here.
1875 bool "FastFPE math emulation (EXPERIMENTAL)"
1876 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1878 Say Y here to include the FAST floating point emulator in the kernel.
1879 This is an experimental much faster emulator which now also has full
1880 precision for the mantissa. It does not support any exceptions.
1881 It is very simple, and approximately 3-6 times faster than NWFPE.
1883 It should be sufficient for most programs. It may be not suitable
1884 for scientific calculations, but you have to check this for yourself.
1885 If you do not feel you need a faster FP emulation you should better
1889 bool "VFP-format floating point maths"
1890 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1892 Say Y to include VFP support code in the kernel. This is needed
1893 if your hardware includes a VFP unit.
1895 Please see <file:Documentation/arm/vfp/release-notes.rst> for
1896 release notes and additional status information.
1898 Say N if your target does not have VFP hardware.
1906 bool "Advanced SIMD (NEON) Extension support"
1907 depends on VFPv3 && CPU_V7
1909 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1912 config KERNEL_MODE_NEON
1913 bool "Support for NEON in kernel mode"
1914 depends on NEON && AEABI
1916 Say Y to include support for NEON in kernel mode.
1920 menu "Power management options"
1922 source "kernel/power/Kconfig"
1924 config ARCH_SUSPEND_POSSIBLE
1925 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1926 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
1929 config ARM_CPU_SUSPEND
1930 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1931 depends on ARCH_SUSPEND_POSSIBLE
1933 config ARCH_HIBERNATION_POSSIBLE
1936 default y if ARCH_SUSPEND_POSSIBLE
1941 source "arch/arm/crypto/Kconfig"
1944 source "arch/arm/Kconfig.assembler"