5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
46 config SYS_SUPPORTS_APM_EMULATION
49 config HAVE_SCHED_CLOCK
55 config ARCH_USES_GETTIMEOFFSET
59 config GENERIC_CLOCKEVENTS
62 config GENERIC_CLOCKEVENTS_BROADCAST
64 depends on GENERIC_CLOCKEVENTS
73 select GENERIC_ALLOCATOR
84 The Extended Industry Standard Architecture (EISA) bus was
85 developed as an open alternative to the IBM MicroChannel bus.
87 The EISA bus provided some of the features of the IBM MicroChannel
88 bus while maintaining backward compatibility with cards made for
89 the older ISA bus. The EISA bus saw limited use between 1988 and
90 1995 when it was made obsolete by the PCI bus.
92 Say Y here if you are building a kernel for an EISA-based machine.
102 MicroChannel Architecture is found in some IBM PS/2 machines and
103 laptops. It is a bus system similar to PCI or ISA. See
104 <file:Documentation/mca.txt> (and especially the web page given
105 there) before attempting to build an MCA bus kernel.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config HARDIRQS_SW_RESEND
128 config GENERIC_IRQ_PROBE
132 config GENERIC_LOCKBREAK
135 depends on SMP && PREEMPT
137 config RWSEM_GENERIC_SPINLOCK
141 config RWSEM_XCHGADD_ALGORITHM
144 config ARCH_HAS_ILOG2_U32
147 config ARCH_HAS_ILOG2_U64
150 config ARCH_HAS_CPUFREQ
153 Internal node to signify that the ARCH has CPUFREQ support
154 and that the relevant menu configurations are displayed for
157 config ARCH_HAS_CPU_IDLE_WAIT
160 config GENERIC_HWEIGHT
164 config GENERIC_CALIBRATE_DELAY
168 config ARCH_MAY_HAVE_PC_FDC
174 config NEED_DMA_MAP_STATE
177 config GENERIC_ISA_DMA
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 config ARM_PATCH_PHYS_VIRT
195 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
196 depends on EXPERIMENTAL
197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM
200 Patch phys-to-virt and virt-to-phys translation functions at
201 boot and module load time according to the position of the
202 kernel in system memory.
204 This can only be used with non-XIP MMU kernels where the base
205 of physical memory is at a 16MB boundary, or theoretically 64K
206 for the MSM machine class.
208 config ARM_PATCH_PHYS_VIRT_16BIT
210 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
212 This option extends the physical to virtual translation patching
213 to allow physical memory down to a theoretical minimum of 64K
216 source "init/Kconfig"
218 source "kernel/Kconfig.freezer"
223 bool "MMU-based Paged Memory Management Support"
226 Select if you want MMU-based virtualised addressing space
227 support by paged memory management. If unsure, say 'Y'.
230 # The "ARM system type" choice list is ordered alphabetically by option
231 # text. Please add new entries in the option alphabetic order.
234 prompt "ARM system type"
235 default ARCH_VERSATILE
237 config ARCH_INTEGRATOR
238 bool "ARM Ltd. Integrator family"
240 select ARCH_HAS_CPUFREQ
243 select GENERIC_CLOCKEVENTS
244 select PLAT_VERSATILE
245 select PLAT_VERSATILE_FPGA_IRQ
247 Support for ARM's Integrator platform.
250 bool "ARM Ltd. RealView family"
254 select GENERIC_CLOCKEVENTS
255 select ARCH_WANT_OPTIONAL_GPIOLIB
256 select PLAT_VERSATILE
257 select PLAT_VERSATILE_CLCD
258 select ARM_TIMER_SP804
259 select GPIO_PL061 if GPIOLIB
261 This enables support for ARM Ltd RealView boards.
263 config ARCH_VERSATILE
264 bool "ARM Ltd. Versatile family"
269 select GENERIC_CLOCKEVENTS
270 select ARCH_WANT_OPTIONAL_GPIOLIB
271 select PLAT_VERSATILE
272 select PLAT_VERSATILE_CLCD
273 select PLAT_VERSATILE_FPGA_IRQ
274 select ARM_TIMER_SP804
276 This enables support for ARM Ltd Versatile board.
279 bool "ARM Ltd. Versatile Express family"
280 select ARCH_WANT_OPTIONAL_GPIOLIB
282 select ARM_TIMER_SP804
284 select GENERIC_CLOCKEVENTS
286 select HAVE_PATA_PLATFORM
288 select PLAT_VERSATILE
289 select PLAT_VERSATILE_CLCD
291 This enables support for the ARM Ltd Versatile Express boards.
295 select ARCH_REQUIRE_GPIOLIB
298 This enables support for systems based on the Atmel AT91RM9200,
299 AT91SAM9 and AT91CAP9 processors.
302 bool "Broadcom BCMRING"
306 select ARM_TIMER_SP804
308 select GENERIC_CLOCKEVENTS
309 select ARCH_WANT_OPTIONAL_GPIOLIB
311 Support for Broadcom's BCMRing platform.
314 bool "Cirrus Logic CLPS711x/EP721x-based"
316 select ARCH_USES_GETTIMEOFFSET
318 Support for Cirrus Logic 711x/721x based boards.
321 bool "Cavium Networks CNS3XXX family"
323 select GENERIC_CLOCKEVENTS
325 select MIGHT_HAVE_PCI
326 select PCI_DOMAINS if PCI
328 Support for Cavium Networks CNS3XXX platform.
331 bool "Cortina Systems Gemini"
333 select ARCH_REQUIRE_GPIOLIB
334 select ARCH_USES_GETTIMEOFFSET
336 Support for the Cortina Systems Gemini family SoCs
343 select ARCH_USES_GETTIMEOFFSET
345 This is an evaluation board for the StrongARM processor available
346 from Digital. It has limited hardware on-board, including an
347 Ethernet interface, two PCMCIA sockets, two serial ports and a
356 select ARCH_REQUIRE_GPIOLIB
357 select ARCH_HAS_HOLES_MEMORYMODEL
358 select ARCH_USES_GETTIMEOFFSET
360 This enables support for the Cirrus EP93xx series of CPUs.
362 config ARCH_FOOTBRIDGE
366 select GENERIC_CLOCKEVENTS
368 Support for systems based on the DC21285 companion chip
369 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
372 bool "Freescale MXC/iMX-based"
373 select GENERIC_CLOCKEVENTS
374 select ARCH_REQUIRE_GPIOLIB
377 select HAVE_SCHED_CLOCK
379 Support for Freescale MXC/iMX-based family of processors
382 bool "Freescale MXS-based"
383 select GENERIC_CLOCKEVENTS
384 select ARCH_REQUIRE_GPIOLIB
388 Support for Freescale MXS-based family of processors
391 bool "Hilscher NetX based"
395 select GENERIC_CLOCKEVENTS
397 This enables support for systems based on the Hilscher NetX Soc
400 bool "Hynix HMS720x-based"
403 select ARCH_USES_GETTIMEOFFSET
405 This enables support for systems based on the Hynix HMS720x
413 select ARCH_SUPPORTS_MSI
416 Support for Intel's IOP13XX (XScale) family of processors.
424 select ARCH_REQUIRE_GPIOLIB
426 Support for Intel's 80219 and IOP32X (XScale) family of
435 select ARCH_REQUIRE_GPIOLIB
437 Support for Intel's IOP33X (XScale) family of processors.
444 select ARCH_USES_GETTIMEOFFSET
446 Support for Intel's IXP23xx (XScale) family of processors.
449 bool "IXP2400/2800-based"
453 select ARCH_USES_GETTIMEOFFSET
455 Support for Intel's IXP2400/2800 (XScale) family of processors.
463 select GENERIC_CLOCKEVENTS
464 select HAVE_SCHED_CLOCK
465 select MIGHT_HAVE_PCI
466 select DMABOUNCE if PCI
468 Support for Intel's IXP4XX (XScale) family of processors.
474 select ARCH_REQUIRE_GPIOLIB
475 select GENERIC_CLOCKEVENTS
478 Support for the Marvell Dove SoC 88AP510
481 bool "Marvell Kirkwood"
484 select ARCH_REQUIRE_GPIOLIB
485 select GENERIC_CLOCKEVENTS
488 Support for the following Marvell Kirkwood series SoCs:
489 88F6180, 88F6192 and 88F6281.
492 bool "Marvell Loki (88RC8480)"
494 select GENERIC_CLOCKEVENTS
497 Support for the Marvell Loki (88RC8480) SoC.
503 select ARCH_REQUIRE_GPIOLIB
506 select USB_ARCH_HAS_OHCI
509 select GENERIC_CLOCKEVENTS
511 Support for the NXP LPC32XX family of processors
514 bool "Marvell MV78xx0"
517 select ARCH_REQUIRE_GPIOLIB
518 select GENERIC_CLOCKEVENTS
521 Support for the following Marvell MV78xx0 series SoCs:
529 select ARCH_REQUIRE_GPIOLIB
530 select GENERIC_CLOCKEVENTS
533 Support for the following Marvell Orion 5x series SoCs:
534 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
535 Orion-2 (5281), Orion-1-90 (6183).
538 bool "Marvell PXA168/910/MMP2"
540 select ARCH_REQUIRE_GPIOLIB
542 select GENERIC_CLOCKEVENTS
543 select HAVE_SCHED_CLOCK
548 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
551 bool "Micrel/Kendin KS8695"
553 select ARCH_REQUIRE_GPIOLIB
554 select ARCH_USES_GETTIMEOFFSET
556 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
557 System-on-Chip devices.
560 bool "Nuvoton W90X900 CPU"
562 select ARCH_REQUIRE_GPIOLIB
565 select GENERIC_CLOCKEVENTS
567 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
568 At present, the w90x900 has been renamed nuc900, regarding
569 the ARM series product line, you can login the following
570 link address to know more.
572 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
573 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
576 bool "Nuvoton NUC93X CPU"
580 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
581 low-power and high performance MPEG-4/JPEG multimedia controller chip.
588 select GENERIC_CLOCKEVENTS
591 select HAVE_SCHED_CLOCK
592 select ARCH_HAS_BARRIERS if CACHE_L2X0
593 select ARCH_HAS_CPUFREQ
595 This enables support for NVIDIA Tegra based systems (Tegra APX,
596 Tegra 6xx and Tegra 2 series).
599 bool "Philips Nexperia PNX4008 Mobile"
602 select ARCH_USES_GETTIMEOFFSET
604 This enables support for Philips PNX4008 mobile platform.
607 bool "PXA2xx/PXA3xx-based"
610 select ARCH_HAS_CPUFREQ
613 select ARCH_REQUIRE_GPIOLIB
614 select GENERIC_CLOCKEVENTS
615 select HAVE_SCHED_CLOCK
620 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
625 select GENERIC_CLOCKEVENTS
626 select ARCH_REQUIRE_GPIOLIB
629 Support for Qualcomm MSM/QSD based systems. This runs on the
630 apps processor of the MSM/QSD and depends on a shared memory
631 interface to the modem processor which runs the baseband
632 stack and controls some vital subsystems
633 (clock and power control, etc).
636 bool "Renesas SH-Mobile / R-Mobile"
639 select GENERIC_CLOCKEVENTS
642 select MULTI_IRQ_HANDLER
644 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
651 select ARCH_MAY_HAVE_PC_FDC
652 select HAVE_PATA_PLATFORM
655 select ARCH_SPARSEMEM_ENABLE
656 select ARCH_USES_GETTIMEOFFSET
658 On the Acorn Risc-PC, Linux can support the internal IDE disk and
659 CD-ROM interface, serial and parallel port, and the floppy drive.
666 select ARCH_SPARSEMEM_ENABLE
668 select ARCH_HAS_CPUFREQ
670 select GENERIC_CLOCKEVENTS
672 select HAVE_SCHED_CLOCK
674 select ARCH_REQUIRE_GPIOLIB
676 Support for StrongARM 11x0 based boards.
679 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
681 select ARCH_HAS_CPUFREQ
683 select ARCH_USES_GETTIMEOFFSET
684 select HAVE_S3C2410_I2C if I2C
686 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
687 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
688 the Samsung SMDK2410 development board (and derivatives).
690 Note, the S3C2416 and the S3C2450 are so close that they even share
691 the same SoC ID code. This means that there is no separate machine
692 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
695 bool "Samsung S3C64XX"
701 select ARCH_USES_GETTIMEOFFSET
702 select ARCH_HAS_CPUFREQ
703 select ARCH_REQUIRE_GPIOLIB
704 select SAMSUNG_CLKSRC
705 select SAMSUNG_IRQ_VIC_TIMER
706 select SAMSUNG_IRQ_UART
707 select S3C_GPIO_TRACK
708 select S3C_GPIO_PULL_UPDOWN
709 select S3C_GPIO_CFG_S3C24XX
710 select S3C_GPIO_CFG_S3C64XX
712 select USB_ARCH_HAS_OHCI
713 select SAMSUNG_GPIOLIB_4BIT
714 select HAVE_S3C2410_I2C if I2C
715 select HAVE_S3C2410_WATCHDOG if WATCHDOG
717 Samsung S3C64XX series based systems
720 bool "Samsung S5P6440 S5P6450"
724 select HAVE_S3C2410_WATCHDOG if WATCHDOG
725 select GENERIC_CLOCKEVENTS
726 select HAVE_SCHED_CLOCK
727 select HAVE_S3C2410_I2C if I2C
728 select HAVE_S3C_RTC if RTC_CLASS
730 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
734 bool "Samsung S5P6442"
738 select ARCH_USES_GETTIMEOFFSET
739 select HAVE_S3C2410_WATCHDOG if WATCHDOG
741 Samsung S5P6442 CPU based systems
744 bool "Samsung S5PC100"
748 select ARM_L1_CACHE_SHIFT_6
749 select ARCH_USES_GETTIMEOFFSET
750 select HAVE_S3C2410_I2C if I2C
751 select HAVE_S3C_RTC if RTC_CLASS
752 select HAVE_S3C2410_WATCHDOG if WATCHDOG
754 Samsung S5PC100 series based systems
757 bool "Samsung S5PV210/S5PC110"
759 select ARCH_SPARSEMEM_ENABLE
762 select ARM_L1_CACHE_SHIFT_6
763 select ARCH_HAS_CPUFREQ
764 select GENERIC_CLOCKEVENTS
765 select HAVE_SCHED_CLOCK
766 select HAVE_S3C2410_I2C if I2C
767 select HAVE_S3C_RTC if RTC_CLASS
768 select HAVE_S3C2410_WATCHDOG if WATCHDOG
770 Samsung S5PV210/S5PC110 series based systems
773 bool "Samsung EXYNOS4"
775 select ARCH_SPARSEMEM_ENABLE
778 select ARCH_HAS_CPUFREQ
779 select GENERIC_CLOCKEVENTS
780 select HAVE_S3C_RTC if RTC_CLASS
781 select HAVE_S3C2410_I2C if I2C
782 select HAVE_S3C2410_WATCHDOG if WATCHDOG
784 Samsung EXYNOS4 series based systems
793 select ARCH_USES_GETTIMEOFFSET
795 Support for the StrongARM based Digital DNARD machine, also known
796 as "Shark" (<http://www.shark-linux.de/shark.html>).
799 bool "Telechips TCC ARM926-based systems"
804 select GENERIC_CLOCKEVENTS
806 Support for Telechips TCC ARM926-based systems.
809 bool "ST-Ericsson U300 Series"
813 select HAVE_SCHED_CLOCK
817 select GENERIC_CLOCKEVENTS
821 Support for ST-Ericsson U300 series mobile platforms.
824 bool "ST-Ericsson U8500 Series"
827 select GENERIC_CLOCKEVENTS
829 select ARCH_REQUIRE_GPIOLIB
830 select ARCH_HAS_CPUFREQ
832 Support for ST-Ericsson's Ux500 architecture
835 bool "STMicroelectronics Nomadik"
840 select GENERIC_CLOCKEVENTS
841 select ARCH_REQUIRE_GPIOLIB
843 Support for the Nomadik platform by ST-Ericsson
847 select GENERIC_CLOCKEVENTS
848 select ARCH_REQUIRE_GPIOLIB
852 select GENERIC_ALLOCATOR
853 select ARCH_HAS_HOLES_MEMORYMODEL
855 Support for TI's DaVinci platform.
860 select ARCH_REQUIRE_GPIOLIB
861 select ARCH_HAS_CPUFREQ
862 select GENERIC_CLOCKEVENTS
863 select HAVE_SCHED_CLOCK
864 select ARCH_HAS_HOLES_MEMORYMODEL
866 Support for TI's OMAP platform (OMAP1/2/3/4).
871 select ARCH_REQUIRE_GPIOLIB
874 select GENERIC_CLOCKEVENTS
877 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
880 bool "VIA/WonderMedia 85xx"
883 select ARCH_HAS_CPUFREQ
884 select GENERIC_CLOCKEVENTS
885 select ARCH_REQUIRE_GPIOLIB
888 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
892 # This is sorted alphabetically by mach-* pathname. However, plat-*
893 # Kconfigs may be included either alphabetically (according to the
894 # plat- suffix) or along side the corresponding mach-* source.
896 source "arch/arm/mach-at91/Kconfig"
898 source "arch/arm/mach-bcmring/Kconfig"
900 source "arch/arm/mach-clps711x/Kconfig"
902 source "arch/arm/mach-cns3xxx/Kconfig"
904 source "arch/arm/mach-davinci/Kconfig"
906 source "arch/arm/mach-dove/Kconfig"
908 source "arch/arm/mach-ep93xx/Kconfig"
910 source "arch/arm/mach-footbridge/Kconfig"
912 source "arch/arm/mach-gemini/Kconfig"
914 source "arch/arm/mach-h720x/Kconfig"
916 source "arch/arm/mach-integrator/Kconfig"
918 source "arch/arm/mach-iop32x/Kconfig"
920 source "arch/arm/mach-iop33x/Kconfig"
922 source "arch/arm/mach-iop13xx/Kconfig"
924 source "arch/arm/mach-ixp4xx/Kconfig"
926 source "arch/arm/mach-ixp2000/Kconfig"
928 source "arch/arm/mach-ixp23xx/Kconfig"
930 source "arch/arm/mach-kirkwood/Kconfig"
932 source "arch/arm/mach-ks8695/Kconfig"
934 source "arch/arm/mach-loki/Kconfig"
936 source "arch/arm/mach-lpc32xx/Kconfig"
938 source "arch/arm/mach-msm/Kconfig"
940 source "arch/arm/mach-mv78xx0/Kconfig"
942 source "arch/arm/plat-mxc/Kconfig"
944 source "arch/arm/mach-mxs/Kconfig"
946 source "arch/arm/mach-netx/Kconfig"
948 source "arch/arm/mach-nomadik/Kconfig"
949 source "arch/arm/plat-nomadik/Kconfig"
951 source "arch/arm/mach-nuc93x/Kconfig"
953 source "arch/arm/plat-omap/Kconfig"
955 source "arch/arm/mach-omap1/Kconfig"
957 source "arch/arm/mach-omap2/Kconfig"
959 source "arch/arm/mach-orion5x/Kconfig"
961 source "arch/arm/mach-pxa/Kconfig"
962 source "arch/arm/plat-pxa/Kconfig"
964 source "arch/arm/mach-mmp/Kconfig"
966 source "arch/arm/mach-realview/Kconfig"
968 source "arch/arm/mach-sa1100/Kconfig"
970 source "arch/arm/plat-samsung/Kconfig"
971 source "arch/arm/plat-s3c24xx/Kconfig"
972 source "arch/arm/plat-s5p/Kconfig"
974 source "arch/arm/plat-spear/Kconfig"
976 source "arch/arm/plat-tcc/Kconfig"
979 source "arch/arm/mach-s3c2400/Kconfig"
980 source "arch/arm/mach-s3c2410/Kconfig"
981 source "arch/arm/mach-s3c2412/Kconfig"
982 source "arch/arm/mach-s3c2416/Kconfig"
983 source "arch/arm/mach-s3c2440/Kconfig"
984 source "arch/arm/mach-s3c2443/Kconfig"
988 source "arch/arm/mach-s3c64xx/Kconfig"
991 source "arch/arm/mach-s5p64x0/Kconfig"
993 source "arch/arm/mach-s5p6442/Kconfig"
995 source "arch/arm/mach-s5pc100/Kconfig"
997 source "arch/arm/mach-s5pv210/Kconfig"
999 source "arch/arm/mach-exynos4/Kconfig"
1001 source "arch/arm/mach-shmobile/Kconfig"
1003 source "arch/arm/mach-tegra/Kconfig"
1005 source "arch/arm/mach-u300/Kconfig"
1007 source "arch/arm/mach-ux500/Kconfig"
1009 source "arch/arm/mach-versatile/Kconfig"
1011 source "arch/arm/mach-vexpress/Kconfig"
1012 source "arch/arm/plat-versatile/Kconfig"
1014 source "arch/arm/mach-vt8500/Kconfig"
1016 source "arch/arm/mach-w90x900/Kconfig"
1018 # Definitions to make life easier
1024 select GENERIC_CLOCKEVENTS
1025 select HAVE_SCHED_CLOCK
1030 select HAVE_SCHED_CLOCK
1035 config PLAT_VERSATILE
1038 config ARM_TIMER_SP804
1042 source arch/arm/mm/Kconfig
1045 bool "Enable iWMMXt support"
1046 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1047 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1049 Enable support for iWMMXt context switching at run time if
1050 running on a CPU that supports it.
1052 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1055 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1059 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1060 (!ARCH_OMAP3 || OMAP3_EMU)
1064 config MULTI_IRQ_HANDLER
1067 Allow each machine to specify it's own IRQ handler at run time.
1070 source "arch/arm/Kconfig-nommu"
1073 config ARM_ERRATA_411920
1074 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1075 depends on CPU_V6 || CPU_V6K
1077 Invalidation of the Instruction Cache operation can
1078 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1079 It does not affect the MPCore. This option enables the ARM Ltd.
1080 recommended workaround.
1082 config ARM_ERRATA_430973
1083 bool "ARM errata: Stale prediction on replaced interworking branch"
1086 This option enables the workaround for the 430973 Cortex-A8
1087 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1088 interworking branch is replaced with another code sequence at the
1089 same virtual address, whether due to self-modifying code or virtual
1090 to physical address re-mapping, Cortex-A8 does not recover from the
1091 stale interworking branch prediction. This results in Cortex-A8
1092 executing the new code sequence in the incorrect ARM or Thumb state.
1093 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1094 and also flushes the branch target cache at every context switch.
1095 Note that setting specific bits in the ACTLR register may not be
1096 available in non-secure mode.
1098 config ARM_ERRATA_458693
1099 bool "ARM errata: Processor deadlock when a false hazard is created"
1102 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1103 erratum. For very specific sequences of memory operations, it is
1104 possible for a hazard condition intended for a cache line to instead
1105 be incorrectly associated with a different cache line. This false
1106 hazard might then cause a processor deadlock. The workaround enables
1107 the L1 caching of the NEON accesses and disables the PLD instruction
1108 in the ACTLR register. Note that setting specific bits in the ACTLR
1109 register may not be available in non-secure mode.
1111 config ARM_ERRATA_460075
1112 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1115 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1116 erratum. Any asynchronous access to the L2 cache may encounter a
1117 situation in which recent store transactions to the L2 cache are lost
1118 and overwritten with stale memory contents from external memory. The
1119 workaround disables the write-allocate mode for the L2 cache via the
1120 ACTLR register. Note that setting specific bits in the ACTLR register
1121 may not be available in non-secure mode.
1123 config ARM_ERRATA_742230
1124 bool "ARM errata: DMB operation may be faulty"
1125 depends on CPU_V7 && SMP
1127 This option enables the workaround for the 742230 Cortex-A9
1128 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1129 between two write operations may not ensure the correct visibility
1130 ordering of the two writes. This workaround sets a specific bit in
1131 the diagnostic register of the Cortex-A9 which causes the DMB
1132 instruction to behave as a DSB, ensuring the correct behaviour of
1135 config ARM_ERRATA_742231
1136 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1137 depends on CPU_V7 && SMP
1139 This option enables the workaround for the 742231 Cortex-A9
1140 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1141 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1142 accessing some data located in the same cache line, may get corrupted
1143 data due to bad handling of the address hazard when the line gets
1144 replaced from one of the CPUs at the same time as another CPU is
1145 accessing it. This workaround sets specific bits in the diagnostic
1146 register of the Cortex-A9 which reduces the linefill issuing
1147 capabilities of the processor.
1149 config PL310_ERRATA_588369
1150 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1151 depends on CACHE_L2X0
1153 The PL310 L2 cache controller implements three types of Clean &
1154 Invalidate maintenance operations: by Physical Address
1155 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1156 They are architecturally defined to behave as the execution of a
1157 clean operation followed immediately by an invalidate operation,
1158 both performing to the same memory location. This functionality
1159 is not correctly implemented in PL310 as clean lines are not
1160 invalidated as a result of these operations.
1162 config ARM_ERRATA_720789
1163 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1164 depends on CPU_V7 && SMP
1166 This option enables the workaround for the 720789 Cortex-A9 (prior to
1167 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1168 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1169 As a consequence of this erratum, some TLB entries which should be
1170 invalidated are not, resulting in an incoherency in the system page
1171 tables. The workaround changes the TLB flushing routines to invalidate
1172 entries regardless of the ASID.
1174 config PL310_ERRATA_727915
1175 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1176 depends on CACHE_L2X0
1178 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1179 operation (offset 0x7FC). This operation runs in background so that
1180 PL310 can handle normal accesses while it is in progress. Under very
1181 rare circumstances, due to this erratum, write data can be lost when
1182 PL310 treats a cacheable write transaction during a Clean &
1183 Invalidate by Way operation.
1185 config ARM_ERRATA_743622
1186 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1189 This option enables the workaround for the 743622 Cortex-A9
1190 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1191 optimisation in the Cortex-A9 Store Buffer may lead to data
1192 corruption. This workaround sets a specific bit in the diagnostic
1193 register of the Cortex-A9 which disables the Store Buffer
1194 optimisation, preventing the defect from occurring. This has no
1195 visible impact on the overall performance or power consumption of the
1198 config ARM_ERRATA_751472
1199 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1200 depends on CPU_V7 && SMP
1202 This option enables the workaround for the 751472 Cortex-A9 (prior
1203 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1204 completion of a following broadcasted operation if the second
1205 operation is received by a CPU before the ICIALLUIS has completed,
1206 potentially leading to corrupted entries in the cache or TLB.
1208 config ARM_ERRATA_753970
1209 bool "ARM errata: cache sync operation may be faulty"
1210 depends on CACHE_PL310
1212 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1214 Under some condition the effect of cache sync operation on
1215 the store buffer still remains when the operation completes.
1216 This means that the store buffer is always asked to drain and
1217 this prevents it from merging any further writes. The workaround
1218 is to replace the normal offset of cache sync operation (0x730)
1219 by another offset targeting an unmapped PL310 register 0x740.
1220 This has the same effect as the cache sync operation: store buffer
1221 drain and waiting for all buffers empty.
1223 config ARM_ERRATA_754322
1224 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1227 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1228 r3p*) erratum. A speculative memory access may cause a page table walk
1229 which starts prior to an ASID switch but completes afterwards. This
1230 can populate the micro-TLB with a stale entry which may be hit with
1231 the new ASID. This workaround places two dsb instructions in the mm
1232 switching code so that no page table walks can cross the ASID switch.
1234 config ARM_ERRATA_754327
1235 bool "ARM errata: no automatic Store Buffer drain"
1236 depends on CPU_V7 && SMP
1238 This option enables the workaround for the 754327 Cortex-A9 (prior to
1239 r2p0) erratum. The Store Buffer does not have any automatic draining
1240 mechanism and therefore a livelock may occur if an external agent
1241 continuously polls a memory location waiting to observe an update.
1242 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1243 written polling loops from denying visibility of updates to memory.
1247 source "arch/arm/common/Kconfig"
1257 Find out whether you have ISA slots on your motherboard. ISA is the
1258 name of a bus system, i.e. the way the CPU talks to the other stuff
1259 inside your box. Other bus systems are PCI, EISA, MicroChannel
1260 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1261 newer boards don't support it. If you have ISA, say Y, otherwise N.
1263 # Select ISA DMA controller support
1268 # Select ISA DMA interface
1273 bool "PCI support" if MIGHT_HAVE_PCI
1275 Find out whether you have a PCI motherboard. PCI is the name of a
1276 bus system, i.e. the way the CPU talks to the other stuff inside
1277 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1278 VESA. If you have PCI, say Y, otherwise N.
1284 config PCI_NANOENGINE
1285 bool "BSE nanoEngine PCI support"
1286 depends on SA1100_NANOENGINE
1288 Enable PCI on the BSE nanoEngine board.
1293 # Select the host bridge type
1294 config PCI_HOST_VIA82C505
1296 depends on PCI && ARCH_SHARK
1299 config PCI_HOST_ITE8152
1301 depends on PCI && MACH_ARMCORE
1305 source "drivers/pci/Kconfig"
1307 source "drivers/pcmcia/Kconfig"
1311 menu "Kernel Features"
1313 source "kernel/time/Kconfig"
1316 bool "Symmetric Multi-Processing"
1317 depends on CPU_V6K || CPU_V7
1318 depends on GENERIC_CLOCKEVENTS
1319 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1320 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1321 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1322 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1323 select USE_GENERIC_SMP_HELPERS
1324 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1326 This enables support for systems with more than one CPU. If you have
1327 a system with only one CPU, like most personal computers, say N. If
1328 you have a system with more than one CPU, say Y.
1330 If you say N here, the kernel will run on single and multiprocessor
1331 machines, but will use only one CPU of a multiprocessor machine. If
1332 you say Y here, the kernel will run on many, but not all, single
1333 processor machines. On a single processor machine, the kernel will
1334 run faster if you say N here.
1336 See also <file:Documentation/i386/IO-APIC.txt>,
1337 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1338 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1340 If you don't know what to do here, say N.
1343 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1344 depends on EXPERIMENTAL
1345 depends on SMP && !XIP_KERNEL
1348 SMP kernels contain instructions which fail on non-SMP processors.
1349 Enabling this option allows the kernel to modify itself to make
1350 these instructions safe. Disabling it allows about 1K of space
1353 If you don't know what to do here, say Y.
1359 This option enables support for the ARM system coherency unit
1366 This options enables support for the ARM timer and watchdog unit
1369 prompt "Memory split"
1372 Select the desired split between kernel and user memory.
1374 If you are not absolutely sure what you are doing, leave this
1378 bool "3G/1G user/kernel split"
1380 bool "2G/2G user/kernel split"
1382 bool "1G/3G user/kernel split"
1387 default 0x40000000 if VMSPLIT_1G
1388 default 0x80000000 if VMSPLIT_2G
1392 int "Maximum number of CPUs (2-32)"
1398 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1399 depends on SMP && HOTPLUG && EXPERIMENTAL
1400 depends on !ARCH_MSM
1402 Say Y here to experiment with turning CPUs off and on. CPUs
1403 can be controlled through /sys/devices/system/cpu.
1406 bool "Use local timer interrupts"
1409 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1411 Enable support for local timers on SMP platforms, rather then the
1412 legacy IPI broadcast method. Local timers allows the system
1413 accounting to be spread across the timer interval, preventing a
1414 "thundering herd" at every timer tick.
1416 source kernel/Kconfig.preempt
1420 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1421 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
1422 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1423 default AT91_TIMER_HZ if ARCH_AT91
1424 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1427 config THUMB2_KERNEL
1428 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1429 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1431 select ARM_ASM_UNIFIED
1433 By enabling this option, the kernel will be compiled in
1434 Thumb-2 mode. A compiler/assembler that understand the unified
1435 ARM-Thumb syntax is needed.
1439 config THUMB2_AVOID_R_ARM_THM_JUMP11
1440 bool "Work around buggy Thumb-2 short branch relocations in gas"
1441 depends on THUMB2_KERNEL && MODULES
1444 Various binutils versions can resolve Thumb-2 branches to
1445 locally-defined, preemptible global symbols as short-range "b.n"
1446 branch instructions.
1448 This is a problem, because there's no guarantee the final
1449 destination of the symbol, or any candidate locations for a
1450 trampoline, are within range of the branch. For this reason, the
1451 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1452 relocation in modules at all, and it makes little sense to add
1455 The symptom is that the kernel fails with an "unsupported
1456 relocation" error when loading some modules.
1458 Until fixed tools are available, passing
1459 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1460 code which hits this problem, at the cost of a bit of extra runtime
1461 stack usage in some cases.
1463 The problem is described in more detail at:
1464 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1466 Only Thumb-2 kernels are affected.
1468 Unless you are sure your tools don't have this problem, say Y.
1470 config ARM_ASM_UNIFIED
1474 bool "Use the ARM EABI to compile the kernel"
1476 This option allows for the kernel to be compiled using the latest
1477 ARM ABI (aka EABI). This is only useful if you are using a user
1478 space environment that is also compiled with EABI.
1480 Since there are major incompatibilities between the legacy ABI and
1481 EABI, especially with regard to structure member alignment, this
1482 option also changes the kernel syscall calling convention to
1483 disambiguate both ABIs and allow for backward compatibility support
1484 (selected with CONFIG_OABI_COMPAT).
1486 To use this you need GCC version 4.0.0 or later.
1489 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1490 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1493 This option preserves the old syscall interface along with the
1494 new (ARM EABI) one. It also provides a compatibility layer to
1495 intercept syscalls that have structure arguments which layout
1496 in memory differs between the legacy ABI and the new ARM EABI
1497 (only for non "thumb" binaries). This option adds a tiny
1498 overhead to all syscalls and produces a slightly larger kernel.
1499 If you know you'll be using only pure EABI user space then you
1500 can say N here. If this option is not selected and you attempt
1501 to execute a legacy ABI binary then the result will be
1502 UNPREDICTABLE (in fact it can be predicted that it won't work
1503 at all). If in doubt say Y.
1505 config ARCH_HAS_HOLES_MEMORYMODEL
1508 config ARCH_SPARSEMEM_ENABLE
1511 config ARCH_SPARSEMEM_DEFAULT
1512 def_bool ARCH_SPARSEMEM_ENABLE
1514 config ARCH_SELECT_MEMORY_MODEL
1515 def_bool ARCH_SPARSEMEM_ENABLE
1518 bool "High Memory Support"
1521 The address space of ARM processors is only 4 Gigabytes large
1522 and it has to accommodate user address space, kernel address
1523 space as well as some memory mapped IO. That means that, if you
1524 have a large amount of physical memory and/or IO, not all of the
1525 memory can be "permanently mapped" by the kernel. The physical
1526 memory that is not permanently mapped is called "high memory".
1528 Depending on the selected kernel/user memory split, minimum
1529 vmalloc space and actual amount of RAM, you may not need this
1530 option which should result in a slightly faster kernel.
1535 bool "Allocate 2nd-level pagetables from highmem"
1538 config HW_PERF_EVENTS
1539 bool "Enable hardware performance counter support for perf events"
1540 depends on PERF_EVENTS && CPU_HAS_PMU
1543 Enable hardware performance counter support for perf events. If
1544 disabled, perf events will use software events only.
1548 config FORCE_MAX_ZONEORDER
1549 int "Maximum zone order" if ARCH_SHMOBILE
1550 range 11 64 if ARCH_SHMOBILE
1551 default "9" if SA1111
1554 The kernel memory allocator divides physically contiguous memory
1555 blocks into "zones", where each zone is a power of two number of
1556 pages. This option selects the largest power of two that the kernel
1557 keeps in the memory allocator. If you need to allocate very large
1558 blocks of physically contiguous memory, then you may need to
1559 increase this value.
1561 This config option is actually maximum order plus one. For example,
1562 a value of 11 means that the largest free memory block is 2^10 pages.
1565 bool "Timer and CPU usage LEDs"
1566 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1567 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1568 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1569 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1570 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1571 ARCH_AT91 || ARCH_DAVINCI || \
1572 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1574 If you say Y here, the LEDs on your machine will be used
1575 to provide useful information about your current system status.
1577 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1578 be able to select which LEDs are active using the options below. If
1579 you are compiling a kernel for the EBSA-110 or the LART however, the
1580 red LED will simply flash regularly to indicate that the system is
1581 still functional. It is safe to say Y here if you have a CATS
1582 system, but the driver will do nothing.
1585 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1586 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1587 || MACH_OMAP_PERSEUS2
1589 depends on !GENERIC_CLOCKEVENTS
1590 default y if ARCH_EBSA110
1592 If you say Y here, one of the system LEDs (the green one on the
1593 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1594 will flash regularly to indicate that the system is still
1595 operational. This is mainly useful to kernel hackers who are
1596 debugging unstable kernels.
1598 The LART uses the same LED for both Timer LED and CPU usage LED
1599 functions. You may choose to use both, but the Timer LED function
1600 will overrule the CPU usage LED.
1603 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1605 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1606 || MACH_OMAP_PERSEUS2
1609 If you say Y here, the red LED will be used to give a good real
1610 time indication of CPU usage, by lighting whenever the idle task
1611 is not currently executing.
1613 The LART uses the same LED for both Timer LED and CPU usage LED
1614 functions. You may choose to use both, but the Timer LED function
1615 will overrule the CPU usage LED.
1617 config ALIGNMENT_TRAP
1619 depends on CPU_CP15_MMU
1620 default y if !ARCH_EBSA110
1621 select HAVE_PROC_CPU if PROC_FS
1623 ARM processors cannot fetch/store information which is not
1624 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1625 address divisible by 4. On 32-bit ARM processors, these non-aligned
1626 fetch/store instructions will be emulated in software if you say
1627 here, which has a severe performance impact. This is necessary for
1628 correct operation of some network protocols. With an IP-only
1629 configuration it is safe to say N, otherwise say Y.
1631 config UACCESS_WITH_MEMCPY
1632 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1633 depends on MMU && EXPERIMENTAL
1634 default y if CPU_FEROCEON
1636 Implement faster copy_to_user and clear_user methods for CPU
1637 cores where a 8-word STM instruction give significantly higher
1638 memory write throughput than a sequence of individual 32bit stores.
1640 A possible side effect is a slight increase in scheduling latency
1641 between threads sharing the same address space if they invoke
1642 such copy operations with large buffers.
1644 However, if the CPU data cache is using a write-allocate mode,
1645 this option is unlikely to provide any performance gain.
1649 prompt "Enable seccomp to safely compute untrusted bytecode"
1651 This kernel feature is useful for number crunching applications
1652 that may need to compute untrusted bytecode during their
1653 execution. By using pipes or other transports made available to
1654 the process as file descriptors supporting the read/write
1655 syscalls, it's possible to isolate those applications in
1656 their own address space using seccomp. Once seccomp is
1657 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1658 and the task is only allowed to execute a few safe syscalls
1659 defined by each seccomp mode.
1661 config CC_STACKPROTECTOR
1662 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1663 depends on EXPERIMENTAL
1665 This option turns on the -fstack-protector GCC feature. This
1666 feature puts, at the beginning of functions, a canary value on
1667 the stack just before the return address, and validates
1668 the value just before actually returning. Stack based buffer
1669 overflows (that need to overwrite this return address) now also
1670 overwrite the canary, which gets detected and the attack is then
1671 neutralized via a kernel panic.
1672 This feature requires gcc version 4.2 or above.
1674 config DEPRECATED_PARAM_STRUCT
1675 bool "Provide old way to pass kernel parameters"
1677 This was deprecated in 2001 and announced to live on for 5 years.
1678 Some old boot loaders still use this way.
1684 # Compressed boot loader in ROM. Yes, we really want to ask about
1685 # TEXT and BSS so we preserve their values in the config files.
1686 config ZBOOT_ROM_TEXT
1687 hex "Compressed ROM boot loader base address"
1690 The physical address at which the ROM-able zImage is to be
1691 placed in the target. Platforms which normally make use of
1692 ROM-able zImage formats normally set this to a suitable
1693 value in their defconfig file.
1695 If ZBOOT_ROM is not enabled, this has no effect.
1697 config ZBOOT_ROM_BSS
1698 hex "Compressed ROM boot loader BSS address"
1701 The base address of an area of read/write memory in the target
1702 for the ROM-able zImage which must be available while the
1703 decompressor is running. It must be large enough to hold the
1704 entire decompressed kernel plus an additional 128 KiB.
1705 Platforms which normally make use of ROM-able zImage formats
1706 normally set this to a suitable value in their defconfig file.
1708 If ZBOOT_ROM is not enabled, this has no effect.
1711 bool "Compressed boot loader in ROM/flash"
1712 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1714 Say Y here if you intend to execute your compressed kernel image
1715 (zImage) directly from ROM or flash. If unsure, say N.
1717 config ZBOOT_ROM_MMCIF
1718 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1719 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1721 Say Y here to include experimental MMCIF loading code in the
1722 ROM-able zImage. With this enabled it is possible to write the
1723 the ROM-able zImage kernel image to an MMC card and boot the
1724 kernel straight from the reset vector. At reset the processor
1725 Mask ROM will load the first part of the the ROM-able zImage
1726 which in turn loads the rest the kernel image to RAM using the
1727 MMCIF hardware block.
1730 string "Default kernel command string"
1733 On some architectures (EBSA110 and CATS), there is currently no way
1734 for the boot loader to pass arguments to the kernel. For these
1735 architectures, you should supply some command-line options at build
1736 time by entering them here. As a minimum, you should specify the
1737 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1740 prompt "Kernel command line type" if CMDLINE != ""
1741 default CMDLINE_FROM_BOOTLOADER
1743 config CMDLINE_FROM_BOOTLOADER
1744 bool "Use bootloader kernel arguments if available"
1746 Uses the command-line options passed by the boot loader. If
1747 the boot loader doesn't provide any, the default kernel command
1748 string provided in CMDLINE will be used.
1750 config CMDLINE_EXTEND
1751 bool "Extend bootloader kernel arguments"
1753 The command-line arguments provided by the boot loader will be
1754 appended to the default kernel command string.
1756 config CMDLINE_FORCE
1757 bool "Always use the default kernel command string"
1759 Always use the default kernel command string, even if the boot
1760 loader passes other arguments to the kernel.
1761 This is useful if you cannot or don't want to change the
1762 command-line options your boot loader passes to the kernel.
1766 bool "Kernel Execute-In-Place from ROM"
1767 depends on !ZBOOT_ROM
1769 Execute-In-Place allows the kernel to run from non-volatile storage
1770 directly addressable by the CPU, such as NOR flash. This saves RAM
1771 space since the text section of the kernel is not loaded from flash
1772 to RAM. Read-write sections, such as the data section and stack,
1773 are still copied to RAM. The XIP kernel is not compressed since
1774 it has to run directly from flash, so it will take more space to
1775 store it. The flash address used to link the kernel object files,
1776 and for storing it, is configuration dependent. Therefore, if you
1777 say Y here, you must know the proper physical address where to
1778 store the kernel image depending on your own flash memory usage.
1780 Also note that the make target becomes "make xipImage" rather than
1781 "make zImage" or "make Image". The final kernel binary to put in
1782 ROM memory will be arch/arm/boot/xipImage.
1786 config XIP_PHYS_ADDR
1787 hex "XIP Kernel Physical Location"
1788 depends on XIP_KERNEL
1789 default "0x00080000"
1791 This is the physical address in your flash memory the kernel will
1792 be linked for and stored to. This address is dependent on your
1796 bool "Kexec system call (EXPERIMENTAL)"
1797 depends on EXPERIMENTAL
1799 kexec is a system call that implements the ability to shutdown your
1800 current kernel, and to start another kernel. It is like a reboot
1801 but it is independent of the system firmware. And like a reboot
1802 you can start any kernel with it, not just Linux.
1804 It is an ongoing process to be certain the hardware in a machine
1805 is properly shutdown, so do not be surprised if this code does not
1806 initially work for you. It may help to enable device hotplugging
1810 bool "Export atags in procfs"
1814 Should the atags used to boot the kernel be exported in an "atags"
1815 file in procfs. Useful with kexec.
1818 bool "Build kdump crash kernel (EXPERIMENTAL)"
1819 depends on EXPERIMENTAL
1821 Generate crash dump after being started by kexec. This should
1822 be normally only set in special crash dump kernels which are
1823 loaded in the main kernel with kexec-tools into a specially
1824 reserved region and then later executed after a crash by
1825 kdump/kexec. The crash dump kernel must be compiled to a
1826 memory address not used by the main kernel
1828 For more details see Documentation/kdump/kdump.txt
1830 config AUTO_ZRELADDR
1831 bool "Auto calculation of the decompressed kernel image address"
1832 depends on !ZBOOT_ROM && !ARCH_U300
1834 ZRELADDR is the physical address where the decompressed kernel
1835 image will be placed. If AUTO_ZRELADDR is selected, the address
1836 will be determined at run-time by masking the current IP with
1837 0xf8000000. This assumes the zImage being placed in the first 128MB
1838 from start of memory.
1842 menu "CPU Power Management"
1846 source "drivers/cpufreq/Kconfig"
1849 tristate "CPUfreq driver for i.MX CPUs"
1850 depends on ARCH_MXC && CPU_FREQ
1852 This enables the CPUfreq driver for i.MX CPUs.
1854 config CPU_FREQ_SA1100
1857 config CPU_FREQ_SA1110
1860 config CPU_FREQ_INTEGRATOR
1861 tristate "CPUfreq driver for ARM Integrator CPUs"
1862 depends on ARCH_INTEGRATOR && CPU_FREQ
1865 This enables the CPUfreq driver for ARM Integrator CPUs.
1867 For details, take a look at <file:Documentation/cpu-freq>.
1873 depends on CPU_FREQ && ARCH_PXA && PXA25x
1875 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1877 config CPU_FREQ_S3C64XX
1878 bool "CPUfreq support for Samsung S3C64XX CPUs"
1879 depends on CPU_FREQ && CPU_S3C6410
1884 Internal configuration node for common cpufreq on Samsung SoC
1886 config CPU_FREQ_S3C24XX
1887 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1888 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1891 This enables the CPUfreq driver for the Samsung S3C24XX family
1894 For details, take a look at <file:Documentation/cpu-freq>.
1898 config CPU_FREQ_S3C24XX_PLL
1899 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1900 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1902 Compile in support for changing the PLL frequency from the
1903 S3C24XX series CPUfreq driver. The PLL takes time to settle
1904 after a frequency change, so by default it is not enabled.
1906 This also means that the PLL tables for the selected CPU(s) will
1907 be built which may increase the size of the kernel image.
1909 config CPU_FREQ_S3C24XX_DEBUG
1910 bool "Debug CPUfreq Samsung driver core"
1911 depends on CPU_FREQ_S3C24XX
1913 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1915 config CPU_FREQ_S3C24XX_IODEBUG
1916 bool "Debug CPUfreq Samsung driver IO timing"
1917 depends on CPU_FREQ_S3C24XX
1919 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1921 config CPU_FREQ_S3C24XX_DEBUGFS
1922 bool "Export debugfs for CPUFreq"
1923 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1925 Export status information via debugfs.
1929 source "drivers/cpuidle/Kconfig"
1933 menu "Floating point emulation"
1935 comment "At least one emulation must be selected"
1938 bool "NWFPE math emulation"
1939 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1941 Say Y to include the NWFPE floating point emulator in the kernel.
1942 This is necessary to run most binaries. Linux does not currently
1943 support floating point hardware so you need to say Y here even if
1944 your machine has an FPA or floating point co-processor podule.
1946 You may say N here if you are going to load the Acorn FPEmulator
1947 early in the bootup.
1950 bool "Support extended precision"
1951 depends on FPE_NWFPE
1953 Say Y to include 80-bit support in the kernel floating-point
1954 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1955 Note that gcc does not generate 80-bit operations by default,
1956 so in most cases this option only enlarges the size of the
1957 floating point emulator without any good reason.
1959 You almost surely want to say N here.
1962 bool "FastFPE math emulation (EXPERIMENTAL)"
1963 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1965 Say Y here to include the FAST floating point emulator in the kernel.
1966 This is an experimental much faster emulator which now also has full
1967 precision for the mantissa. It does not support any exceptions.
1968 It is very simple, and approximately 3-6 times faster than NWFPE.
1970 It should be sufficient for most programs. It may be not suitable
1971 for scientific calculations, but you have to check this for yourself.
1972 If you do not feel you need a faster FP emulation you should better
1976 bool "VFP-format floating point maths"
1977 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1979 Say Y to include VFP support code in the kernel. This is needed
1980 if your hardware includes a VFP unit.
1982 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1983 release notes and additional status information.
1985 Say N if your target does not have VFP hardware.
1993 bool "Advanced SIMD (NEON) Extension support"
1994 depends on VFPv3 && CPU_V7
1996 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2001 menu "Userspace binary formats"
2003 source "fs/Kconfig.binfmt"
2006 tristate "RISC OS personality"
2009 Say Y here to include the kernel code necessary if you want to run
2010 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2011 experimental; if this sounds frightening, say N and sleep in peace.
2012 You can also say M here to compile this support as a module (which
2013 will be called arthur).
2017 menu "Power management options"
2019 source "kernel/power/Kconfig"
2021 config ARCH_SUSPEND_POSSIBLE
2022 depends on !ARCH_S5P64X0 && !ARCH_S5P6442 && !ARCH_S5PC100
2023 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2024 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2029 source "net/Kconfig"
2031 source "drivers/Kconfig"
2035 source "arch/arm/Kconfig.debug"
2037 source "security/Kconfig"
2039 source "crypto/Kconfig"
2041 source "lib/Kconfig"