4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_ELF_RANDOMIZE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
19 select EDAC_ATOMIC_SCRUB
20 select GENERIC_ALLOCATOR
21 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
22 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
23 select GENERIC_IDLE_POLL_SETUP
24 select GENERIC_IRQ_PROBE
25 select GENERIC_IRQ_SHOW
26 select GENERIC_IRQ_SHOW_LEVEL
27 select GENERIC_PCI_IOMAP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
30 select GENERIC_STRNCPY_FROM_USER
31 select GENERIC_STRNLEN_USER
32 select HANDLE_DOMAIN_IRQ
33 select HARDIRQS_SW_RESEND
34 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
35 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
36 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32
37 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32
38 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
39 select HAVE_ARCH_TRACEHOOK
41 select HAVE_CC_STACKPROTECTOR
42 select HAVE_CONTEXT_TRACKING
43 select HAVE_C_RECORDMCOUNT
44 select HAVE_DEBUG_KMEMLEAK
45 select HAVE_DMA_API_DEBUG
47 select HAVE_DMA_CONTIGUOUS if MMU
48 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32
49 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
50 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
51 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
52 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
53 select HAVE_GENERIC_DMA_COHERENT
54 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
55 select HAVE_IDE if PCI || ISA || PCMCIA
56 select HAVE_IRQ_TIME_ACCOUNTING
57 select HAVE_KERNEL_GZIP
58 select HAVE_KERNEL_LZ4
59 select HAVE_KERNEL_LZMA
60 select HAVE_KERNEL_LZO
62 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
63 select HAVE_KRETPROBES if (HAVE_KPROBES)
65 select HAVE_MOD_ARCH_SPECIFIC
66 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
67 select HAVE_OPTPROBES if !THUMB2_KERNEL
68 select HAVE_PERF_EVENTS
70 select HAVE_PERF_USER_STACK_DUMP
71 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
72 select HAVE_REGS_AND_STACK_ACCESS_API
73 select HAVE_SYSCALL_TRACEPOINTS
75 select HAVE_VIRT_CPU_ACCOUNTING_GEN
76 select IRQ_FORCED_THREADING
77 select MODULES_USE_ELF_REL
80 select OLD_SIGSUSPEND3
81 select PERF_USE_VMALLOC
83 select SYS_SUPPORTS_APM_EMULATION
84 # Above selects are sorted alphabetically; please add new ones
85 # according to that. Thanks.
87 The ARM series is a line of low-power-consumption RISC chip designs
88 licensed by ARM Ltd and targeted at embedded applications and
89 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
90 manufactured, but legacy ARM-based PC hardware remains popular in
91 Europe. There is an ARM Linux project with a web page at
92 <http://www.arm.linux.org.uk/>.
94 config ARM_HAS_SG_CHAIN
95 select ARCH_HAS_SG_CHAIN
98 config NEED_SG_DMA_LENGTH
101 config ARM_DMA_USE_IOMMU
103 select ARM_HAS_SG_CHAIN
104 select NEED_SG_DMA_LENGTH
108 config ARM_DMA_IOMMU_ALIGNMENT
109 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
113 DMA mapping framework by default aligns all buffers to the smallest
114 PAGE_SIZE order which is greater than or equal to the requested buffer
115 size. This works well for buffers up to a few hundreds kilobytes, but
116 for larger buffers it just a waste of address space. Drivers which has
117 relatively small addressing window (like 64Mib) might run out of
118 virtual space with just a few allocations.
120 With this parameter you can specify the maximum PAGE_SIZE order for
121 DMA IOMMU buffers. Larger buffers will be aligned only to this
122 specified order. The order is expressed as a power of two multiplied
127 config MIGHT_HAVE_PCI
130 config SYS_SUPPORTS_APM_EMULATION
135 select GENERIC_ALLOCATOR
146 The Extended Industry Standard Architecture (EISA) bus was
147 developed as an open alternative to the IBM MicroChannel bus.
149 The EISA bus provided some of the features of the IBM MicroChannel
150 bus while maintaining backward compatibility with cards made for
151 the older ISA bus. The EISA bus saw limited use between 1988 and
152 1995 when it was made obsolete by the PCI bus.
154 Say Y here if you are building a kernel for an EISA-based machine.
161 config STACKTRACE_SUPPORT
165 config HAVE_LATENCYTOP_SUPPORT
170 config LOCKDEP_SUPPORT
174 config TRACE_IRQFLAGS_SUPPORT
178 config RWSEM_XCHGADD_ALGORITHM
182 config ARCH_HAS_ILOG2_U32
185 config ARCH_HAS_ILOG2_U64
188 config ARCH_HAS_BANDGAP
191 config FIX_EARLYCON_MEM
194 config GENERIC_HWEIGHT
198 config GENERIC_CALIBRATE_DELAY
202 config ARCH_MAY_HAVE_PC_FDC
208 config NEED_DMA_MAP_STATE
211 config ARCH_SUPPORTS_UPROBES
214 config ARCH_HAS_DMA_SET_COHERENT_MASK
217 config GENERIC_ISA_DMA
223 config NEED_RET_TO_USER
231 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
232 default DRAM_BASE if REMAP_VECTORS_TO_RAM
235 The base address of exception vectors. This must be two pages
238 config ARM_PATCH_PHYS_VIRT
239 bool "Patch physical to virtual translations at runtime" if EMBEDDED
241 depends on !XIP_KERNEL && MMU
243 Patch phys-to-virt and virt-to-phys translation functions at
244 boot and module load time according to the position of the
245 kernel in system memory.
247 This can only be used with non-XIP MMU kernels where the base
248 of physical memory is at a 16MB boundary.
250 Only disable this option if you know that you do not require
251 this feature (eg, building a kernel for a single machine) and
252 you need to shrink the kernel to the minimal size.
254 config NEED_MACH_IO_H
257 Select this when mach/io.h is required to provide special
258 definitions for this platform. The need for mach/io.h should
259 be avoided when possible.
261 config NEED_MACH_MEMORY_H
264 Select this when mach/memory.h is required to provide special
265 definitions for this platform. The need for mach/memory.h should
266 be avoided when possible.
269 hex "Physical address of main memory" if MMU
270 depends on !ARM_PATCH_PHYS_VIRT
271 default DRAM_BASE if !MMU
272 default 0x00000000 if ARCH_EBSA110 || \
277 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
278 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
279 default 0x20000000 if ARCH_S5PV210
280 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
281 default 0xc0000000 if ARCH_SA1100
283 Please provide the physical address corresponding to the
284 location of main memory in your system.
290 config PGTABLE_LEVELS
292 default 3 if ARM_LPAE
295 source "init/Kconfig"
297 source "kernel/Kconfig.freezer"
302 bool "MMU-based Paged Memory Management Support"
305 Select if you want MMU-based virtualised addressing space
306 support by paged memory management. If unsure, say 'Y'.
309 # The "ARM system type" choice list is ordered alphabetically by option
310 # text. Please add new entries in the option alphabetic order.
313 prompt "ARM system type"
314 default ARCH_VERSATILE if !MMU
315 default ARCH_MULTIPLATFORM if MMU
317 config ARCH_MULTIPLATFORM
318 bool "Allow multiple platforms to be selected"
320 select ARCH_WANT_OPTIONAL_GPIOLIB
321 select ARM_HAS_SG_CHAIN
322 select ARM_PATCH_PHYS_VIRT
326 select GENERIC_CLOCKEVENTS
327 select MIGHT_HAVE_PCI
328 select MULTI_IRQ_HANDLER
332 config ARM_SINGLE_ARMV7M
333 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
341 select GENERIC_CLOCKEVENTS
347 config ARCH_VERSATILE
348 bool "ARM Ltd. Versatile family"
349 select ARCH_WANT_OPTIONAL_GPIOLIB
351 select ARM_TIMER_SP804
354 select GENERIC_CLOCKEVENTS
355 select HAVE_MACH_CLKDEV
357 select PLAT_VERSATILE
358 select PLAT_VERSATILE_CLOCK
359 select PLAT_VERSATILE_SCHED_CLOCK
360 select VERSATILE_FPGA_IRQ
362 This enables support for ARM Ltd Versatile board.
365 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
366 select ARCH_REQUIRE_GPIOLIB
371 select GENERIC_CLOCKEVENTS
375 Support for Cirrus Logic 711x/721x/731x based boards.
378 bool "Cortina Systems Gemini"
379 select ARCH_REQUIRE_GPIOLIB
382 select GENERIC_CLOCKEVENTS
384 Support for the Cortina Systems Gemini family SoCs
388 select ARCH_USES_GETTIMEOFFSET
391 select NEED_MACH_IO_H
392 select NEED_MACH_MEMORY_H
395 This is an evaluation board for the StrongARM processor available
396 from Digital. It has limited hardware on-board, including an
397 Ethernet interface, two PCMCIA sockets, two serial ports and a
402 select ARCH_HAS_HOLES_MEMORYMODEL
403 select ARCH_REQUIRE_GPIOLIB
405 select ARM_PATCH_PHYS_VIRT
411 select GENERIC_CLOCKEVENTS
413 This enables support for the Cirrus EP93xx series of CPUs.
415 config ARCH_FOOTBRIDGE
419 select GENERIC_CLOCKEVENTS
421 select NEED_MACH_IO_H if !MMU
422 select NEED_MACH_MEMORY_H
424 Support for systems based on the DC21285 companion chip
425 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
428 bool "Hilscher NetX based"
432 select GENERIC_CLOCKEVENTS
434 This enables support for systems based on the Hilscher NetX Soc
440 select NEED_MACH_MEMORY_H
441 select NEED_RET_TO_USER
447 Support for Intel's IOP13XX (XScale) family of processors.
452 select ARCH_REQUIRE_GPIOLIB
455 select NEED_RET_TO_USER
459 Support for Intel's 80219 and IOP32X (XScale) family of
465 select ARCH_REQUIRE_GPIOLIB
468 select NEED_RET_TO_USER
472 Support for Intel's IOP33X (XScale) family of processors.
477 select ARCH_HAS_DMA_SET_COHERENT_MASK
478 select ARCH_REQUIRE_GPIOLIB
479 select ARCH_SUPPORTS_BIG_ENDIAN
482 select DMABOUNCE if PCI
483 select GENERIC_CLOCKEVENTS
484 select MIGHT_HAVE_PCI
485 select NEED_MACH_IO_H
486 select USB_EHCI_BIG_ENDIAN_DESC
487 select USB_EHCI_BIG_ENDIAN_MMIO
489 Support for Intel's IXP4XX (XScale) family of processors.
493 select ARCH_REQUIRE_GPIOLIB
495 select GENERIC_CLOCKEVENTS
496 select MIGHT_HAVE_PCI
500 select PLAT_ORION_LEGACY
502 Support for the Marvell Dove SoC 88AP510
505 bool "Marvell MV78xx0"
506 select ARCH_REQUIRE_GPIOLIB
508 select GENERIC_CLOCKEVENTS
511 select PLAT_ORION_LEGACY
513 Support for the following Marvell MV78xx0 series SoCs:
519 select ARCH_REQUIRE_GPIOLIB
521 select GENERIC_CLOCKEVENTS
524 select PLAT_ORION_LEGACY
525 select MULTI_IRQ_HANDLER
527 Support for the following Marvell Orion 5x series SoCs:
528 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
529 Orion-2 (5281), Orion-1-90 (6183).
532 bool "Marvell PXA168/910/MMP2"
534 select ARCH_REQUIRE_GPIOLIB
536 select GENERIC_ALLOCATOR
537 select GENERIC_CLOCKEVENTS
540 select MULTI_IRQ_HANDLER
545 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
548 bool "Micrel/Kendin KS8695"
549 select ARCH_REQUIRE_GPIOLIB
552 select GENERIC_CLOCKEVENTS
553 select NEED_MACH_MEMORY_H
555 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
556 System-on-Chip devices.
559 bool "Nuvoton W90X900 CPU"
560 select ARCH_REQUIRE_GPIOLIB
564 select GENERIC_CLOCKEVENTS
566 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
567 At present, the w90x900 has been renamed nuc900, regarding
568 the ARM series product line, you can login the following
569 link address to know more.
571 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
572 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
576 select ARCH_REQUIRE_GPIOLIB
581 select GENERIC_CLOCKEVENTS
585 Support for the NXP LPC32XX family of processors
588 bool "PXA2xx/PXA3xx-based"
591 select ARCH_REQUIRE_GPIOLIB
592 select ARM_CPU_SUSPEND if PM
598 select GENERIC_CLOCKEVENTS
602 select MULTI_IRQ_HANDLER
606 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
612 select ARCH_MAY_HAVE_PC_FDC
613 select ARCH_SPARSEMEM_ENABLE
614 select ARCH_USES_GETTIMEOFFSET
618 select HAVE_PATA_PLATFORM
620 select NEED_MACH_IO_H
621 select NEED_MACH_MEMORY_H
625 On the Acorn Risc-PC, Linux can support the internal IDE disk and
626 CD-ROM interface, serial and parallel port, and the floppy drive.
631 select ARCH_REQUIRE_GPIOLIB
632 select ARCH_SPARSEMEM_ENABLE
637 select GENERIC_CLOCKEVENTS
641 select MULTI_IRQ_HANDLER
642 select NEED_MACH_MEMORY_H
645 Support for StrongARM 11x0 based boards.
648 bool "Samsung S3C24XX SoCs"
649 select ARCH_REQUIRE_GPIOLIB
652 select CLKSRC_SAMSUNG_PWM
653 select GENERIC_CLOCKEVENTS
655 select HAVE_S3C2410_I2C if I2C
656 select HAVE_S3C2410_WATCHDOG if WATCHDOG
657 select HAVE_S3C_RTC if RTC_CLASS
658 select MULTI_IRQ_HANDLER
659 select NEED_MACH_IO_H
662 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
663 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
664 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
665 Samsung SMDK2410 development board (and derivatives).
668 bool "Samsung S3C64XX"
669 select ARCH_REQUIRE_GPIOLIB
674 select CLKSRC_SAMSUNG_PWM
675 select COMMON_CLK_SAMSUNG
677 select GENERIC_CLOCKEVENTS
679 select HAVE_S3C2410_I2C if I2C
680 select HAVE_S3C2410_WATCHDOG if WATCHDOG
684 select PM_GENERIC_DOMAINS if PM
686 select S3C_GPIO_TRACK
688 select SAMSUNG_WAKEMASK
689 select SAMSUNG_WDT_RESET
691 Samsung S3C64XX series based systems
695 select ARCH_HAS_HOLES_MEMORYMODEL
696 select ARCH_REQUIRE_GPIOLIB
698 select GENERIC_ALLOCATOR
699 select GENERIC_CLOCKEVENTS
700 select GENERIC_IRQ_CHIP
705 Support for TI's DaVinci platform.
710 select ARCH_HAS_HOLES_MEMORYMODEL
712 select ARCH_REQUIRE_GPIOLIB
715 select GENERIC_CLOCKEVENTS
716 select GENERIC_IRQ_CHIP
719 select MULTI_IRQ_HANDLER
720 select NEED_MACH_IO_H if PCCARD
721 select NEED_MACH_MEMORY_H
724 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
728 menu "Multiple platform selection"
729 depends on ARCH_MULTIPLATFORM
731 comment "CPU Core family selection"
734 bool "ARMv4 based platforms (FA526)"
735 depends on !ARCH_MULTI_V6_V7
736 select ARCH_MULTI_V4_V5
739 config ARCH_MULTI_V4T
740 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
741 depends on !ARCH_MULTI_V6_V7
742 select ARCH_MULTI_V4_V5
743 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
744 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
745 CPU_ARM925T || CPU_ARM940T)
748 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
749 depends on !ARCH_MULTI_V6_V7
750 select ARCH_MULTI_V4_V5
751 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
752 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
753 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
755 config ARCH_MULTI_V4_V5
759 bool "ARMv6 based platforms (ARM11)"
760 select ARCH_MULTI_V6_V7
764 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
766 select ARCH_MULTI_V6_V7
770 config ARCH_MULTI_V6_V7
772 select MIGHT_HAVE_CACHE_L2X0
774 config ARCH_MULTI_CPU_AUTO
775 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
781 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
786 select HAVE_ARM_ARCH_TIMER
789 # This is sorted alphabetically by mach-* pathname. However, plat-*
790 # Kconfigs may be included either alphabetically (according to the
791 # plat- suffix) or along side the corresponding mach-* source.
793 source "arch/arm/mach-mvebu/Kconfig"
795 source "arch/arm/mach-alpine/Kconfig"
797 source "arch/arm/mach-asm9260/Kconfig"
799 source "arch/arm/mach-at91/Kconfig"
801 source "arch/arm/mach-axxia/Kconfig"
803 source "arch/arm/mach-bcm/Kconfig"
805 source "arch/arm/mach-berlin/Kconfig"
807 source "arch/arm/mach-clps711x/Kconfig"
809 source "arch/arm/mach-cns3xxx/Kconfig"
811 source "arch/arm/mach-davinci/Kconfig"
813 source "arch/arm/mach-digicolor/Kconfig"
815 source "arch/arm/mach-dove/Kconfig"
817 source "arch/arm/mach-ep93xx/Kconfig"
819 source "arch/arm/mach-footbridge/Kconfig"
821 source "arch/arm/mach-gemini/Kconfig"
823 source "arch/arm/mach-highbank/Kconfig"
825 source "arch/arm/mach-hisi/Kconfig"
827 source "arch/arm/mach-integrator/Kconfig"
829 source "arch/arm/mach-iop32x/Kconfig"
831 source "arch/arm/mach-iop33x/Kconfig"
833 source "arch/arm/mach-iop13xx/Kconfig"
835 source "arch/arm/mach-ixp4xx/Kconfig"
837 source "arch/arm/mach-keystone/Kconfig"
839 source "arch/arm/mach-ks8695/Kconfig"
841 source "arch/arm/mach-meson/Kconfig"
843 source "arch/arm/mach-moxart/Kconfig"
845 source "arch/arm/mach-mv78xx0/Kconfig"
847 source "arch/arm/mach-imx/Kconfig"
849 source "arch/arm/mach-mediatek/Kconfig"
851 source "arch/arm/mach-mxs/Kconfig"
853 source "arch/arm/mach-netx/Kconfig"
855 source "arch/arm/mach-nomadik/Kconfig"
857 source "arch/arm/mach-nspire/Kconfig"
859 source "arch/arm/plat-omap/Kconfig"
861 source "arch/arm/mach-omap1/Kconfig"
863 source "arch/arm/mach-omap2/Kconfig"
865 source "arch/arm/mach-orion5x/Kconfig"
867 source "arch/arm/mach-picoxcell/Kconfig"
869 source "arch/arm/mach-pxa/Kconfig"
870 source "arch/arm/plat-pxa/Kconfig"
872 source "arch/arm/mach-mmp/Kconfig"
874 source "arch/arm/mach-qcom/Kconfig"
876 source "arch/arm/mach-realview/Kconfig"
878 source "arch/arm/mach-rockchip/Kconfig"
880 source "arch/arm/mach-sa1100/Kconfig"
882 source "arch/arm/mach-socfpga/Kconfig"
884 source "arch/arm/mach-spear/Kconfig"
886 source "arch/arm/mach-sti/Kconfig"
888 source "arch/arm/mach-s3c24xx/Kconfig"
890 source "arch/arm/mach-s3c64xx/Kconfig"
892 source "arch/arm/mach-s5pv210/Kconfig"
894 source "arch/arm/mach-exynos/Kconfig"
895 source "arch/arm/plat-samsung/Kconfig"
897 source "arch/arm/mach-shmobile/Kconfig"
899 source "arch/arm/mach-sunxi/Kconfig"
901 source "arch/arm/mach-prima2/Kconfig"
903 source "arch/arm/mach-tegra/Kconfig"
905 source "arch/arm/mach-u300/Kconfig"
907 source "arch/arm/mach-uniphier/Kconfig"
909 source "arch/arm/mach-ux500/Kconfig"
911 source "arch/arm/mach-versatile/Kconfig"
913 source "arch/arm/mach-vexpress/Kconfig"
914 source "arch/arm/plat-versatile/Kconfig"
916 source "arch/arm/mach-vt8500/Kconfig"
918 source "arch/arm/mach-w90x900/Kconfig"
920 source "arch/arm/mach-zx/Kconfig"
922 source "arch/arm/mach-zynq/Kconfig"
924 # ARMv7-M architecture
926 bool "Energy Micro efm32"
927 depends on ARM_SINGLE_ARMV7M
928 select ARCH_REQUIRE_GPIOLIB
930 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
934 bool "NXP LPC18xx/LPC43xx"
935 depends on ARM_SINGLE_ARMV7M
936 select ARCH_HAS_RESET_CONTROLLER
938 select CLKSRC_LPC32XX
941 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
942 high performance microcontrollers.
945 bool "STMicrolectronics STM32"
946 depends on ARM_SINGLE_ARMV7M
947 select ARCH_HAS_RESET_CONTROLLER
948 select ARMV7M_SYSTICK
950 select RESET_CONTROLLER
952 Support for STMicroelectronics STM32 processors.
954 # Definitions to make life easier
960 select GENERIC_CLOCKEVENTS
966 select GENERIC_IRQ_CHIP
969 config PLAT_ORION_LEGACY
976 config PLAT_VERSATILE
979 source "arch/arm/firmware/Kconfig"
981 source arch/arm/mm/Kconfig
984 bool "Enable iWMMXt support"
985 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
986 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
988 Enable support for iWMMXt context switching at run time if
989 running on a CPU that supports it.
991 config MULTI_IRQ_HANDLER
994 Allow each machine to specify it's own IRQ handler at run time.
997 source "arch/arm/Kconfig-nommu"
1000 config PJ4B_ERRATA_4742
1001 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1002 depends on CPU_PJ4B && MACH_ARMADA_370
1005 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1006 Event (WFE) IDLE states, a specific timing sensitivity exists between
1007 the retiring WFI/WFE instructions and the newly issued subsequent
1008 instructions. This sensitivity can result in a CPU hang scenario.
1010 The software must insert either a Data Synchronization Barrier (DSB)
1011 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1014 config ARM_ERRATA_326103
1015 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1018 Executing a SWP instruction to read-only memory does not set bit 11
1019 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1020 treat the access as a read, preventing a COW from occurring and
1021 causing the faulting task to livelock.
1023 config ARM_ERRATA_411920
1024 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1025 depends on CPU_V6 || CPU_V6K
1027 Invalidation of the Instruction Cache operation can
1028 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1029 It does not affect the MPCore. This option enables the ARM Ltd.
1030 recommended workaround.
1032 config ARM_ERRATA_430973
1033 bool "ARM errata: Stale prediction on replaced interworking branch"
1036 This option enables the workaround for the 430973 Cortex-A8
1037 r1p* erratum. If a code sequence containing an ARM/Thumb
1038 interworking branch is replaced with another code sequence at the
1039 same virtual address, whether due to self-modifying code or virtual
1040 to physical address re-mapping, Cortex-A8 does not recover from the
1041 stale interworking branch prediction. This results in Cortex-A8
1042 executing the new code sequence in the incorrect ARM or Thumb state.
1043 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1044 and also flushes the branch target cache at every context switch.
1045 Note that setting specific bits in the ACTLR register may not be
1046 available in non-secure mode.
1048 config ARM_ERRATA_458693
1049 bool "ARM errata: Processor deadlock when a false hazard is created"
1051 depends on !ARCH_MULTIPLATFORM
1053 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1054 erratum. For very specific sequences of memory operations, it is
1055 possible for a hazard condition intended for a cache line to instead
1056 be incorrectly associated with a different cache line. This false
1057 hazard might then cause a processor deadlock. The workaround enables
1058 the L1 caching of the NEON accesses and disables the PLD instruction
1059 in the ACTLR register. Note that setting specific bits in the ACTLR
1060 register may not be available in non-secure mode.
1062 config ARM_ERRATA_460075
1063 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1065 depends on !ARCH_MULTIPLATFORM
1067 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1068 erratum. Any asynchronous access to the L2 cache may encounter a
1069 situation in which recent store transactions to the L2 cache are lost
1070 and overwritten with stale memory contents from external memory. The
1071 workaround disables the write-allocate mode for the L2 cache via the
1072 ACTLR register. Note that setting specific bits in the ACTLR register
1073 may not be available in non-secure mode.
1075 config ARM_ERRATA_742230
1076 bool "ARM errata: DMB operation may be faulty"
1077 depends on CPU_V7 && SMP
1078 depends on !ARCH_MULTIPLATFORM
1080 This option enables the workaround for the 742230 Cortex-A9
1081 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1082 between two write operations may not ensure the correct visibility
1083 ordering of the two writes. This workaround sets a specific bit in
1084 the diagnostic register of the Cortex-A9 which causes the DMB
1085 instruction to behave as a DSB, ensuring the correct behaviour of
1088 config ARM_ERRATA_742231
1089 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1090 depends on CPU_V7 && SMP
1091 depends on !ARCH_MULTIPLATFORM
1093 This option enables the workaround for the 742231 Cortex-A9
1094 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1095 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1096 accessing some data located in the same cache line, may get corrupted
1097 data due to bad handling of the address hazard when the line gets
1098 replaced from one of the CPUs at the same time as another CPU is
1099 accessing it. This workaround sets specific bits in the diagnostic
1100 register of the Cortex-A9 which reduces the linefill issuing
1101 capabilities of the processor.
1103 config ARM_ERRATA_643719
1104 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1105 depends on CPU_V7 && SMP
1108 This option enables the workaround for the 643719 Cortex-A9 (prior to
1109 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1110 register returns zero when it should return one. The workaround
1111 corrects this value, ensuring cache maintenance operations which use
1112 it behave as intended and avoiding data corruption.
1114 config ARM_ERRATA_720789
1115 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1118 This option enables the workaround for the 720789 Cortex-A9 (prior to
1119 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1120 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1121 As a consequence of this erratum, some TLB entries which should be
1122 invalidated are not, resulting in an incoherency in the system page
1123 tables. The workaround changes the TLB flushing routines to invalidate
1124 entries regardless of the ASID.
1126 config ARM_ERRATA_743622
1127 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1129 depends on !ARCH_MULTIPLATFORM
1131 This option enables the workaround for the 743622 Cortex-A9
1132 (r2p*) erratum. Under very rare conditions, a faulty
1133 optimisation in the Cortex-A9 Store Buffer may lead to data
1134 corruption. This workaround sets a specific bit in the diagnostic
1135 register of the Cortex-A9 which disables the Store Buffer
1136 optimisation, preventing the defect from occurring. This has no
1137 visible impact on the overall performance or power consumption of the
1140 config ARM_ERRATA_751472
1141 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1143 depends on !ARCH_MULTIPLATFORM
1145 This option enables the workaround for the 751472 Cortex-A9 (prior
1146 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1147 completion of a following broadcasted operation if the second
1148 operation is received by a CPU before the ICIALLUIS has completed,
1149 potentially leading to corrupted entries in the cache or TLB.
1151 config ARM_ERRATA_754322
1152 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1155 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1156 r3p*) erratum. A speculative memory access may cause a page table walk
1157 which starts prior to an ASID switch but completes afterwards. This
1158 can populate the micro-TLB with a stale entry which may be hit with
1159 the new ASID. This workaround places two dsb instructions in the mm
1160 switching code so that no page table walks can cross the ASID switch.
1162 config ARM_ERRATA_754327
1163 bool "ARM errata: no automatic Store Buffer drain"
1164 depends on CPU_V7 && SMP
1166 This option enables the workaround for the 754327 Cortex-A9 (prior to
1167 r2p0) erratum. The Store Buffer does not have any automatic draining
1168 mechanism and therefore a livelock may occur if an external agent
1169 continuously polls a memory location waiting to observe an update.
1170 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1171 written polling loops from denying visibility of updates to memory.
1173 config ARM_ERRATA_364296
1174 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1177 This options enables the workaround for the 364296 ARM1136
1178 r0p2 erratum (possible cache data corruption with
1179 hit-under-miss enabled). It sets the undocumented bit 31 in
1180 the auxiliary control register and the FI bit in the control
1181 register, thus disabling hit-under-miss without putting the
1182 processor into full low interrupt latency mode. ARM11MPCore
1185 config ARM_ERRATA_764369
1186 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1187 depends on CPU_V7 && SMP
1189 This option enables the workaround for erratum 764369
1190 affecting Cortex-A9 MPCore with two or more processors (all
1191 current revisions). Under certain timing circumstances, a data
1192 cache line maintenance operation by MVA targeting an Inner
1193 Shareable memory region may fail to proceed up to either the
1194 Point of Coherency or to the Point of Unification of the
1195 system. This workaround adds a DSB instruction before the
1196 relevant cache maintenance functions and sets a specific bit
1197 in the diagnostic control register of the SCU.
1199 config ARM_ERRATA_775420
1200 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1203 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1204 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1205 operation aborts with MMU exception, it might cause the processor
1206 to deadlock. This workaround puts DSB before executing ISB if
1207 an abort may occur on cache maintenance.
1209 config ARM_ERRATA_798181
1210 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1211 depends on CPU_V7 && SMP
1213 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1214 adequately shooting down all use of the old entries. This
1215 option enables the Linux kernel workaround for this erratum
1216 which sends an IPI to the CPUs that are running the same ASID
1217 as the one being invalidated.
1219 config ARM_ERRATA_773022
1220 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1223 This option enables the workaround for the 773022 Cortex-A15
1224 (up to r0p4) erratum. In certain rare sequences of code, the
1225 loop buffer may deliver incorrect instructions. This
1226 workaround disables the loop buffer to avoid the erratum.
1230 source "arch/arm/common/Kconfig"
1237 Find out whether you have ISA slots on your motherboard. ISA is the
1238 name of a bus system, i.e. the way the CPU talks to the other stuff
1239 inside your box. Other bus systems are PCI, EISA, MicroChannel
1240 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1241 newer boards don't support it. If you have ISA, say Y, otherwise N.
1243 # Select ISA DMA controller support
1248 # Select ISA DMA interface
1253 bool "PCI support" if MIGHT_HAVE_PCI
1255 Find out whether you have a PCI motherboard. PCI is the name of a
1256 bus system, i.e. the way the CPU talks to the other stuff inside
1257 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1258 VESA. If you have PCI, say Y, otherwise N.
1264 config PCI_DOMAINS_GENERIC
1265 def_bool PCI_DOMAINS
1267 config PCI_NANOENGINE
1268 bool "BSE nanoEngine PCI support"
1269 depends on SA1100_NANOENGINE
1271 Enable PCI on the BSE nanoEngine board.
1276 config PCI_HOST_ITE8152
1278 depends on PCI && MACH_ARMCORE
1282 source "drivers/pci/Kconfig"
1283 source "drivers/pci/pcie/Kconfig"
1285 source "drivers/pcmcia/Kconfig"
1289 menu "Kernel Features"
1294 This option should be selected by machines which have an SMP-
1297 The only effect of this option is to make the SMP-related
1298 options available to the user for configuration.
1301 bool "Symmetric Multi-Processing"
1302 depends on CPU_V6K || CPU_V7
1303 depends on GENERIC_CLOCKEVENTS
1305 depends on MMU || ARM_MPU
1308 This enables support for systems with more than one CPU. If you have
1309 a system with only one CPU, say N. If you have a system with more
1310 than one CPU, say Y.
1312 If you say N here, the kernel will run on uni- and multiprocessor
1313 machines, but will use only one CPU of a multiprocessor machine. If
1314 you say Y here, the kernel will run on many, but not all,
1315 uniprocessor machines. On a uniprocessor machine, the kernel
1316 will run faster if you say N here.
1318 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1319 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1320 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1322 If you don't know what to do here, say N.
1325 bool "Allow booting SMP kernel on uniprocessor systems"
1326 depends on SMP && !XIP_KERNEL && MMU
1329 SMP kernels contain instructions which fail on non-SMP processors.
1330 Enabling this option allows the kernel to modify itself to make
1331 these instructions safe. Disabling it allows about 1K of space
1334 If you don't know what to do here, say Y.
1336 config ARM_CPU_TOPOLOGY
1337 bool "Support cpu topology definition"
1338 depends on SMP && CPU_V7
1341 Support ARM cpu topology definition. The MPIDR register defines
1342 affinity between processors which is then used to describe the cpu
1343 topology of an ARM System.
1346 bool "Multi-core scheduler support"
1347 depends on ARM_CPU_TOPOLOGY
1349 Multi-core scheduler support improves the CPU scheduler's decision
1350 making when dealing with multi-core CPU chips at a cost of slightly
1351 increased overhead in some places. If unsure say N here.
1354 bool "SMT scheduler support"
1355 depends on ARM_CPU_TOPOLOGY
1357 Improves the CPU scheduler's decision making when dealing with
1358 MultiThreading at a cost of slightly increased overhead in some
1359 places. If unsure say N here.
1364 This option enables support for the ARM system coherency unit
1366 config HAVE_ARM_ARCH_TIMER
1367 bool "Architected timer support"
1369 select ARM_ARCH_TIMER
1370 select GENERIC_CLOCKEVENTS
1372 This option enables support for the ARM architected timer
1376 select CLKSRC_OF if OF
1378 This options enables support for the ARM timer and watchdog unit
1381 bool "Multi-Cluster Power Management"
1382 depends on CPU_V7 && SMP
1384 This option provides the common power management infrastructure
1385 for (multi-)cluster based systems, such as big.LITTLE based
1388 config MCPM_QUAD_CLUSTER
1392 To avoid wasting resources unnecessarily, MCPM only supports up
1393 to 2 clusters by default.
1394 Platforms with 3 or 4 clusters that use MCPM must select this
1395 option to allow the additional clusters to be managed.
1398 bool "big.LITTLE support (Experimental)"
1399 depends on CPU_V7 && SMP
1402 This option enables support selections for the big.LITTLE
1403 system architecture.
1406 bool "big.LITTLE switcher support"
1407 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1408 select ARM_CPU_SUSPEND
1411 The big.LITTLE "switcher" provides the core functionality to
1412 transparently handle transition between a cluster of A15's
1413 and a cluster of A7's in a big.LITTLE system.
1415 config BL_SWITCHER_DUMMY_IF
1416 tristate "Simple big.LITTLE switcher user interface"
1417 depends on BL_SWITCHER && DEBUG_KERNEL
1419 This is a simple and dummy char dev interface to control
1420 the big.LITTLE switcher core code. It is meant for
1421 debugging purposes only.
1424 prompt "Memory split"
1428 Select the desired split between kernel and user memory.
1430 If you are not absolutely sure what you are doing, leave this
1434 bool "3G/1G user/kernel split"
1435 config VMSPLIT_3G_OPT
1436 bool "3G/1G user/kernel split (for full 1G low memory)"
1438 bool "2G/2G user/kernel split"
1440 bool "1G/3G user/kernel split"
1445 default PHYS_OFFSET if !MMU
1446 default 0x40000000 if VMSPLIT_1G
1447 default 0x80000000 if VMSPLIT_2G
1448 default 0xB0000000 if VMSPLIT_3G_OPT
1452 int "Maximum number of CPUs (2-32)"
1458 bool "Support for hot-pluggable CPUs"
1461 Say Y here to experiment with turning CPUs off and on. CPUs
1462 can be controlled through /sys/devices/system/cpu.
1465 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1469 Say Y here if you want Linux to communicate with system firmware
1470 implementing the PSCI specification for CPU-centric power
1471 management operations described in ARM document number ARM DEN
1472 0022A ("Power State Coordination Interface System Software on
1475 # The GPIO number here must be sorted by descending number. In case of
1476 # a multiplatform kernel, we just want the highest value required by the
1477 # selected platforms.
1480 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1482 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1483 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1484 default 416 if ARCH_SUNXI
1485 default 392 if ARCH_U8500
1486 default 352 if ARCH_VT8500
1487 default 288 if ARCH_ROCKCHIP
1488 default 264 if MACH_H4700
1491 Maximum number of GPIOs in the system.
1493 If unsure, leave the default value.
1495 source kernel/Kconfig.preempt
1499 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1500 ARCH_S5PV210 || ARCH_EXYNOS4
1501 default 128 if SOC_AT91RM9200
1505 depends on HZ_FIXED = 0
1506 prompt "Timer frequency"
1530 default HZ_FIXED if HZ_FIXED != 0
1531 default 100 if HZ_100
1532 default 200 if HZ_200
1533 default 250 if HZ_250
1534 default 300 if HZ_300
1535 default 500 if HZ_500
1539 def_bool HIGH_RES_TIMERS
1541 config THUMB2_KERNEL
1542 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1543 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1544 default y if CPU_THUMBONLY
1546 select ARM_ASM_UNIFIED
1549 By enabling this option, the kernel will be compiled in
1550 Thumb-2 mode. A compiler/assembler that understand the unified
1551 ARM-Thumb syntax is needed.
1555 config THUMB2_AVOID_R_ARM_THM_JUMP11
1556 bool "Work around buggy Thumb-2 short branch relocations in gas"
1557 depends on THUMB2_KERNEL && MODULES
1560 Various binutils versions can resolve Thumb-2 branches to
1561 locally-defined, preemptible global symbols as short-range "b.n"
1562 branch instructions.
1564 This is a problem, because there's no guarantee the final
1565 destination of the symbol, or any candidate locations for a
1566 trampoline, are within range of the branch. For this reason, the
1567 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1568 relocation in modules at all, and it makes little sense to add
1571 The symptom is that the kernel fails with an "unsupported
1572 relocation" error when loading some modules.
1574 Until fixed tools are available, passing
1575 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1576 code which hits this problem, at the cost of a bit of extra runtime
1577 stack usage in some cases.
1579 The problem is described in more detail at:
1580 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1582 Only Thumb-2 kernels are affected.
1584 Unless you are sure your tools don't have this problem, say Y.
1586 config ARM_ASM_UNIFIED
1590 bool "Use the ARM EABI to compile the kernel"
1592 This option allows for the kernel to be compiled using the latest
1593 ARM ABI (aka EABI). This is only useful if you are using a user
1594 space environment that is also compiled with EABI.
1596 Since there are major incompatibilities between the legacy ABI and
1597 EABI, especially with regard to structure member alignment, this
1598 option also changes the kernel syscall calling convention to
1599 disambiguate both ABIs and allow for backward compatibility support
1600 (selected with CONFIG_OABI_COMPAT).
1602 To use this you need GCC version 4.0.0 or later.
1605 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1606 depends on AEABI && !THUMB2_KERNEL
1608 This option preserves the old syscall interface along with the
1609 new (ARM EABI) one. It also provides a compatibility layer to
1610 intercept syscalls that have structure arguments which layout
1611 in memory differs between the legacy ABI and the new ARM EABI
1612 (only for non "thumb" binaries). This option adds a tiny
1613 overhead to all syscalls and produces a slightly larger kernel.
1615 The seccomp filter system will not be available when this is
1616 selected, since there is no way yet to sensibly distinguish
1617 between calling conventions during filtering.
1619 If you know you'll be using only pure EABI user space then you
1620 can say N here. If this option is not selected and you attempt
1621 to execute a legacy ABI binary then the result will be
1622 UNPREDICTABLE (in fact it can be predicted that it won't work
1623 at all). If in doubt say N.
1625 config ARCH_HAS_HOLES_MEMORYMODEL
1628 config ARCH_SPARSEMEM_ENABLE
1631 config ARCH_SPARSEMEM_DEFAULT
1632 def_bool ARCH_SPARSEMEM_ENABLE
1634 config ARCH_SELECT_MEMORY_MODEL
1635 def_bool ARCH_SPARSEMEM_ENABLE
1637 config HAVE_ARCH_PFN_VALID
1638 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1640 config HAVE_GENERIC_RCU_GUP
1645 bool "High Memory Support"
1648 The address space of ARM processors is only 4 Gigabytes large
1649 and it has to accommodate user address space, kernel address
1650 space as well as some memory mapped IO. That means that, if you
1651 have a large amount of physical memory and/or IO, not all of the
1652 memory can be "permanently mapped" by the kernel. The physical
1653 memory that is not permanently mapped is called "high memory".
1655 Depending on the selected kernel/user memory split, minimum
1656 vmalloc space and actual amount of RAM, you may not need this
1657 option which should result in a slightly faster kernel.
1662 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1666 The VM uses one page of physical memory for each page table.
1667 For systems with a lot of processes, this can use a lot of
1668 precious low memory, eventually leading to low memory being
1669 consumed by page tables. Setting this option will allow
1670 user-space 2nd level page tables to reside in high memory.
1672 config CPU_SW_DOMAIN_PAN
1673 bool "Enable use of CPU domains to implement privileged no-access"
1674 depends on MMU && !ARM_LPAE
1677 Increase kernel security by ensuring that normal kernel accesses
1678 are unable to access userspace addresses. This can help prevent
1679 use-after-free bugs becoming an exploitable privilege escalation
1680 by ensuring that magic values (such as LIST_POISON) will always
1681 fault when dereferenced.
1683 CPUs with low-vector mappings use a best-efforts implementation.
1684 Their lower 1MB needs to remain accessible for the vectors, but
1685 the remainder of userspace will become appropriately inaccessible.
1687 config HW_PERF_EVENTS
1691 config SYS_SUPPORTS_HUGETLBFS
1695 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1699 config ARCH_WANT_GENERAL_HUGETLB
1702 config ARM_MODULE_PLTS
1703 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1706 Allocate PLTs when loading modules so that jumps and calls whose
1707 targets are too far away for their relative offsets to be encoded
1708 in the instructions themselves can be bounced via veneers in the
1709 module's PLT. This allows modules to be allocated in the generic
1710 vmalloc area after the dedicated module memory area has been
1711 exhausted. The modules will use slightly more memory, but after
1712 rounding up to page size, the actual memory footprint is usually
1715 Say y if you are getting out of memory errors while loading modules
1719 config FORCE_MAX_ZONEORDER
1720 int "Maximum zone order"
1721 default "12" if SOC_AM33XX
1722 default "9" if SA1111 || ARCH_EFM32
1725 The kernel memory allocator divides physically contiguous memory
1726 blocks into "zones", where each zone is a power of two number of
1727 pages. This option selects the largest power of two that the kernel
1728 keeps in the memory allocator. If you need to allocate very large
1729 blocks of physically contiguous memory, then you may need to
1730 increase this value.
1732 This config option is actually maximum order plus one. For example,
1733 a value of 11 means that the largest free memory block is 2^10 pages.
1735 config ALIGNMENT_TRAP
1737 depends on CPU_CP15_MMU
1738 default y if !ARCH_EBSA110
1739 select HAVE_PROC_CPU if PROC_FS
1741 ARM processors cannot fetch/store information which is not
1742 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1743 address divisible by 4. On 32-bit ARM processors, these non-aligned
1744 fetch/store instructions will be emulated in software if you say
1745 here, which has a severe performance impact. This is necessary for
1746 correct operation of some network protocols. With an IP-only
1747 configuration it is safe to say N, otherwise say Y.
1749 config UACCESS_WITH_MEMCPY
1750 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1752 default y if CPU_FEROCEON
1754 Implement faster copy_to_user and clear_user methods for CPU
1755 cores where a 8-word STM instruction give significantly higher
1756 memory write throughput than a sequence of individual 32bit stores.
1758 A possible side effect is a slight increase in scheduling latency
1759 between threads sharing the same address space if they invoke
1760 such copy operations with large buffers.
1762 However, if the CPU data cache is using a write-allocate mode,
1763 this option is unlikely to provide any performance gain.
1767 prompt "Enable seccomp to safely compute untrusted bytecode"
1769 This kernel feature is useful for number crunching applications
1770 that may need to compute untrusted bytecode during their
1771 execution. By using pipes or other transports made available to
1772 the process as file descriptors supporting the read/write
1773 syscalls, it's possible to isolate those applications in
1774 their own address space using seccomp. Once seccomp is
1775 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1776 and the task is only allowed to execute a few safe syscalls
1777 defined by each seccomp mode.
1790 bool "Xen guest support on ARM"
1791 depends on ARM && AEABI && OF
1792 depends on CPU_V7 && !CPU_V6
1793 depends on !GENERIC_ATOMIC64
1795 select ARCH_DMA_ADDR_T_64BIT
1799 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1806 bool "Flattened Device Tree support"
1809 select OF_EARLY_FLATTREE
1810 select OF_RESERVED_MEM
1812 Include support for flattened device tree machine descriptions.
1815 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1818 This is the traditional way of passing data to the kernel at boot
1819 time. If you are solely relying on the flattened device tree (or
1820 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1821 to remove ATAGS support from your kernel binary. If unsure,
1824 config DEPRECATED_PARAM_STRUCT
1825 bool "Provide old way to pass kernel parameters"
1828 This was deprecated in 2001 and announced to live on for 5 years.
1829 Some old boot loaders still use this way.
1831 # Compressed boot loader in ROM. Yes, we really want to ask about
1832 # TEXT and BSS so we preserve their values in the config files.
1833 config ZBOOT_ROM_TEXT
1834 hex "Compressed ROM boot loader base address"
1837 The physical address at which the ROM-able zImage is to be
1838 placed in the target. Platforms which normally make use of
1839 ROM-able zImage formats normally set this to a suitable
1840 value in their defconfig file.
1842 If ZBOOT_ROM is not enabled, this has no effect.
1844 config ZBOOT_ROM_BSS
1845 hex "Compressed ROM boot loader BSS address"
1848 The base address of an area of read/write memory in the target
1849 for the ROM-able zImage which must be available while the
1850 decompressor is running. It must be large enough to hold the
1851 entire decompressed kernel plus an additional 128 KiB.
1852 Platforms which normally make use of ROM-able zImage formats
1853 normally set this to a suitable value in their defconfig file.
1855 If ZBOOT_ROM is not enabled, this has no effect.
1858 bool "Compressed boot loader in ROM/flash"
1859 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1860 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1862 Say Y here if you intend to execute your compressed kernel image
1863 (zImage) directly from ROM or flash. If unsure, say N.
1865 config ARM_APPENDED_DTB
1866 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1869 With this option, the boot code will look for a device tree binary
1870 (DTB) appended to zImage
1871 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1873 This is meant as a backward compatibility convenience for those
1874 systems with a bootloader that can't be upgraded to accommodate
1875 the documented boot protocol using a device tree.
1877 Beware that there is very little in terms of protection against
1878 this option being confused by leftover garbage in memory that might
1879 look like a DTB header after a reboot if no actual DTB is appended
1880 to zImage. Do not leave this option active in a production kernel
1881 if you don't intend to always append a DTB. Proper passing of the
1882 location into r2 of a bootloader provided DTB is always preferable
1885 config ARM_ATAG_DTB_COMPAT
1886 bool "Supplement the appended DTB with traditional ATAG information"
1887 depends on ARM_APPENDED_DTB
1889 Some old bootloaders can't be updated to a DTB capable one, yet
1890 they provide ATAGs with memory configuration, the ramdisk address,
1891 the kernel cmdline string, etc. Such information is dynamically
1892 provided by the bootloader and can't always be stored in a static
1893 DTB. To allow a device tree enabled kernel to be used with such
1894 bootloaders, this option allows zImage to extract the information
1895 from the ATAG list and store it at run time into the appended DTB.
1898 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1899 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1901 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1902 bool "Use bootloader kernel arguments if available"
1904 Uses the command-line options passed by the boot loader instead of
1905 the device tree bootargs property. If the boot loader doesn't provide
1906 any, the device tree bootargs property will be used.
1908 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1909 bool "Extend with bootloader kernel arguments"
1911 The command-line arguments provided by the boot loader will be
1912 appended to the the device tree bootargs property.
1917 string "Default kernel command string"
1920 On some architectures (EBSA110 and CATS), there is currently no way
1921 for the boot loader to pass arguments to the kernel. For these
1922 architectures, you should supply some command-line options at build
1923 time by entering them here. As a minimum, you should specify the
1924 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1927 prompt "Kernel command line type" if CMDLINE != ""
1928 default CMDLINE_FROM_BOOTLOADER
1931 config CMDLINE_FROM_BOOTLOADER
1932 bool "Use bootloader kernel arguments if available"
1934 Uses the command-line options passed by the boot loader. If
1935 the boot loader doesn't provide any, the default kernel command
1936 string provided in CMDLINE will be used.
1938 config CMDLINE_EXTEND
1939 bool "Extend bootloader kernel arguments"
1941 The command-line arguments provided by the boot loader will be
1942 appended to the default kernel command string.
1944 config CMDLINE_FORCE
1945 bool "Always use the default kernel command string"
1947 Always use the default kernel command string, even if the boot
1948 loader passes other arguments to the kernel.
1949 This is useful if you cannot or don't want to change the
1950 command-line options your boot loader passes to the kernel.
1954 bool "Kernel Execute-In-Place from ROM"
1955 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1957 Execute-In-Place allows the kernel to run from non-volatile storage
1958 directly addressable by the CPU, such as NOR flash. This saves RAM
1959 space since the text section of the kernel is not loaded from flash
1960 to RAM. Read-write sections, such as the data section and stack,
1961 are still copied to RAM. The XIP kernel is not compressed since
1962 it has to run directly from flash, so it will take more space to
1963 store it. The flash address used to link the kernel object files,
1964 and for storing it, is configuration dependent. Therefore, if you
1965 say Y here, you must know the proper physical address where to
1966 store the kernel image depending on your own flash memory usage.
1968 Also note that the make target becomes "make xipImage" rather than
1969 "make zImage" or "make Image". The final kernel binary to put in
1970 ROM memory will be arch/arm/boot/xipImage.
1974 config XIP_PHYS_ADDR
1975 hex "XIP Kernel Physical Location"
1976 depends on XIP_KERNEL
1977 default "0x00080000"
1979 This is the physical address in your flash memory the kernel will
1980 be linked for and stored to. This address is dependent on your
1984 bool "Kexec system call (EXPERIMENTAL)"
1985 depends on (!SMP || PM_SLEEP_SMP)
1989 kexec is a system call that implements the ability to shutdown your
1990 current kernel, and to start another kernel. It is like a reboot
1991 but it is independent of the system firmware. And like a reboot
1992 you can start any kernel with it, not just Linux.
1994 It is an ongoing process to be certain the hardware in a machine
1995 is properly shutdown, so do not be surprised if this code does not
1996 initially work for you.
1999 bool "Export atags in procfs"
2000 depends on ATAGS && KEXEC
2003 Should the atags used to boot the kernel be exported in an "atags"
2004 file in procfs. Useful with kexec.
2007 bool "Build kdump crash kernel (EXPERIMENTAL)"
2009 Generate crash dump after being started by kexec. This should
2010 be normally only set in special crash dump kernels which are
2011 loaded in the main kernel with kexec-tools into a specially
2012 reserved region and then later executed after a crash by
2013 kdump/kexec. The crash dump kernel must be compiled to a
2014 memory address not used by the main kernel
2016 For more details see Documentation/kdump/kdump.txt
2018 config AUTO_ZRELADDR
2019 bool "Auto calculation of the decompressed kernel image address"
2021 ZRELADDR is the physical address where the decompressed kernel
2022 image will be placed. If AUTO_ZRELADDR is selected, the address
2023 will be determined at run-time by masking the current IP with
2024 0xf8000000. This assumes the zImage being placed in the first 128MB
2025 from start of memory.
2029 menu "CPU Power Management"
2031 source "drivers/cpufreq/Kconfig"
2033 source "drivers/cpuidle/Kconfig"
2037 menu "Floating point emulation"
2039 comment "At least one emulation must be selected"
2042 bool "NWFPE math emulation"
2043 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2045 Say Y to include the NWFPE floating point emulator in the kernel.
2046 This is necessary to run most binaries. Linux does not currently
2047 support floating point hardware so you need to say Y here even if
2048 your machine has an FPA or floating point co-processor podule.
2050 You may say N here if you are going to load the Acorn FPEmulator
2051 early in the bootup.
2054 bool "Support extended precision"
2055 depends on FPE_NWFPE
2057 Say Y to include 80-bit support in the kernel floating-point
2058 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2059 Note that gcc does not generate 80-bit operations by default,
2060 so in most cases this option only enlarges the size of the
2061 floating point emulator without any good reason.
2063 You almost surely want to say N here.
2066 bool "FastFPE math emulation (EXPERIMENTAL)"
2067 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2069 Say Y here to include the FAST floating point emulator in the kernel.
2070 This is an experimental much faster emulator which now also has full
2071 precision for the mantissa. It does not support any exceptions.
2072 It is very simple, and approximately 3-6 times faster than NWFPE.
2074 It should be sufficient for most programs. It may be not suitable
2075 for scientific calculations, but you have to check this for yourself.
2076 If you do not feel you need a faster FP emulation you should better
2080 bool "VFP-format floating point maths"
2081 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2083 Say Y to include VFP support code in the kernel. This is needed
2084 if your hardware includes a VFP unit.
2086 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2087 release notes and additional status information.
2089 Say N if your target does not have VFP hardware.
2097 bool "Advanced SIMD (NEON) Extension support"
2098 depends on VFPv3 && CPU_V7
2100 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2103 config KERNEL_MODE_NEON
2104 bool "Support for NEON in kernel mode"
2105 depends on NEON && AEABI
2107 Say Y to include support for NEON in kernel mode.
2111 menu "Userspace binary formats"
2113 source "fs/Kconfig.binfmt"
2117 menu "Power management options"
2119 source "kernel/power/Kconfig"
2121 config ARCH_SUSPEND_POSSIBLE
2122 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2123 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2126 config ARM_CPU_SUSPEND
2129 config ARCH_HIBERNATION_POSSIBLE
2132 default y if ARCH_SUSPEND_POSSIBLE
2136 source "net/Kconfig"
2138 source "drivers/Kconfig"
2140 source "drivers/firmware/Kconfig"
2144 source "arch/arm/Kconfig.debug"
2146 source "security/Kconfig"
2148 source "crypto/Kconfig"
2150 source "arch/arm/crypto/Kconfig"
2153 source "lib/Kconfig"
2155 source "arch/arm/kvm/Kconfig"