1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_CLOCKSOURCE_DATA
7 select ARCH_HAS_BINFMT_FLAT
8 select ARCH_HAS_DEBUG_VIRTUAL if MMU
9 select ARCH_HAS_DEVMEM_IS_ALLOWED
10 select ARCH_HAS_ELF_RANDOMIZE
11 select ARCH_HAS_FORTIFY_SOURCE
12 select ARCH_HAS_KEEPINITRD
14 select ARCH_HAS_MEMBARRIER_SYNC_CORE
15 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
16 select ARCH_HAS_PHYS_TO_DMA
17 select ARCH_HAS_SETUP_DMA_OPS
18 select ARCH_HAS_SET_MEMORY
19 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
20 select ARCH_HAS_STRICT_MODULE_RWX if MMU
21 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
22 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
23 select ARCH_HAVE_CUSTOM_GPIO_H
24 select ARCH_HAS_GCOV_PROFILE_ALL
25 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC
26 select ARCH_MIGHT_HAVE_PC_PARPORT
27 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
28 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
29 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
30 select ARCH_SUPPORTS_ATOMIC_RMW
31 select ARCH_USE_BUILTIN_BSWAP
32 select ARCH_USE_CMPXCHG_LOCKREF
33 select ARCH_WANT_IPC_PARSE_VERSION
34 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
35 select BUILDTIME_EXTABLE_SORT if MMU
36 select CLONE_BACKWARDS
37 select CPU_PM if SUSPEND || CPU_IDLE
38 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
39 select DMA_DECLARE_COHERENT
40 select DMA_REMAP if MMU
42 select EDAC_ATOMIC_SCRUB
43 select GENERIC_ALLOCATOR
44 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
45 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
46 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
47 select GENERIC_CPU_AUTOPROBE
48 select GENERIC_EARLY_IOREMAP
49 select GENERIC_IDLE_POLL_SETUP
50 select GENERIC_IRQ_PROBE
51 select GENERIC_IRQ_SHOW
52 select GENERIC_IRQ_SHOW_LEVEL
53 select GENERIC_PCI_IOMAP
54 select GENERIC_SCHED_CLOCK
55 select GENERIC_SMP_IDLE_THREAD
56 select GENERIC_STRNCPY_FROM_USER
57 select GENERIC_STRNLEN_USER
58 select HANDLE_DOMAIN_IRQ
59 select HARDIRQS_SW_RESEND
60 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
61 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
62 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
63 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
64 select HAVE_ARCH_MMAP_RND_BITS if MMU
65 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
66 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
67 select HAVE_ARCH_TRACEHOOK
68 select HAVE_ARM_SMCCC if CPU_V7
69 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
70 select HAVE_CONTEXT_TRACKING
71 select HAVE_C_RECORDMCOUNT
72 select HAVE_DEBUG_KMEMLEAK
73 select HAVE_DMA_CONTIGUOUS if MMU
74 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
75 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
76 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
77 select HAVE_EXIT_THREAD
78 select HAVE_FAST_GUP if ARM_LPAE
79 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
80 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
81 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
82 select HAVE_GCC_PLUGINS
83 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
84 select HAVE_IDE if PCI || ISA || PCMCIA
85 select HAVE_IRQ_TIME_ACCOUNTING
86 select HAVE_KERNEL_GZIP
87 select HAVE_KERNEL_LZ4
88 select HAVE_KERNEL_LZMA
89 select HAVE_KERNEL_LZO
91 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
92 select HAVE_KRETPROBES if HAVE_KPROBES
93 select HAVE_MOD_ARCH_SPECIFIC
95 select HAVE_OPROFILE if HAVE_PERF_EVENTS
96 select HAVE_OPTPROBES if !THUMB2_KERNEL
97 select HAVE_PERF_EVENTS
99 select HAVE_PERF_USER_STACK_DUMP
100 select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE
101 select HAVE_REGS_AND_STACK_ACCESS_API
103 select HAVE_STACKPROTECTOR
104 select HAVE_SYSCALL_TRACEPOINTS
106 select HAVE_VIRT_CPU_ACCOUNTING_GEN
107 select IRQ_FORCED_THREADING
108 select MODULES_USE_ELF_REL
109 select NEED_DMA_MAP_STATE
110 select OF_EARLY_FLATTREE if OF
112 select OLD_SIGSUSPEND3
113 select PCI_SYSCALL if PCI
114 select PERF_USE_VMALLOC
117 select SYS_SUPPORTS_APM_EMULATION
118 # Above selects are sorted alphabetically; please add new ones
119 # according to that. Thanks.
121 The ARM series is a line of low-power-consumption RISC chip designs
122 licensed by ARM Ltd and targeted at embedded applications and
123 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
124 manufactured, but legacy ARM-based PC hardware remains popular in
125 Europe. There is an ARM Linux project with a web page at
126 <http://www.arm.linux.org.uk/>.
128 config ARM_HAS_SG_CHAIN
131 config ARM_DMA_USE_IOMMU
133 select ARM_HAS_SG_CHAIN
134 select NEED_SG_DMA_LENGTH
138 config ARM_DMA_IOMMU_ALIGNMENT
139 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
143 DMA mapping framework by default aligns all buffers to the smallest
144 PAGE_SIZE order which is greater than or equal to the requested buffer
145 size. This works well for buffers up to a few hundreds kilobytes, but
146 for larger buffers it just a waste of address space. Drivers which has
147 relatively small addressing window (like 64Mib) might run out of
148 virtual space with just a few allocations.
150 With this parameter you can specify the maximum PAGE_SIZE order for
151 DMA IOMMU buffers. Larger buffers will be aligned only to this
152 specified order. The order is expressed as a power of two multiplied
157 config SYS_SUPPORTS_APM_EMULATION
162 select GENERIC_ALLOCATOR
173 config STACKTRACE_SUPPORT
177 config LOCKDEP_SUPPORT
181 config TRACE_IRQFLAGS_SUPPORT
185 config ARCH_HAS_ILOG2_U32
188 config ARCH_HAS_ILOG2_U64
191 config ARCH_HAS_BANDGAP
194 config FIX_EARLYCON_MEM
197 config GENERIC_HWEIGHT
201 config GENERIC_CALIBRATE_DELAY
205 config ARCH_MAY_HAVE_PC_FDC
211 config ARCH_SUPPORTS_UPROBES
214 config ARCH_HAS_DMA_SET_COHERENT_MASK
217 config GENERIC_ISA_DMA
223 config NEED_RET_TO_USER
229 config ARM_PATCH_PHYS_VIRT
230 bool "Patch physical to virtual translations at runtime" if EMBEDDED
232 depends on !XIP_KERNEL && MMU
234 Patch phys-to-virt and virt-to-phys translation functions at
235 boot and module load time according to the position of the
236 kernel in system memory.
238 This can only be used with non-XIP MMU kernels where the base
239 of physical memory is at a 16MB boundary.
241 Only disable this option if you know that you do not require
242 this feature (eg, building a kernel for a single machine) and
243 you need to shrink the kernel to the minimal size.
245 config NEED_MACH_IO_H
248 Select this when mach/io.h is required to provide special
249 definitions for this platform. The need for mach/io.h should
250 be avoided when possible.
252 config NEED_MACH_MEMORY_H
255 Select this when mach/memory.h is required to provide special
256 definitions for this platform. The need for mach/memory.h should
257 be avoided when possible.
260 hex "Physical address of main memory" if MMU
261 depends on !ARM_PATCH_PHYS_VIRT
262 default DRAM_BASE if !MMU
263 default 0x00000000 if ARCH_EBSA110 || \
267 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
268 default 0x20000000 if ARCH_S5PV210
269 default 0xc0000000 if ARCH_SA1100
271 Please provide the physical address corresponding to the
272 location of main memory in your system.
278 config PGTABLE_LEVELS
280 default 3 if ARM_LPAE
286 bool "MMU-based Paged Memory Management Support"
289 Select if you want MMU-based virtualised addressing space
290 support by paged memory management. If unsure, say 'Y'.
292 config ARCH_MMAP_RND_BITS_MIN
295 config ARCH_MMAP_RND_BITS_MAX
296 default 14 if PAGE_OFFSET=0x40000000
297 default 15 if PAGE_OFFSET=0x80000000
301 # The "ARM system type" choice list is ordered alphabetically by option
302 # text. Please add new entries in the option alphabetic order.
305 prompt "ARM system type"
306 default ARM_SINGLE_ARMV7M if !MMU
307 default ARCH_MULTIPLATFORM if MMU
309 config ARCH_MULTIPLATFORM
310 bool "Allow multiple platforms to be selected"
312 select ARM_HAS_SG_CHAIN
313 select ARM_PATCH_PHYS_VIRT
317 select GENERIC_CLOCKEVENTS
318 select GENERIC_IRQ_MULTI_HANDLER
320 select PCI_DOMAINS_GENERIC if PCI
324 config ARM_SINGLE_ARMV7M
325 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
332 select GENERIC_CLOCKEVENTS
339 select ARCH_USES_GETTIMEOFFSET
342 select NEED_MACH_IO_H
343 select NEED_MACH_MEMORY_H
346 This is an evaluation board for the StrongARM processor available
347 from Digital. It has limited hardware on-board, including an
348 Ethernet interface, two PCMCIA sockets, two serial ports and a
353 select ARCH_SPARSEMEM_ENABLE
355 imply ARM_PATCH_PHYS_VIRT
361 select GENERIC_CLOCKEVENTS
364 This enables support for the Cirrus EP93xx series of CPUs.
366 config ARCH_FOOTBRIDGE
370 select GENERIC_CLOCKEVENTS
372 select NEED_MACH_IO_H if !MMU
373 select NEED_MACH_MEMORY_H
375 Support for systems based on the DC21285 companion chip
376 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
384 select NEED_RET_TO_USER
388 Support for Intel's 80219 and IOP32X (XScale) family of
394 select ARCH_HAS_DMA_SET_COHERENT_MASK
395 select ARCH_SUPPORTS_BIG_ENDIAN
397 select DMABOUNCE if PCI
398 select GENERIC_CLOCKEVENTS
399 select GENERIC_IRQ_MULTI_HANDLER
405 select NEED_MACH_IO_H
406 select USB_EHCI_BIG_ENDIAN_DESC
407 select USB_EHCI_BIG_ENDIAN_MMIO
409 Support for Intel's IXP4XX (XScale) family of processors.
414 select GENERIC_CLOCKEVENTS
415 select GENERIC_IRQ_MULTI_HANDLER
421 select PLAT_ORION_LEGACY
423 select PM_GENERIC_DOMAINS if PM
425 Support for the Marvell Dove SoC 88AP510
428 bool "PXA2xx/PXA3xx-based"
431 select ARM_CPU_SUSPEND if PM
438 select CPU_XSCALE if !CPU_XSC3
439 select GENERIC_CLOCKEVENTS
440 select GENERIC_IRQ_MULTI_HANDLER
448 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
454 select ARCH_MAY_HAVE_PC_FDC
455 select ARCH_SPARSEMEM_ENABLE
456 select ARM_HAS_SG_CHAIN
460 select HAVE_PATA_PLATFORM
462 select NEED_MACH_IO_H
463 select NEED_MACH_MEMORY_H
466 On the Acorn Risc-PC, Linux can support the internal IDE disk and
467 CD-ROM interface, serial and parallel port, and the floppy drive.
472 select ARCH_SPARSEMEM_ENABLE
476 select TIMER_OF if OF
480 select GENERIC_CLOCKEVENTS
481 select GENERIC_IRQ_MULTI_HANDLER
486 select NEED_MACH_MEMORY_H
489 Support for StrongARM 11x0 based boards.
492 bool "Samsung S3C24XX SoCs"
495 select CLKSRC_SAMSUNG_PWM
496 select GENERIC_CLOCKEVENTS
499 select GENERIC_IRQ_MULTI_HANDLER
500 select HAVE_S3C2410_I2C if I2C
501 select HAVE_S3C2410_WATCHDOG if WATCHDOG
502 select HAVE_S3C_RTC if RTC_CLASS
503 select NEED_MACH_IO_H
507 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
508 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
509 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
510 Samsung SMDK2410 development board (and derivatives).
515 select ARCH_HAS_HOLES_MEMORYMODEL
519 select GENERIC_CLOCKEVENTS
520 select GENERIC_IRQ_CHIP
521 select GENERIC_IRQ_MULTI_HANDLER
525 select NEED_MACH_IO_H if PCCARD
526 select NEED_MACH_MEMORY_H
529 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
533 menu "Multiple platform selection"
534 depends on ARCH_MULTIPLATFORM
536 comment "CPU Core family selection"
539 bool "ARMv4 based platforms (FA526)"
540 depends on !ARCH_MULTI_V6_V7
541 select ARCH_MULTI_V4_V5
544 config ARCH_MULTI_V4T
545 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
546 depends on !ARCH_MULTI_V6_V7
547 select ARCH_MULTI_V4_V5
548 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
549 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
550 CPU_ARM925T || CPU_ARM940T)
553 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
554 depends on !ARCH_MULTI_V6_V7
555 select ARCH_MULTI_V4_V5
556 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
557 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
558 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
560 config ARCH_MULTI_V4_V5
564 bool "ARMv6 based platforms (ARM11)"
565 select ARCH_MULTI_V6_V7
569 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
571 select ARCH_MULTI_V6_V7
575 config ARCH_MULTI_V6_V7
577 select MIGHT_HAVE_CACHE_L2X0
579 config ARCH_MULTI_CPU_AUTO
580 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
586 bool "Dummy Virtual Machine"
587 depends on ARCH_MULTI_V7
590 select ARM_GIC_V2M if PCI
592 select ARM_GIC_V3_ITS if PCI
594 select HAVE_ARM_ARCH_TIMER
595 select ARCH_SUPPORTS_BIG_ENDIAN
598 # This is sorted alphabetically by mach-* pathname. However, plat-*
599 # Kconfigs may be included either alphabetically (according to the
600 # plat- suffix) or along side the corresponding mach-* source.
602 source "arch/arm/mach-actions/Kconfig"
604 source "arch/arm/mach-alpine/Kconfig"
606 source "arch/arm/mach-artpec/Kconfig"
608 source "arch/arm/mach-asm9260/Kconfig"
610 source "arch/arm/mach-aspeed/Kconfig"
612 source "arch/arm/mach-at91/Kconfig"
614 source "arch/arm/mach-axxia/Kconfig"
616 source "arch/arm/mach-bcm/Kconfig"
618 source "arch/arm/mach-berlin/Kconfig"
620 source "arch/arm/mach-clps711x/Kconfig"
622 source "arch/arm/mach-cns3xxx/Kconfig"
624 source "arch/arm/mach-davinci/Kconfig"
626 source "arch/arm/mach-digicolor/Kconfig"
628 source "arch/arm/mach-dove/Kconfig"
630 source "arch/arm/mach-ep93xx/Kconfig"
632 source "arch/arm/mach-exynos/Kconfig"
633 source "arch/arm/plat-samsung/Kconfig"
635 source "arch/arm/mach-footbridge/Kconfig"
637 source "arch/arm/mach-gemini/Kconfig"
639 source "arch/arm/mach-highbank/Kconfig"
641 source "arch/arm/mach-hisi/Kconfig"
643 source "arch/arm/mach-imx/Kconfig"
645 source "arch/arm/mach-integrator/Kconfig"
647 source "arch/arm/mach-iop32x/Kconfig"
649 source "arch/arm/mach-ixp4xx/Kconfig"
651 source "arch/arm/mach-keystone/Kconfig"
653 source "arch/arm/mach-lpc32xx/Kconfig"
655 source "arch/arm/mach-mediatek/Kconfig"
657 source "arch/arm/mach-meson/Kconfig"
659 source "arch/arm/mach-milbeaut/Kconfig"
661 source "arch/arm/mach-mmp/Kconfig"
663 source "arch/arm/mach-moxart/Kconfig"
665 source "arch/arm/mach-mv78xx0/Kconfig"
667 source "arch/arm/mach-mvebu/Kconfig"
669 source "arch/arm/mach-mxs/Kconfig"
671 source "arch/arm/mach-nomadik/Kconfig"
673 source "arch/arm/mach-npcm/Kconfig"
675 source "arch/arm/mach-nspire/Kconfig"
677 source "arch/arm/plat-omap/Kconfig"
679 source "arch/arm/mach-omap1/Kconfig"
681 source "arch/arm/mach-omap2/Kconfig"
683 source "arch/arm/mach-orion5x/Kconfig"
685 source "arch/arm/mach-oxnas/Kconfig"
687 source "arch/arm/mach-picoxcell/Kconfig"
689 source "arch/arm/mach-prima2/Kconfig"
691 source "arch/arm/mach-pxa/Kconfig"
692 source "arch/arm/plat-pxa/Kconfig"
694 source "arch/arm/mach-qcom/Kconfig"
696 source "arch/arm/mach-rda/Kconfig"
698 source "arch/arm/mach-realview/Kconfig"
700 source "arch/arm/mach-rockchip/Kconfig"
702 source "arch/arm/mach-s3c24xx/Kconfig"
704 source "arch/arm/mach-s3c64xx/Kconfig"
706 source "arch/arm/mach-s5pv210/Kconfig"
708 source "arch/arm/mach-sa1100/Kconfig"
710 source "arch/arm/mach-shmobile/Kconfig"
712 source "arch/arm/mach-socfpga/Kconfig"
714 source "arch/arm/mach-spear/Kconfig"
716 source "arch/arm/mach-sti/Kconfig"
718 source "arch/arm/mach-stm32/Kconfig"
720 source "arch/arm/mach-sunxi/Kconfig"
722 source "arch/arm/mach-tango/Kconfig"
724 source "arch/arm/mach-tegra/Kconfig"
726 source "arch/arm/mach-u300/Kconfig"
728 source "arch/arm/mach-uniphier/Kconfig"
730 source "arch/arm/mach-ux500/Kconfig"
732 source "arch/arm/mach-versatile/Kconfig"
734 source "arch/arm/mach-vexpress/Kconfig"
735 source "arch/arm/plat-versatile/Kconfig"
737 source "arch/arm/mach-vt8500/Kconfig"
739 source "arch/arm/mach-zx/Kconfig"
741 source "arch/arm/mach-zynq/Kconfig"
743 # ARMv7-M architecture
745 bool "Energy Micro efm32"
746 depends on ARM_SINGLE_ARMV7M
749 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
753 bool "NXP LPC18xx/LPC43xx"
754 depends on ARM_SINGLE_ARMV7M
755 select ARCH_HAS_RESET_CONTROLLER
757 select CLKSRC_LPC32XX
760 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
761 high performance microcontrollers.
764 bool "ARM MPS2 platform"
765 depends on ARM_SINGLE_ARMV7M
769 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
770 with a range of available cores like Cortex-M3/M4/M7.
772 Please, note that depends which Application Note is used memory map
773 for the platform may vary, so adjustment of RAM base might be needed.
775 # Definitions to make life easier
781 select GENERIC_CLOCKEVENTS
787 select GENERIC_IRQ_CHIP
790 config PLAT_ORION_LEGACY
797 config PLAT_VERSATILE
800 source "arch/arm/mm/Kconfig"
803 bool "Enable iWMMXt support"
804 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
805 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
807 Enable support for iWMMXt context switching at run time if
808 running on a CPU that supports it.
811 source "arch/arm/Kconfig-nommu"
814 config PJ4B_ERRATA_4742
815 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
816 depends on CPU_PJ4B && MACH_ARMADA_370
819 When coming out of either a Wait for Interrupt (WFI) or a Wait for
820 Event (WFE) IDLE states, a specific timing sensitivity exists between
821 the retiring WFI/WFE instructions and the newly issued subsequent
822 instructions. This sensitivity can result in a CPU hang scenario.
824 The software must insert either a Data Synchronization Barrier (DSB)
825 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
828 config ARM_ERRATA_326103
829 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
832 Executing a SWP instruction to read-only memory does not set bit 11
833 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
834 treat the access as a read, preventing a COW from occurring and
835 causing the faulting task to livelock.
837 config ARM_ERRATA_411920
838 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
839 depends on CPU_V6 || CPU_V6K
841 Invalidation of the Instruction Cache operation can
842 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
843 It does not affect the MPCore. This option enables the ARM Ltd.
844 recommended workaround.
846 config ARM_ERRATA_430973
847 bool "ARM errata: Stale prediction on replaced interworking branch"
850 This option enables the workaround for the 430973 Cortex-A8
851 r1p* erratum. If a code sequence containing an ARM/Thumb
852 interworking branch is replaced with another code sequence at the
853 same virtual address, whether due to self-modifying code or virtual
854 to physical address re-mapping, Cortex-A8 does not recover from the
855 stale interworking branch prediction. This results in Cortex-A8
856 executing the new code sequence in the incorrect ARM or Thumb state.
857 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
858 and also flushes the branch target cache at every context switch.
859 Note that setting specific bits in the ACTLR register may not be
860 available in non-secure mode.
862 config ARM_ERRATA_458693
863 bool "ARM errata: Processor deadlock when a false hazard is created"
865 depends on !ARCH_MULTIPLATFORM
867 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
868 erratum. For very specific sequences of memory operations, it is
869 possible for a hazard condition intended for a cache line to instead
870 be incorrectly associated with a different cache line. This false
871 hazard might then cause a processor deadlock. The workaround enables
872 the L1 caching of the NEON accesses and disables the PLD instruction
873 in the ACTLR register. Note that setting specific bits in the ACTLR
874 register may not be available in non-secure mode.
876 config ARM_ERRATA_460075
877 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
879 depends on !ARCH_MULTIPLATFORM
881 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
882 erratum. Any asynchronous access to the L2 cache may encounter a
883 situation in which recent store transactions to the L2 cache are lost
884 and overwritten with stale memory contents from external memory. The
885 workaround disables the write-allocate mode for the L2 cache via the
886 ACTLR register. Note that setting specific bits in the ACTLR register
887 may not be available in non-secure mode.
889 config ARM_ERRATA_742230
890 bool "ARM errata: DMB operation may be faulty"
891 depends on CPU_V7 && SMP
892 depends on !ARCH_MULTIPLATFORM
894 This option enables the workaround for the 742230 Cortex-A9
895 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
896 between two write operations may not ensure the correct visibility
897 ordering of the two writes. This workaround sets a specific bit in
898 the diagnostic register of the Cortex-A9 which causes the DMB
899 instruction to behave as a DSB, ensuring the correct behaviour of
902 config ARM_ERRATA_742231
903 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
904 depends on CPU_V7 && SMP
905 depends on !ARCH_MULTIPLATFORM
907 This option enables the workaround for the 742231 Cortex-A9
908 (r2p0..r2p2) erratum. Under certain conditions, specific to the
909 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
910 accessing some data located in the same cache line, may get corrupted
911 data due to bad handling of the address hazard when the line gets
912 replaced from one of the CPUs at the same time as another CPU is
913 accessing it. This workaround sets specific bits in the diagnostic
914 register of the Cortex-A9 which reduces the linefill issuing
915 capabilities of the processor.
917 config ARM_ERRATA_643719
918 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
919 depends on CPU_V7 && SMP
922 This option enables the workaround for the 643719 Cortex-A9 (prior to
923 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
924 register returns zero when it should return one. The workaround
925 corrects this value, ensuring cache maintenance operations which use
926 it behave as intended and avoiding data corruption.
928 config ARM_ERRATA_720789
929 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
932 This option enables the workaround for the 720789 Cortex-A9 (prior to
933 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
934 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
935 As a consequence of this erratum, some TLB entries which should be
936 invalidated are not, resulting in an incoherency in the system page
937 tables. The workaround changes the TLB flushing routines to invalidate
938 entries regardless of the ASID.
940 config ARM_ERRATA_743622
941 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
943 depends on !ARCH_MULTIPLATFORM
945 This option enables the workaround for the 743622 Cortex-A9
946 (r2p*) erratum. Under very rare conditions, a faulty
947 optimisation in the Cortex-A9 Store Buffer may lead to data
948 corruption. This workaround sets a specific bit in the diagnostic
949 register of the Cortex-A9 which disables the Store Buffer
950 optimisation, preventing the defect from occurring. This has no
951 visible impact on the overall performance or power consumption of the
954 config ARM_ERRATA_751472
955 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
957 depends on !ARCH_MULTIPLATFORM
959 This option enables the workaround for the 751472 Cortex-A9 (prior
960 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
961 completion of a following broadcasted operation if the second
962 operation is received by a CPU before the ICIALLUIS has completed,
963 potentially leading to corrupted entries in the cache or TLB.
965 config ARM_ERRATA_754322
966 bool "ARM errata: possible faulty MMU translations following an ASID switch"
969 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
970 r3p*) erratum. A speculative memory access may cause a page table walk
971 which starts prior to an ASID switch but completes afterwards. This
972 can populate the micro-TLB with a stale entry which may be hit with
973 the new ASID. This workaround places two dsb instructions in the mm
974 switching code so that no page table walks can cross the ASID switch.
976 config ARM_ERRATA_754327
977 bool "ARM errata: no automatic Store Buffer drain"
978 depends on CPU_V7 && SMP
980 This option enables the workaround for the 754327 Cortex-A9 (prior to
981 r2p0) erratum. The Store Buffer does not have any automatic draining
982 mechanism and therefore a livelock may occur if an external agent
983 continuously polls a memory location waiting to observe an update.
984 This workaround defines cpu_relax() as smp_mb(), preventing correctly
985 written polling loops from denying visibility of updates to memory.
987 config ARM_ERRATA_364296
988 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
991 This options enables the workaround for the 364296 ARM1136
992 r0p2 erratum (possible cache data corruption with
993 hit-under-miss enabled). It sets the undocumented bit 31 in
994 the auxiliary control register and the FI bit in the control
995 register, thus disabling hit-under-miss without putting the
996 processor into full low interrupt latency mode. ARM11MPCore
999 config ARM_ERRATA_764369
1000 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1001 depends on CPU_V7 && SMP
1003 This option enables the workaround for erratum 764369
1004 affecting Cortex-A9 MPCore with two or more processors (all
1005 current revisions). Under certain timing circumstances, a data
1006 cache line maintenance operation by MVA targeting an Inner
1007 Shareable memory region may fail to proceed up to either the
1008 Point of Coherency or to the Point of Unification of the
1009 system. This workaround adds a DSB instruction before the
1010 relevant cache maintenance functions and sets a specific bit
1011 in the diagnostic control register of the SCU.
1013 config ARM_ERRATA_775420
1014 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1017 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1018 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1019 operation aborts with MMU exception, it might cause the processor
1020 to deadlock. This workaround puts DSB before executing ISB if
1021 an abort may occur on cache maintenance.
1023 config ARM_ERRATA_798181
1024 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1025 depends on CPU_V7 && SMP
1027 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1028 adequately shooting down all use of the old entries. This
1029 option enables the Linux kernel workaround for this erratum
1030 which sends an IPI to the CPUs that are running the same ASID
1031 as the one being invalidated.
1033 config ARM_ERRATA_773022
1034 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1037 This option enables the workaround for the 773022 Cortex-A15
1038 (up to r0p4) erratum. In certain rare sequences of code, the
1039 loop buffer may deliver incorrect instructions. This
1040 workaround disables the loop buffer to avoid the erratum.
1042 config ARM_ERRATA_818325_852422
1043 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1046 This option enables the workaround for:
1047 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1048 instruction might deadlock. Fixed in r0p1.
1049 - Cortex-A12 852422: Execution of a sequence of instructions might
1050 lead to either a data corruption or a CPU deadlock. Not fixed in
1051 any Cortex-A12 cores yet.
1052 This workaround for all both errata involves setting bit[12] of the
1053 Feature Register. This bit disables an optimisation applied to a
1054 sequence of 2 instructions that use opposing condition codes.
1056 config ARM_ERRATA_821420
1057 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1060 This option enables the workaround for the 821420 Cortex-A12
1061 (all revs) erratum. In very rare timing conditions, a sequence
1062 of VMOV to Core registers instructions, for which the second
1063 one is in the shadow of a branch or abort, can lead to a
1064 deadlock when the VMOV instructions are issued out-of-order.
1066 config ARM_ERRATA_825619
1067 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1070 This option enables the workaround for the 825619 Cortex-A12
1071 (all revs) erratum. Within rare timing constraints, executing a
1072 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1073 and Device/Strongly-Ordered loads and stores might cause deadlock
1075 config ARM_ERRATA_857271
1076 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1079 This option enables the workaround for the 857271 Cortex-A12
1080 (all revs) erratum. Under very rare timing conditions, the CPU might
1081 hang. The workaround is expected to have a < 1% performance impact.
1083 config ARM_ERRATA_852421
1084 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1087 This option enables the workaround for the 852421 Cortex-A17
1088 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1089 execution of a DMB ST instruction might fail to properly order
1090 stores from GroupA and stores from GroupB.
1092 config ARM_ERRATA_852423
1093 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1096 This option enables the workaround for:
1097 - Cortex-A17 852423: Execution of a sequence of instructions might
1098 lead to either a data corruption or a CPU deadlock. Not fixed in
1099 any Cortex-A17 cores yet.
1100 This is identical to Cortex-A12 erratum 852422. It is a separate
1101 config option from the A12 erratum due to the way errata are checked
1104 config ARM_ERRATA_857272
1105 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1108 This option enables the workaround for the 857272 Cortex-A17 erratum.
1109 This erratum is not known to be fixed in any A17 revision.
1110 This is identical to Cortex-A12 erratum 857271. It is a separate
1111 config option from the A12 erratum due to the way errata are checked
1116 source "arch/arm/common/Kconfig"
1123 Find out whether you have ISA slots on your motherboard. ISA is the
1124 name of a bus system, i.e. the way the CPU talks to the other stuff
1125 inside your box. Other bus systems are PCI, EISA, MicroChannel
1126 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1127 newer boards don't support it. If you have ISA, say Y, otherwise N.
1129 # Select ISA DMA controller support
1134 # Select ISA DMA interface
1138 config PCI_NANOENGINE
1139 bool "BSE nanoEngine PCI support"
1140 depends on SA1100_NANOENGINE
1142 Enable PCI on the BSE nanoEngine board.
1144 config PCI_HOST_ITE8152
1146 depends on PCI && MACH_ARMCORE
1150 config ARM_ERRATA_814220
1151 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1154 The v7 ARM states that all cache and branch predictor maintenance
1155 operations that do not specify an address execute, relative to
1156 each other, in program order.
1157 However, because of this erratum, an L2 set/way cache maintenance
1158 operation can overtake an L1 set/way cache maintenance operation.
1159 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1164 menu "Kernel Features"
1169 This option should be selected by machines which have an SMP-
1172 The only effect of this option is to make the SMP-related
1173 options available to the user for configuration.
1176 bool "Symmetric Multi-Processing"
1177 depends on CPU_V6K || CPU_V7
1178 depends on GENERIC_CLOCKEVENTS
1180 depends on MMU || ARM_MPU
1183 This enables support for systems with more than one CPU. If you have
1184 a system with only one CPU, say N. If you have a system with more
1185 than one CPU, say Y.
1187 If you say N here, the kernel will run on uni- and multiprocessor
1188 machines, but will use only one CPU of a multiprocessor machine. If
1189 you say Y here, the kernel will run on many, but not all,
1190 uniprocessor machines. On a uniprocessor machine, the kernel
1191 will run faster if you say N here.
1193 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1194 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1195 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1197 If you don't know what to do here, say N.
1200 bool "Allow booting SMP kernel on uniprocessor systems"
1201 depends on SMP && !XIP_KERNEL && MMU
1204 SMP kernels contain instructions which fail on non-SMP processors.
1205 Enabling this option allows the kernel to modify itself to make
1206 these instructions safe. Disabling it allows about 1K of space
1209 If you don't know what to do here, say Y.
1211 config ARM_CPU_TOPOLOGY
1212 bool "Support cpu topology definition"
1213 depends on SMP && CPU_V7
1216 Support ARM cpu topology definition. The MPIDR register defines
1217 affinity between processors which is then used to describe the cpu
1218 topology of an ARM System.
1221 bool "Multi-core scheduler support"
1222 depends on ARM_CPU_TOPOLOGY
1224 Multi-core scheduler support improves the CPU scheduler's decision
1225 making when dealing with multi-core CPU chips at a cost of slightly
1226 increased overhead in some places. If unsure say N here.
1229 bool "SMT scheduler support"
1230 depends on ARM_CPU_TOPOLOGY
1232 Improves the CPU scheduler's decision making when dealing with
1233 MultiThreading at a cost of slightly increased overhead in some
1234 places. If unsure say N here.
1239 This option enables support for the ARM snoop control unit
1241 config HAVE_ARM_ARCH_TIMER
1242 bool "Architected timer support"
1244 select ARM_ARCH_TIMER
1245 select GENERIC_CLOCKEVENTS
1247 This option enables support for the ARM architected timer
1252 This options enables support for the ARM timer and watchdog unit
1255 bool "Multi-Cluster Power Management"
1256 depends on CPU_V7 && SMP
1258 This option provides the common power management infrastructure
1259 for (multi-)cluster based systems, such as big.LITTLE based
1262 config MCPM_QUAD_CLUSTER
1266 To avoid wasting resources unnecessarily, MCPM only supports up
1267 to 2 clusters by default.
1268 Platforms with 3 or 4 clusters that use MCPM must select this
1269 option to allow the additional clusters to be managed.
1272 bool "big.LITTLE support (Experimental)"
1273 depends on CPU_V7 && SMP
1276 This option enables support selections for the big.LITTLE
1277 system architecture.
1280 bool "big.LITTLE switcher support"
1281 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1284 The big.LITTLE "switcher" provides the core functionality to
1285 transparently handle transition between a cluster of A15's
1286 and a cluster of A7's in a big.LITTLE system.
1288 config BL_SWITCHER_DUMMY_IF
1289 tristate "Simple big.LITTLE switcher user interface"
1290 depends on BL_SWITCHER && DEBUG_KERNEL
1292 This is a simple and dummy char dev interface to control
1293 the big.LITTLE switcher core code. It is meant for
1294 debugging purposes only.
1297 prompt "Memory split"
1301 Select the desired split between kernel and user memory.
1303 If you are not absolutely sure what you are doing, leave this
1307 bool "3G/1G user/kernel split"
1308 config VMSPLIT_3G_OPT
1309 depends on !ARM_LPAE
1310 bool "3G/1G user/kernel split (for full 1G low memory)"
1312 bool "2G/2G user/kernel split"
1314 bool "1G/3G user/kernel split"
1319 default PHYS_OFFSET if !MMU
1320 default 0x40000000 if VMSPLIT_1G
1321 default 0x80000000 if VMSPLIT_2G
1322 default 0xB0000000 if VMSPLIT_3G_OPT
1326 int "Maximum number of CPUs (2-32)"
1332 bool "Support for hot-pluggable CPUs"
1334 select GENERIC_IRQ_MIGRATION
1336 Say Y here to experiment with turning CPUs off and on. CPUs
1337 can be controlled through /sys/devices/system/cpu.
1340 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1341 depends on HAVE_ARM_SMCCC
1344 Say Y here if you want Linux to communicate with system firmware
1345 implementing the PSCI specification for CPU-centric power
1346 management operations described in ARM document number ARM DEN
1347 0022A ("Power State Coordination Interface System Software on
1350 # The GPIO number here must be sorted by descending number. In case of
1351 # a multiplatform kernel, we just want the highest value required by the
1352 # selected platforms.
1355 default 2048 if ARCH_SOCFPGA
1356 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1358 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1359 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1360 default 416 if ARCH_SUNXI
1361 default 392 if ARCH_U8500
1362 default 352 if ARCH_VT8500
1363 default 288 if ARCH_ROCKCHIP
1364 default 264 if MACH_H4700
1367 Maximum number of GPIOs in the system.
1369 If unsure, leave the default value.
1373 default 200 if ARCH_EBSA110
1374 default 128 if SOC_AT91RM9200
1378 depends on HZ_FIXED = 0
1379 prompt "Timer frequency"
1403 default HZ_FIXED if HZ_FIXED != 0
1404 default 100 if HZ_100
1405 default 200 if HZ_200
1406 default 250 if HZ_250
1407 default 300 if HZ_300
1408 default 500 if HZ_500
1412 def_bool HIGH_RES_TIMERS
1414 config THUMB2_KERNEL
1415 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1416 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1417 default y if CPU_THUMBONLY
1420 By enabling this option, the kernel will be compiled in
1425 config THUMB2_AVOID_R_ARM_THM_JUMP11
1426 bool "Work around buggy Thumb-2 short branch relocations in gas"
1427 depends on THUMB2_KERNEL && MODULES
1430 Various binutils versions can resolve Thumb-2 branches to
1431 locally-defined, preemptible global symbols as short-range "b.n"
1432 branch instructions.
1434 This is a problem, because there's no guarantee the final
1435 destination of the symbol, or any candidate locations for a
1436 trampoline, are within range of the branch. For this reason, the
1437 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1438 relocation in modules at all, and it makes little sense to add
1441 The symptom is that the kernel fails with an "unsupported
1442 relocation" error when loading some modules.
1444 Until fixed tools are available, passing
1445 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1446 code which hits this problem, at the cost of a bit of extra runtime
1447 stack usage in some cases.
1449 The problem is described in more detail at:
1450 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1452 Only Thumb-2 kernels are affected.
1454 Unless you are sure your tools don't have this problem, say Y.
1456 config ARM_PATCH_IDIV
1457 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1458 depends on CPU_32v7 && !XIP_KERNEL
1461 The ARM compiler inserts calls to __aeabi_idiv() and
1462 __aeabi_uidiv() when it needs to perform division on signed
1463 and unsigned integers. Some v7 CPUs have support for the sdiv
1464 and udiv instructions that can be used to implement those
1467 Enabling this option allows the kernel to modify itself to
1468 replace the first two instructions of these library functions
1469 with the sdiv or udiv plus "bx lr" instructions when the CPU
1470 it is running on supports them. Typically this will be faster
1471 and less power intensive than running the original library
1472 code to do integer division.
1475 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1476 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1478 This option allows for the kernel to be compiled using the latest
1479 ARM ABI (aka EABI). This is only useful if you are using a user
1480 space environment that is also compiled with EABI.
1482 Since there are major incompatibilities between the legacy ABI and
1483 EABI, especially with regard to structure member alignment, this
1484 option also changes the kernel syscall calling convention to
1485 disambiguate both ABIs and allow for backward compatibility support
1486 (selected with CONFIG_OABI_COMPAT).
1488 To use this you need GCC version 4.0.0 or later.
1491 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1492 depends on AEABI && !THUMB2_KERNEL
1494 This option preserves the old syscall interface along with the
1495 new (ARM EABI) one. It also provides a compatibility layer to
1496 intercept syscalls that have structure arguments which layout
1497 in memory differs between the legacy ABI and the new ARM EABI
1498 (only for non "thumb" binaries). This option adds a tiny
1499 overhead to all syscalls and produces a slightly larger kernel.
1501 The seccomp filter system will not be available when this is
1502 selected, since there is no way yet to sensibly distinguish
1503 between calling conventions during filtering.
1505 If you know you'll be using only pure EABI user space then you
1506 can say N here. If this option is not selected and you attempt
1507 to execute a legacy ABI binary then the result will be
1508 UNPREDICTABLE (in fact it can be predicted that it won't work
1509 at all). If in doubt say N.
1511 config ARCH_HAS_HOLES_MEMORYMODEL
1514 config ARCH_SPARSEMEM_ENABLE
1517 config ARCH_SPARSEMEM_DEFAULT
1518 def_bool ARCH_SPARSEMEM_ENABLE
1520 config HAVE_ARCH_PFN_VALID
1521 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1524 bool "High Memory Support"
1527 The address space of ARM processors is only 4 Gigabytes large
1528 and it has to accommodate user address space, kernel address
1529 space as well as some memory mapped IO. That means that, if you
1530 have a large amount of physical memory and/or IO, not all of the
1531 memory can be "permanently mapped" by the kernel. The physical
1532 memory that is not permanently mapped is called "high memory".
1534 Depending on the selected kernel/user memory split, minimum
1535 vmalloc space and actual amount of RAM, you may not need this
1536 option which should result in a slightly faster kernel.
1541 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1545 The VM uses one page of physical memory for each page table.
1546 For systems with a lot of processes, this can use a lot of
1547 precious low memory, eventually leading to low memory being
1548 consumed by page tables. Setting this option will allow
1549 user-space 2nd level page tables to reside in high memory.
1551 config CPU_SW_DOMAIN_PAN
1552 bool "Enable use of CPU domains to implement privileged no-access"
1553 depends on MMU && !ARM_LPAE
1556 Increase kernel security by ensuring that normal kernel accesses
1557 are unable to access userspace addresses. This can help prevent
1558 use-after-free bugs becoming an exploitable privilege escalation
1559 by ensuring that magic values (such as LIST_POISON) will always
1560 fault when dereferenced.
1562 CPUs with low-vector mappings use a best-efforts implementation.
1563 Their lower 1MB needs to remain accessible for the vectors, but
1564 the remainder of userspace will become appropriately inaccessible.
1566 config HW_PERF_EVENTS
1570 config SYS_SUPPORTS_HUGETLBFS
1574 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1578 config ARCH_WANT_GENERAL_HUGETLB
1581 config ARM_MODULE_PLTS
1582 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1586 Allocate PLTs when loading modules so that jumps and calls whose
1587 targets are too far away for their relative offsets to be encoded
1588 in the instructions themselves can be bounced via veneers in the
1589 module's PLT. This allows modules to be allocated in the generic
1590 vmalloc area after the dedicated module memory area has been
1591 exhausted. The modules will use slightly more memory, but after
1592 rounding up to page size, the actual memory footprint is usually
1595 Disabling this is usually safe for small single-platform
1596 configurations. If unsure, say y.
1598 config FORCE_MAX_ZONEORDER
1599 int "Maximum zone order"
1600 default "12" if SOC_AM33XX
1601 default "9" if SA1111 || ARCH_EFM32
1604 The kernel memory allocator divides physically contiguous memory
1605 blocks into "zones", where each zone is a power of two number of
1606 pages. This option selects the largest power of two that the kernel
1607 keeps in the memory allocator. If you need to allocate very large
1608 blocks of physically contiguous memory, then you may need to
1609 increase this value.
1611 This config option is actually maximum order plus one. For example,
1612 a value of 11 means that the largest free memory block is 2^10 pages.
1614 config ALIGNMENT_TRAP
1616 depends on CPU_CP15_MMU
1617 default y if !ARCH_EBSA110
1618 select HAVE_PROC_CPU if PROC_FS
1620 ARM processors cannot fetch/store information which is not
1621 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1622 address divisible by 4. On 32-bit ARM processors, these non-aligned
1623 fetch/store instructions will be emulated in software if you say
1624 here, which has a severe performance impact. This is necessary for
1625 correct operation of some network protocols. With an IP-only
1626 configuration it is safe to say N, otherwise say Y.
1628 config UACCESS_WITH_MEMCPY
1629 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1631 default y if CPU_FEROCEON
1633 Implement faster copy_to_user and clear_user methods for CPU
1634 cores where a 8-word STM instruction give significantly higher
1635 memory write throughput than a sequence of individual 32bit stores.
1637 A possible side effect is a slight increase in scheduling latency
1638 between threads sharing the same address space if they invoke
1639 such copy operations with large buffers.
1641 However, if the CPU data cache is using a write-allocate mode,
1642 this option is unlikely to provide any performance gain.
1646 prompt "Enable seccomp to safely compute untrusted bytecode"
1648 This kernel feature is useful for number crunching applications
1649 that may need to compute untrusted bytecode during their
1650 execution. By using pipes or other transports made available to
1651 the process as file descriptors supporting the read/write
1652 syscalls, it's possible to isolate those applications in
1653 their own address space using seccomp. Once seccomp is
1654 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1655 and the task is only allowed to execute a few safe syscalls
1656 defined by each seccomp mode.
1659 bool "Enable paravirtualization code"
1661 This changes the kernel so it can modify itself when it is run
1662 under a hypervisor, potentially improving performance significantly
1663 over full virtualization.
1665 config PARAVIRT_TIME_ACCOUNTING
1666 bool "Paravirtual steal time accounting"
1669 Select this option to enable fine granularity task steal time
1670 accounting. Time spent executing other tasks in parallel with
1671 the current vCPU is discounted from the vCPU power. To account for
1672 that, there can be a small performance impact.
1674 If in doubt, say N here.
1681 bool "Xen guest support on ARM"
1682 depends on ARM && AEABI && OF
1683 depends on CPU_V7 && !CPU_V6
1684 depends on !GENERIC_ATOMIC64
1686 select ARCH_DMA_ADDR_T_64BIT
1692 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1694 config STACKPROTECTOR_PER_TASK
1695 bool "Use a unique stack canary value for each task"
1696 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1697 select GCC_PLUGIN_ARM_SSP_PER_TASK
1700 Due to the fact that GCC uses an ordinary symbol reference from
1701 which to load the value of the stack canary, this value can only
1702 change at reboot time on SMP systems, and all tasks running in the
1703 kernel's address space are forced to use the same canary value for
1704 the entire duration that the system is up.
1706 Enable this option to switch to a different method that uses a
1707 different canary value for each task.
1714 bool "Flattened Device Tree support"
1718 Include support for flattened device tree machine descriptions.
1721 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1724 This is the traditional way of passing data to the kernel at boot
1725 time. If you are solely relying on the flattened device tree (or
1726 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1727 to remove ATAGS support from your kernel binary. If unsure,
1730 config DEPRECATED_PARAM_STRUCT
1731 bool "Provide old way to pass kernel parameters"
1734 This was deprecated in 2001 and announced to live on for 5 years.
1735 Some old boot loaders still use this way.
1737 # Compressed boot loader in ROM. Yes, we really want to ask about
1738 # TEXT and BSS so we preserve their values in the config files.
1739 config ZBOOT_ROM_TEXT
1740 hex "Compressed ROM boot loader base address"
1743 The physical address at which the ROM-able zImage is to be
1744 placed in the target. Platforms which normally make use of
1745 ROM-able zImage formats normally set this to a suitable
1746 value in their defconfig file.
1748 If ZBOOT_ROM is not enabled, this has no effect.
1750 config ZBOOT_ROM_BSS
1751 hex "Compressed ROM boot loader BSS address"
1754 The base address of an area of read/write memory in the target
1755 for the ROM-able zImage which must be available while the
1756 decompressor is running. It must be large enough to hold the
1757 entire decompressed kernel plus an additional 128 KiB.
1758 Platforms which normally make use of ROM-able zImage formats
1759 normally set this to a suitable value in their defconfig file.
1761 If ZBOOT_ROM is not enabled, this has no effect.
1764 bool "Compressed boot loader in ROM/flash"
1765 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1766 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1768 Say Y here if you intend to execute your compressed kernel image
1769 (zImage) directly from ROM or flash. If unsure, say N.
1771 config ARM_APPENDED_DTB
1772 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1775 With this option, the boot code will look for a device tree binary
1776 (DTB) appended to zImage
1777 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1779 This is meant as a backward compatibility convenience for those
1780 systems with a bootloader that can't be upgraded to accommodate
1781 the documented boot protocol using a device tree.
1783 Beware that there is very little in terms of protection against
1784 this option being confused by leftover garbage in memory that might
1785 look like a DTB header after a reboot if no actual DTB is appended
1786 to zImage. Do not leave this option active in a production kernel
1787 if you don't intend to always append a DTB. Proper passing of the
1788 location into r2 of a bootloader provided DTB is always preferable
1791 config ARM_ATAG_DTB_COMPAT
1792 bool "Supplement the appended DTB with traditional ATAG information"
1793 depends on ARM_APPENDED_DTB
1795 Some old bootloaders can't be updated to a DTB capable one, yet
1796 they provide ATAGs with memory configuration, the ramdisk address,
1797 the kernel cmdline string, etc. Such information is dynamically
1798 provided by the bootloader and can't always be stored in a static
1799 DTB. To allow a device tree enabled kernel to be used with such
1800 bootloaders, this option allows zImage to extract the information
1801 from the ATAG list and store it at run time into the appended DTB.
1804 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1805 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1807 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1808 bool "Use bootloader kernel arguments if available"
1810 Uses the command-line options passed by the boot loader instead of
1811 the device tree bootargs property. If the boot loader doesn't provide
1812 any, the device tree bootargs property will be used.
1814 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1815 bool "Extend with bootloader kernel arguments"
1817 The command-line arguments provided by the boot loader will be
1818 appended to the the device tree bootargs property.
1823 string "Default kernel command string"
1826 On some architectures (EBSA110 and CATS), there is currently no way
1827 for the boot loader to pass arguments to the kernel. For these
1828 architectures, you should supply some command-line options at build
1829 time by entering them here. As a minimum, you should specify the
1830 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1833 prompt "Kernel command line type" if CMDLINE != ""
1834 default CMDLINE_FROM_BOOTLOADER
1837 config CMDLINE_FROM_BOOTLOADER
1838 bool "Use bootloader kernel arguments if available"
1840 Uses the command-line options passed by the boot loader. If
1841 the boot loader doesn't provide any, the default kernel command
1842 string provided in CMDLINE will be used.
1844 config CMDLINE_EXTEND
1845 bool "Extend bootloader kernel arguments"
1847 The command-line arguments provided by the boot loader will be
1848 appended to the default kernel command string.
1850 config CMDLINE_FORCE
1851 bool "Always use the default kernel command string"
1853 Always use the default kernel command string, even if the boot
1854 loader passes other arguments to the kernel.
1855 This is useful if you cannot or don't want to change the
1856 command-line options your boot loader passes to the kernel.
1860 bool "Kernel Execute-In-Place from ROM"
1861 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1863 Execute-In-Place allows the kernel to run from non-volatile storage
1864 directly addressable by the CPU, such as NOR flash. This saves RAM
1865 space since the text section of the kernel is not loaded from flash
1866 to RAM. Read-write sections, such as the data section and stack,
1867 are still copied to RAM. The XIP kernel is not compressed since
1868 it has to run directly from flash, so it will take more space to
1869 store it. The flash address used to link the kernel object files,
1870 and for storing it, is configuration dependent. Therefore, if you
1871 say Y here, you must know the proper physical address where to
1872 store the kernel image depending on your own flash memory usage.
1874 Also note that the make target becomes "make xipImage" rather than
1875 "make zImage" or "make Image". The final kernel binary to put in
1876 ROM memory will be arch/arm/boot/xipImage.
1880 config XIP_PHYS_ADDR
1881 hex "XIP Kernel Physical Location"
1882 depends on XIP_KERNEL
1883 default "0x00080000"
1885 This is the physical address in your flash memory the kernel will
1886 be linked for and stored to. This address is dependent on your
1889 config XIP_DEFLATED_DATA
1890 bool "Store kernel .data section compressed in ROM"
1891 depends on XIP_KERNEL
1894 Before the kernel is actually executed, its .data section has to be
1895 copied to RAM from ROM. This option allows for storing that data
1896 in compressed form and decompressed to RAM rather than merely being
1897 copied, saving some precious ROM space. A possible drawback is a
1898 slightly longer boot delay.
1901 bool "Kexec system call (EXPERIMENTAL)"
1902 depends on (!SMP || PM_SLEEP_SMP)
1906 kexec is a system call that implements the ability to shutdown your
1907 current kernel, and to start another kernel. It is like a reboot
1908 but it is independent of the system firmware. And like a reboot
1909 you can start any kernel with it, not just Linux.
1911 It is an ongoing process to be certain the hardware in a machine
1912 is properly shutdown, so do not be surprised if this code does not
1913 initially work for you.
1916 bool "Export atags in procfs"
1917 depends on ATAGS && KEXEC
1920 Should the atags used to boot the kernel be exported in an "atags"
1921 file in procfs. Useful with kexec.
1924 bool "Build kdump crash kernel (EXPERIMENTAL)"
1926 Generate crash dump after being started by kexec. This should
1927 be normally only set in special crash dump kernels which are
1928 loaded in the main kernel with kexec-tools into a specially
1929 reserved region and then later executed after a crash by
1930 kdump/kexec. The crash dump kernel must be compiled to a
1931 memory address not used by the main kernel
1933 For more details see Documentation/admin-guide/kdump/kdump.rst
1935 config AUTO_ZRELADDR
1936 bool "Auto calculation of the decompressed kernel image address"
1938 ZRELADDR is the physical address where the decompressed kernel
1939 image will be placed. If AUTO_ZRELADDR is selected, the address
1940 will be determined at run-time by masking the current IP with
1941 0xf8000000. This assumes the zImage being placed in the first 128MB
1942 from start of memory.
1948 bool "UEFI runtime support"
1949 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1951 select EFI_PARAMS_FROM_FDT
1954 select EFI_RUNTIME_WRAPPERS
1956 This option provides support for runtime services provided
1957 by UEFI firmware (such as non-volatile variables, realtime
1958 clock, and platform reset). A UEFI stub is also provided to
1959 allow the kernel to be booted as an EFI application. This
1960 is only useful for kernels that may run on systems that have
1964 bool "Enable support for SMBIOS (DMI) tables"
1968 This enables SMBIOS/DMI feature for systems.
1970 This option is only useful on systems that have UEFI firmware.
1971 However, even with this option, the resultant kernel should
1972 continue to boot on existing non-UEFI platforms.
1974 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1975 i.e., the the practice of identifying the platform via DMI to
1976 decide whether certain workarounds for buggy hardware and/or
1977 firmware need to be enabled. This would require the DMI subsystem
1978 to be enabled much earlier than we do on ARM, which is non-trivial.
1982 menu "CPU Power Management"
1984 source "drivers/cpufreq/Kconfig"
1986 source "drivers/cpuidle/Kconfig"
1990 menu "Floating point emulation"
1992 comment "At least one emulation must be selected"
1995 bool "NWFPE math emulation"
1996 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1998 Say Y to include the NWFPE floating point emulator in the kernel.
1999 This is necessary to run most binaries. Linux does not currently
2000 support floating point hardware so you need to say Y here even if
2001 your machine has an FPA or floating point co-processor podule.
2003 You may say N here if you are going to load the Acorn FPEmulator
2004 early in the bootup.
2007 bool "Support extended precision"
2008 depends on FPE_NWFPE
2010 Say Y to include 80-bit support in the kernel floating-point
2011 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2012 Note that gcc does not generate 80-bit operations by default,
2013 so in most cases this option only enlarges the size of the
2014 floating point emulator without any good reason.
2016 You almost surely want to say N here.
2019 bool "FastFPE math emulation (EXPERIMENTAL)"
2020 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2022 Say Y here to include the FAST floating point emulator in the kernel.
2023 This is an experimental much faster emulator which now also has full
2024 precision for the mantissa. It does not support any exceptions.
2025 It is very simple, and approximately 3-6 times faster than NWFPE.
2027 It should be sufficient for most programs. It may be not suitable
2028 for scientific calculations, but you have to check this for yourself.
2029 If you do not feel you need a faster FP emulation you should better
2033 bool "VFP-format floating point maths"
2034 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2036 Say Y to include VFP support code in the kernel. This is needed
2037 if your hardware includes a VFP unit.
2039 Please see <file:Documentation/arm/vfp/release-notes.rst> for
2040 release notes and additional status information.
2042 Say N if your target does not have VFP hardware.
2050 bool "Advanced SIMD (NEON) Extension support"
2051 depends on VFPv3 && CPU_V7
2053 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2056 config KERNEL_MODE_NEON
2057 bool "Support for NEON in kernel mode"
2058 depends on NEON && AEABI
2060 Say Y to include support for NEON in kernel mode.
2064 menu "Power management options"
2066 source "kernel/power/Kconfig"
2068 config ARCH_SUSPEND_POSSIBLE
2069 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2070 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2073 config ARM_CPU_SUSPEND
2074 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2075 depends on ARCH_SUSPEND_POSSIBLE
2077 config ARCH_HIBERNATION_POSSIBLE
2080 default y if ARCH_SUSPEND_POSSIBLE
2084 source "drivers/firmware/Kconfig"
2087 source "arch/arm/crypto/Kconfig"
2090 source "arch/arm/kvm/Kconfig"