4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
29 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
30 select HAVE_ARCH_TRACEHOOK
32 select HAVE_CONTEXT_TRACKING
33 select HAVE_C_RECORDMCOUNT
34 select HAVE_CC_STACKPROTECTOR
35 select HAVE_DEBUG_KMEMLEAK
36 select HAVE_DMA_API_DEBUG
38 select HAVE_DMA_CONTIGUOUS if MMU
39 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
40 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
41 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
42 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
43 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
44 select HAVE_GENERIC_DMA_COHERENT
45 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
46 select HAVE_IDE if PCI || ISA || PCMCIA
47 select HAVE_IRQ_TIME_ACCOUNTING
48 select HAVE_KERNEL_GZIP
49 select HAVE_KERNEL_LZ4
50 select HAVE_KERNEL_LZMA
51 select HAVE_KERNEL_LZO
53 select HAVE_KPROBES if !XIP_KERNEL
54 select HAVE_KRETPROBES if (HAVE_KPROBES)
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
58 select HAVE_PERF_EVENTS
60 select HAVE_PERF_USER_STACK_DUMP
61 select HAVE_REGS_AND_STACK_ACCESS_API
62 select HAVE_SYSCALL_TRACEPOINTS
64 select HAVE_VIRT_CPU_ACCOUNTING_GEN
65 select IRQ_FORCED_THREADING
67 select MODULES_USE_ELF_REL
70 select OLD_SIGSUSPEND3
71 select PERF_USE_VMALLOC
73 select SYS_SUPPORTS_APM_EMULATION
74 # Above selects are sorted alphabetically; please add new ones
75 # according to that. Thanks.
77 The ARM series is a line of low-power-consumption RISC chip designs
78 licensed by ARM Ltd and targeted at embedded applications and
79 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
80 manufactured, but legacy ARM-based PC hardware remains popular in
81 Europe. There is an ARM Linux project with a web page at
82 <http://www.arm.linux.org.uk/>.
84 config ARM_HAS_SG_CHAIN
87 config NEED_SG_DMA_LENGTH
90 config ARM_DMA_USE_IOMMU
92 select ARM_HAS_SG_CHAIN
93 select NEED_SG_DMA_LENGTH
97 config ARM_DMA_IOMMU_ALIGNMENT
98 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
102 DMA mapping framework by default aligns all buffers to the smallest
103 PAGE_SIZE order which is greater than or equal to the requested buffer
104 size. This works well for buffers up to a few hundreds kilobytes, but
105 for larger buffers it just a waste of address space. Drivers which has
106 relatively small addressing window (like 64Mib) might run out of
107 virtual space with just a few allocations.
109 With this parameter you can specify the maximum PAGE_SIZE order for
110 DMA IOMMU buffers. Larger buffers will be aligned only to this
111 specified order. The order is expressed as a power of two multiplied
119 config MIGHT_HAVE_PCI
122 config SYS_SUPPORTS_APM_EMULATION
127 select GENERIC_ALLOCATOR
138 The Extended Industry Standard Architecture (EISA) bus was
139 developed as an open alternative to the IBM MicroChannel bus.
141 The EISA bus provided some of the features of the IBM MicroChannel
142 bus while maintaining backward compatibility with cards made for
143 the older ISA bus. The EISA bus saw limited use between 1988 and
144 1995 when it was made obsolete by the PCI bus.
146 Say Y here if you are building a kernel for an EISA-based machine.
153 config STACKTRACE_SUPPORT
157 config HAVE_LATENCYTOP_SUPPORT
162 config LOCKDEP_SUPPORT
166 config TRACE_IRQFLAGS_SUPPORT
170 config RWSEM_GENERIC_SPINLOCK
174 config RWSEM_XCHGADD_ALGORITHM
177 config ARCH_HAS_ILOG2_U32
180 config ARCH_HAS_ILOG2_U64
183 config ARCH_HAS_CPUFREQ
186 Internal node to signify that the ARCH has CPUFREQ support
187 and that the relevant menu configurations are displayed for
190 config ARCH_HAS_BANDGAP
193 config GENERIC_HWEIGHT
197 config GENERIC_CALIBRATE_DELAY
201 config ARCH_MAY_HAVE_PC_FDC
207 config NEED_DMA_MAP_STATE
210 config ARCH_SUPPORTS_UPROBES
213 config ARCH_HAS_DMA_SET_COHERENT_MASK
216 config GENERIC_ISA_DMA
222 config NEED_RET_TO_USER
230 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
231 default DRAM_BASE if REMAP_VECTORS_TO_RAM
234 The base address of exception vectors. This must be two pages
237 config ARM_PATCH_PHYS_VIRT
238 bool "Patch physical to virtual translations at runtime" if EMBEDDED
240 depends on !XIP_KERNEL && MMU
241 depends on !ARCH_REALVIEW || !SPARSEMEM
243 Patch phys-to-virt and virt-to-phys translation functions at
244 boot and module load time according to the position of the
245 kernel in system memory.
247 This can only be used with non-XIP MMU kernels where the base
248 of physical memory is at a 16MB boundary.
250 Only disable this option if you know that you do not require
251 this feature (eg, building a kernel for a single machine) and
252 you need to shrink the kernel to the minimal size.
254 config NEED_MACH_GPIO_H
257 Select this when mach/gpio.h is required to provide special
258 definitions for this platform. The need for mach/gpio.h should
259 be avoided when possible.
261 config NEED_MACH_IO_H
264 Select this when mach/io.h is required to provide special
265 definitions for this platform. The need for mach/io.h should
266 be avoided when possible.
268 config NEED_MACH_MEMORY_H
271 Select this when mach/memory.h is required to provide special
272 definitions for this platform. The need for mach/memory.h should
273 be avoided when possible.
276 hex "Physical address of main memory" if MMU
277 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
278 default DRAM_BASE if !MMU
280 Please provide the physical address corresponding to the
281 location of main memory in your system.
287 source "init/Kconfig"
289 source "kernel/Kconfig.freezer"
294 bool "MMU-based Paged Memory Management Support"
297 Select if you want MMU-based virtualised addressing space
298 support by paged memory management. If unsure, say 'Y'.
301 # The "ARM system type" choice list is ordered alphabetically by option
302 # text. Please add new entries in the option alphabetic order.
305 prompt "ARM system type"
306 default ARCH_VERSATILE if !MMU
307 default ARCH_MULTIPLATFORM if MMU
309 config ARCH_MULTIPLATFORM
310 bool "Allow multiple platforms to be selected"
312 select ARM_PATCH_PHYS_VIRT
315 select MULTI_IRQ_HANDLER
319 config ARCH_INTEGRATOR
320 bool "ARM Ltd. Integrator family"
321 select ARCH_HAS_CPUFREQ
323 select ARM_PATCH_PHYS_VIRT
326 select COMMON_CLK_VERSATILE
327 select GENERIC_CLOCKEVENTS
330 select MULTI_IRQ_HANDLER
331 select NEED_MACH_MEMORY_H
332 select PLAT_VERSATILE
335 select VERSATILE_FPGA_IRQ
337 Support for ARM's Integrator platform.
340 bool "ARM Ltd. RealView family"
341 select ARCH_WANT_OPTIONAL_GPIOLIB
343 select ARM_TIMER_SP804
345 select COMMON_CLK_VERSATILE
346 select GENERIC_CLOCKEVENTS
347 select GPIO_PL061 if GPIOLIB
349 select NEED_MACH_MEMORY_H
350 select PLAT_VERSATILE
351 select PLAT_VERSATILE_CLCD
353 This enables support for ARM Ltd RealView boards.
355 config ARCH_VERSATILE
356 bool "ARM Ltd. Versatile family"
357 select ARCH_WANT_OPTIONAL_GPIOLIB
359 select ARM_TIMER_SP804
362 select GENERIC_CLOCKEVENTS
363 select HAVE_MACH_CLKDEV
365 select PLAT_VERSATILE
366 select PLAT_VERSATILE_CLCD
367 select PLAT_VERSATILE_CLOCK
368 select VERSATILE_FPGA_IRQ
370 This enables support for ARM Ltd Versatile board.
374 select ARCH_REQUIRE_GPIOLIB
377 select NEED_MACH_GPIO_H
378 select NEED_MACH_IO_H if PCCARD
380 select PINCTRL_AT91 if USE_OF
382 This enables support for systems based on Atmel
383 AT91RM9200 and AT91SAM9* processors.
386 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
387 select ARCH_REQUIRE_GPIOLIB
392 select GENERIC_CLOCKEVENTS
394 select MULTI_IRQ_HANDLER
397 Support for Cirrus Logic 711x/721x/731x based boards.
400 bool "Cortina Systems Gemini"
401 select ARCH_REQUIRE_GPIOLIB
404 select GENERIC_CLOCKEVENTS
406 Support for the Cortina Systems Gemini family SoCs
410 select ARCH_USES_GETTIMEOFFSET
413 select NEED_MACH_IO_H
414 select NEED_MACH_MEMORY_H
417 This is an evaluation board for the StrongARM processor available
418 from Digital. It has limited hardware on-board, including an
419 Ethernet interface, two PCMCIA sockets, two serial ports and a
423 bool "Energy Micro efm32"
425 select ARCH_REQUIRE_GPIOLIB
427 # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged,
428 # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO
433 select GENERIC_CLOCKEVENTS
439 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
444 select ARCH_HAS_HOLES_MEMORYMODEL
445 select ARCH_REQUIRE_GPIOLIB
446 select ARCH_USES_GETTIMEOFFSET
451 select NEED_MACH_MEMORY_H
453 This enables support for the Cirrus EP93xx series of CPUs.
455 config ARCH_FOOTBRIDGE
459 select GENERIC_CLOCKEVENTS
461 select NEED_MACH_IO_H if !MMU
462 select NEED_MACH_MEMORY_H
464 Support for systems based on the DC21285 companion chip
465 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
468 bool "Hilscher NetX based"
472 select GENERIC_CLOCKEVENTS
474 This enables support for systems based on the Hilscher NetX Soc
480 select NEED_MACH_MEMORY_H
481 select NEED_RET_TO_USER
486 Support for Intel's IOP13XX (XScale) family of processors.
491 select ARCH_REQUIRE_GPIOLIB
494 select NEED_RET_TO_USER
498 Support for Intel's 80219 and IOP32X (XScale) family of
504 select ARCH_REQUIRE_GPIOLIB
507 select NEED_RET_TO_USER
511 Support for Intel's IOP33X (XScale) family of processors.
516 select ARCH_HAS_DMA_SET_COHERENT_MASK
517 select ARCH_SUPPORTS_BIG_ENDIAN
518 select ARCH_REQUIRE_GPIOLIB
521 select DMABOUNCE if PCI
522 select GENERIC_CLOCKEVENTS
523 select MIGHT_HAVE_PCI
524 select NEED_MACH_IO_H
525 select USB_EHCI_BIG_ENDIAN_DESC
526 select USB_EHCI_BIG_ENDIAN_MMIO
528 Support for Intel's IXP4XX (XScale) family of processors.
532 select ARCH_REQUIRE_GPIOLIB
534 select GENERIC_CLOCKEVENTS
535 select MIGHT_HAVE_PCI
539 select PLAT_ORION_LEGACY
540 select USB_ARCH_HAS_EHCI
542 Support for the Marvell Dove SoC 88AP510
545 bool "Marvell Kirkwood"
546 select ARCH_HAS_CPUFREQ
547 select ARCH_REQUIRE_GPIOLIB
549 select GENERIC_CLOCKEVENTS
554 select PINCTRL_KIRKWOOD
555 select PLAT_ORION_LEGACY
557 Support for the following Marvell Kirkwood series SoCs:
558 88F6180, 88F6192 and 88F6281.
561 bool "Marvell MV78xx0"
562 select ARCH_REQUIRE_GPIOLIB
564 select GENERIC_CLOCKEVENTS
567 select PLAT_ORION_LEGACY
569 Support for the following Marvell MV78xx0 series SoCs:
575 select ARCH_REQUIRE_GPIOLIB
577 select GENERIC_CLOCKEVENTS
580 select PLAT_ORION_LEGACY
582 Support for the following Marvell Orion 5x series SoCs:
583 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
584 Orion-2 (5281), Orion-1-90 (6183).
587 bool "Marvell PXA168/910/MMP2"
589 select ARCH_REQUIRE_GPIOLIB
591 select GENERIC_ALLOCATOR
592 select GENERIC_CLOCKEVENTS
595 select MULTI_IRQ_HANDLER
600 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
603 bool "Micrel/Kendin KS8695"
604 select ARCH_REQUIRE_GPIOLIB
607 select GENERIC_CLOCKEVENTS
608 select NEED_MACH_MEMORY_H
610 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
611 System-on-Chip devices.
614 bool "Nuvoton W90X900 CPU"
615 select ARCH_REQUIRE_GPIOLIB
619 select GENERIC_CLOCKEVENTS
621 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
622 At present, the w90x900 has been renamed nuc900, regarding
623 the ARM series product line, you can login the following
624 link address to know more.
626 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
627 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
631 select ARCH_REQUIRE_GPIOLIB
636 select GENERIC_CLOCKEVENTS
639 select USB_ARCH_HAS_OHCI
642 Support for the NXP LPC32XX family of processors
645 bool "PXA2xx/PXA3xx-based"
647 select ARCH_HAS_CPUFREQ
649 select ARCH_REQUIRE_GPIOLIB
650 select ARM_CPU_SUSPEND if PM
654 select GENERIC_CLOCKEVENTS
657 select MULTI_IRQ_HANDLER
661 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
666 select ARCH_REQUIRE_GPIOLIB
668 select GENERIC_CLOCKEVENTS
670 Support for Qualcomm MSM/QSD based systems. This runs on the
671 apps processor of the MSM/QSD and depends on a shared memory
672 interface to the modem processor which runs the baseband
673 stack and controls some vital subsystems
674 (clock and power control, etc).
676 config ARCH_SHMOBILE_LEGACY
677 bool "Renesas ARM SoCs (non-multiplatform)"
679 select ARM_PATCH_PHYS_VIRT
681 select GENERIC_CLOCKEVENTS
682 select HAVE_ARM_SCU if SMP
683 select HAVE_ARM_TWD if SMP
684 select HAVE_MACH_CLKDEV
686 select MIGHT_HAVE_CACHE_L2X0
687 select MULTI_IRQ_HANDLER
690 select PM_GENERIC_DOMAINS if PM
693 Support for Renesas ARM SoC platforms using a non-multiplatform
694 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
700 select ARCH_MAY_HAVE_PC_FDC
701 select ARCH_SPARSEMEM_ENABLE
702 select ARCH_USES_GETTIMEOFFSET
705 select HAVE_PATA_PLATFORM
707 select NEED_MACH_IO_H
708 select NEED_MACH_MEMORY_H
712 On the Acorn Risc-PC, Linux can support the internal IDE disk and
713 CD-ROM interface, serial and parallel port, and the floppy drive.
717 select ARCH_HAS_CPUFREQ
719 select ARCH_REQUIRE_GPIOLIB
720 select ARCH_SPARSEMEM_ENABLE
725 select GENERIC_CLOCKEVENTS
728 select NEED_MACH_MEMORY_H
731 Support for StrongARM 11x0 based boards.
734 bool "Samsung S3C24XX SoCs"
735 select ARCH_HAS_CPUFREQ
736 select ARCH_REQUIRE_GPIOLIB
738 select CLKSRC_SAMSUNG_PWM
739 select GENERIC_CLOCKEVENTS
741 select HAVE_S3C2410_I2C if I2C
742 select HAVE_S3C2410_WATCHDOG if WATCHDOG
743 select HAVE_S3C_RTC if RTC_CLASS
744 select MULTI_IRQ_HANDLER
745 select NEED_MACH_IO_H
748 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
749 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
750 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
751 Samsung SMDK2410 development board (and derivatives).
754 bool "Samsung S3C64XX"
755 select ARCH_HAS_CPUFREQ
756 select ARCH_REQUIRE_GPIOLIB
760 select CLKSRC_SAMSUNG_PWM
763 select GENERIC_CLOCKEVENTS
765 select HAVE_S3C2410_I2C if I2C
766 select HAVE_S3C2410_WATCHDOG if WATCHDOG
770 select PM_GENERIC_DOMAINS
772 select S3C_GPIO_TRACK
774 select SAMSUNG_WAKEMASK
775 select SAMSUNG_WDT_RESET
776 select USB_ARCH_HAS_OHCI
778 Samsung S3C64XX series based systems
781 bool "Samsung S5P6440 S5P6450"
783 select CLKSRC_SAMSUNG_PWM
785 select GENERIC_CLOCKEVENTS
787 select HAVE_S3C2410_I2C if I2C
788 select HAVE_S3C2410_WATCHDOG if WATCHDOG
789 select HAVE_S3C_RTC if RTC_CLASS
790 select NEED_MACH_GPIO_H
792 select SAMSUNG_WDT_RESET
794 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
798 bool "Samsung S5PC100"
799 select ARCH_REQUIRE_GPIOLIB
801 select CLKSRC_SAMSUNG_PWM
803 select GENERIC_CLOCKEVENTS
805 select HAVE_S3C2410_I2C if I2C
806 select HAVE_S3C2410_WATCHDOG if WATCHDOG
807 select HAVE_S3C_RTC if RTC_CLASS
808 select NEED_MACH_GPIO_H
810 select SAMSUNG_WDT_RESET
812 Samsung S5PC100 series based systems
815 bool "Samsung S5PV210/S5PC110"
816 select ARCH_HAS_CPUFREQ
817 select ARCH_HAS_HOLES_MEMORYMODEL
818 select ARCH_SPARSEMEM_ENABLE
820 select CLKSRC_SAMSUNG_PWM
822 select GENERIC_CLOCKEVENTS
824 select HAVE_S3C2410_I2C if I2C
825 select HAVE_S3C2410_WATCHDOG if WATCHDOG
826 select HAVE_S3C_RTC if RTC_CLASS
827 select NEED_MACH_GPIO_H
828 select NEED_MACH_MEMORY_H
831 Samsung S5PV210/S5PC110 series based systems
834 bool "Samsung EXYNOS"
835 select ARCH_HAS_CPUFREQ
836 select ARCH_HAS_HOLES_MEMORYMODEL
837 select ARCH_REQUIRE_GPIOLIB
838 select ARCH_SPARSEMEM_ENABLE
842 select GENERIC_CLOCKEVENTS
843 select HAVE_S3C2410_I2C if I2C
844 select HAVE_S3C2410_WATCHDOG if WATCHDOG
845 select HAVE_S3C_RTC if RTC_CLASS
846 select NEED_MACH_MEMORY_H
850 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
854 select ARCH_HAS_HOLES_MEMORYMODEL
855 select ARCH_REQUIRE_GPIOLIB
857 select GENERIC_ALLOCATOR
858 select GENERIC_CLOCKEVENTS
859 select GENERIC_IRQ_CHIP
865 Support for TI's DaVinci platform.
870 select ARCH_HAS_CPUFREQ
871 select ARCH_HAS_HOLES_MEMORYMODEL
873 select ARCH_REQUIRE_GPIOLIB
876 select GENERIC_CLOCKEVENTS
877 select GENERIC_IRQ_CHIP
880 select NEED_MACH_IO_H if PCCARD
881 select NEED_MACH_MEMORY_H
883 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
887 menu "Multiple platform selection"
888 depends on ARCH_MULTIPLATFORM
890 comment "CPU Core family selection"
892 config ARCH_MULTI_V4T
893 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
894 depends on !ARCH_MULTI_V6_V7
895 select ARCH_MULTI_V4_V5
896 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
897 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
898 CPU_ARM925T || CPU_ARM940T)
901 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
902 depends on !ARCH_MULTI_V6_V7
903 select ARCH_MULTI_V4_V5
904 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
905 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
906 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
908 config ARCH_MULTI_V4_V5
912 bool "ARMv6 based platforms (ARM11)"
913 select ARCH_MULTI_V6_V7
917 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
919 select ARCH_MULTI_V6_V7
922 config ARCH_MULTI_V6_V7
925 config ARCH_MULTI_CPU_AUTO
926 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
932 # This is sorted alphabetically by mach-* pathname. However, plat-*
933 # Kconfigs may be included either alphabetically (according to the
934 # plat- suffix) or along side the corresponding mach-* source.
936 source "arch/arm/mach-mvebu/Kconfig"
938 source "arch/arm/mach-at91/Kconfig"
940 source "arch/arm/mach-bcm/Kconfig"
942 source "arch/arm/mach-bcm2835/Kconfig"
944 source "arch/arm/mach-berlin/Kconfig"
946 source "arch/arm/mach-clps711x/Kconfig"
948 source "arch/arm/mach-cns3xxx/Kconfig"
950 source "arch/arm/mach-davinci/Kconfig"
952 source "arch/arm/mach-dove/Kconfig"
954 source "arch/arm/mach-ep93xx/Kconfig"
956 source "arch/arm/mach-footbridge/Kconfig"
958 source "arch/arm/mach-gemini/Kconfig"
960 source "arch/arm/mach-highbank/Kconfig"
962 source "arch/arm/mach-hisi/Kconfig"
964 source "arch/arm/mach-integrator/Kconfig"
966 source "arch/arm/mach-iop32x/Kconfig"
968 source "arch/arm/mach-iop33x/Kconfig"
970 source "arch/arm/mach-iop13xx/Kconfig"
972 source "arch/arm/mach-ixp4xx/Kconfig"
974 source "arch/arm/mach-keystone/Kconfig"
976 source "arch/arm/mach-kirkwood/Kconfig"
978 source "arch/arm/mach-ks8695/Kconfig"
980 source "arch/arm/mach-msm/Kconfig"
982 source "arch/arm/mach-moxart/Kconfig"
984 source "arch/arm/mach-mv78xx0/Kconfig"
986 source "arch/arm/mach-imx/Kconfig"
988 source "arch/arm/mach-mxs/Kconfig"
990 source "arch/arm/mach-netx/Kconfig"
992 source "arch/arm/mach-nomadik/Kconfig"
994 source "arch/arm/mach-nspire/Kconfig"
996 source "arch/arm/plat-omap/Kconfig"
998 source "arch/arm/mach-omap1/Kconfig"
1000 source "arch/arm/mach-omap2/Kconfig"
1002 source "arch/arm/mach-orion5x/Kconfig"
1004 source "arch/arm/mach-picoxcell/Kconfig"
1006 source "arch/arm/mach-pxa/Kconfig"
1007 source "arch/arm/plat-pxa/Kconfig"
1009 source "arch/arm/mach-mmp/Kconfig"
1011 source "arch/arm/mach-realview/Kconfig"
1013 source "arch/arm/mach-rockchip/Kconfig"
1015 source "arch/arm/mach-sa1100/Kconfig"
1017 source "arch/arm/plat-samsung/Kconfig"
1019 source "arch/arm/mach-socfpga/Kconfig"
1021 source "arch/arm/mach-spear/Kconfig"
1023 source "arch/arm/mach-sti/Kconfig"
1025 source "arch/arm/mach-s3c24xx/Kconfig"
1027 source "arch/arm/mach-s3c64xx/Kconfig"
1029 source "arch/arm/mach-s5p64x0/Kconfig"
1031 source "arch/arm/mach-s5pc100/Kconfig"
1033 source "arch/arm/mach-s5pv210/Kconfig"
1035 source "arch/arm/mach-exynos/Kconfig"
1037 source "arch/arm/mach-shmobile/Kconfig"
1039 source "arch/arm/mach-sunxi/Kconfig"
1041 source "arch/arm/mach-prima2/Kconfig"
1043 source "arch/arm/mach-tegra/Kconfig"
1045 source "arch/arm/mach-u300/Kconfig"
1047 source "arch/arm/mach-ux500/Kconfig"
1049 source "arch/arm/mach-versatile/Kconfig"
1051 source "arch/arm/mach-vexpress/Kconfig"
1052 source "arch/arm/plat-versatile/Kconfig"
1054 source "arch/arm/mach-virt/Kconfig"
1056 source "arch/arm/mach-vt8500/Kconfig"
1058 source "arch/arm/mach-w90x900/Kconfig"
1060 source "arch/arm/mach-zynq/Kconfig"
1062 # Definitions to make life easier
1068 select GENERIC_CLOCKEVENTS
1074 select GENERIC_IRQ_CHIP
1077 config PLAT_ORION_LEGACY
1084 config PLAT_VERSATILE
1087 config ARM_TIMER_SP804
1090 select CLKSRC_OF if OF
1092 source "arch/arm/firmware/Kconfig"
1094 source arch/arm/mm/Kconfig
1098 default 16 if ARCH_EP93XX
1102 bool "Enable iWMMXt support" if !CPU_PJ4
1103 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1104 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1106 Enable support for iWMMXt context switching at run time if
1107 running on a CPU that supports it.
1109 config MULTI_IRQ_HANDLER
1112 Allow each machine to specify it's own IRQ handler at run time.
1115 source "arch/arm/Kconfig-nommu"
1118 config PJ4B_ERRATA_4742
1119 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1120 depends on CPU_PJ4B && MACH_ARMADA_370
1123 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1124 Event (WFE) IDLE states, a specific timing sensitivity exists between
1125 the retiring WFI/WFE instructions and the newly issued subsequent
1126 instructions. This sensitivity can result in a CPU hang scenario.
1128 The software must insert either a Data Synchronization Barrier (DSB)
1129 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1132 config ARM_ERRATA_326103
1133 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1136 Executing a SWP instruction to read-only memory does not set bit 11
1137 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1138 treat the access as a read, preventing a COW from occurring and
1139 causing the faulting task to livelock.
1141 config ARM_ERRATA_411920
1142 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1143 depends on CPU_V6 || CPU_V6K
1145 Invalidation of the Instruction Cache operation can
1146 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1147 It does not affect the MPCore. This option enables the ARM Ltd.
1148 recommended workaround.
1150 config ARM_ERRATA_430973
1151 bool "ARM errata: Stale prediction on replaced interworking branch"
1154 This option enables the workaround for the 430973 Cortex-A8
1155 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1156 interworking branch is replaced with another code sequence at the
1157 same virtual address, whether due to self-modifying code or virtual
1158 to physical address re-mapping, Cortex-A8 does not recover from the
1159 stale interworking branch prediction. This results in Cortex-A8
1160 executing the new code sequence in the incorrect ARM or Thumb state.
1161 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1162 and also flushes the branch target cache at every context switch.
1163 Note that setting specific bits in the ACTLR register may not be
1164 available in non-secure mode.
1166 config ARM_ERRATA_458693
1167 bool "ARM errata: Processor deadlock when a false hazard is created"
1169 depends on !ARCH_MULTIPLATFORM
1171 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1172 erratum. For very specific sequences of memory operations, it is
1173 possible for a hazard condition intended for a cache line to instead
1174 be incorrectly associated with a different cache line. This false
1175 hazard might then cause a processor deadlock. The workaround enables
1176 the L1 caching of the NEON accesses and disables the PLD instruction
1177 in the ACTLR register. Note that setting specific bits in the ACTLR
1178 register may not be available in non-secure mode.
1180 config ARM_ERRATA_460075
1181 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1183 depends on !ARCH_MULTIPLATFORM
1185 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1186 erratum. Any asynchronous access to the L2 cache may encounter a
1187 situation in which recent store transactions to the L2 cache are lost
1188 and overwritten with stale memory contents from external memory. The
1189 workaround disables the write-allocate mode for the L2 cache via the
1190 ACTLR register. Note that setting specific bits in the ACTLR register
1191 may not be available in non-secure mode.
1193 config ARM_ERRATA_742230
1194 bool "ARM errata: DMB operation may be faulty"
1195 depends on CPU_V7 && SMP
1196 depends on !ARCH_MULTIPLATFORM
1198 This option enables the workaround for the 742230 Cortex-A9
1199 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1200 between two write operations may not ensure the correct visibility
1201 ordering of the two writes. This workaround sets a specific bit in
1202 the diagnostic register of the Cortex-A9 which causes the DMB
1203 instruction to behave as a DSB, ensuring the correct behaviour of
1206 config ARM_ERRATA_742231
1207 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1208 depends on CPU_V7 && SMP
1209 depends on !ARCH_MULTIPLATFORM
1211 This option enables the workaround for the 742231 Cortex-A9
1212 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1213 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1214 accessing some data located in the same cache line, may get corrupted
1215 data due to bad handling of the address hazard when the line gets
1216 replaced from one of the CPUs at the same time as another CPU is
1217 accessing it. This workaround sets specific bits in the diagnostic
1218 register of the Cortex-A9 which reduces the linefill issuing
1219 capabilities of the processor.
1221 config PL310_ERRATA_588369
1222 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1223 depends on CACHE_L2X0
1225 The PL310 L2 cache controller implements three types of Clean &
1226 Invalidate maintenance operations: by Physical Address
1227 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1228 They are architecturally defined to behave as the execution of a
1229 clean operation followed immediately by an invalidate operation,
1230 both performing to the same memory location. This functionality
1231 is not correctly implemented in PL310 as clean lines are not
1232 invalidated as a result of these operations.
1234 config ARM_ERRATA_643719
1235 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1236 depends on CPU_V7 && SMP
1238 This option enables the workaround for the 643719 Cortex-A9 (prior to
1239 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1240 register returns zero when it should return one. The workaround
1241 corrects this value, ensuring cache maintenance operations which use
1242 it behave as intended and avoiding data corruption.
1244 config ARM_ERRATA_720789
1245 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1248 This option enables the workaround for the 720789 Cortex-A9 (prior to
1249 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1250 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1251 As a consequence of this erratum, some TLB entries which should be
1252 invalidated are not, resulting in an incoherency in the system page
1253 tables. The workaround changes the TLB flushing routines to invalidate
1254 entries regardless of the ASID.
1256 config PL310_ERRATA_727915
1257 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1258 depends on CACHE_L2X0
1260 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1261 operation (offset 0x7FC). This operation runs in background so that
1262 PL310 can handle normal accesses while it is in progress. Under very
1263 rare circumstances, due to this erratum, write data can be lost when
1264 PL310 treats a cacheable write transaction during a Clean &
1265 Invalidate by Way operation.
1267 config ARM_ERRATA_743622
1268 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1270 depends on !ARCH_MULTIPLATFORM
1272 This option enables the workaround for the 743622 Cortex-A9
1273 (r2p*) erratum. Under very rare conditions, a faulty
1274 optimisation in the Cortex-A9 Store Buffer may lead to data
1275 corruption. This workaround sets a specific bit in the diagnostic
1276 register of the Cortex-A9 which disables the Store Buffer
1277 optimisation, preventing the defect from occurring. This has no
1278 visible impact on the overall performance or power consumption of the
1281 config ARM_ERRATA_751472
1282 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1284 depends on !ARCH_MULTIPLATFORM
1286 This option enables the workaround for the 751472 Cortex-A9 (prior
1287 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1288 completion of a following broadcasted operation if the second
1289 operation is received by a CPU before the ICIALLUIS has completed,
1290 potentially leading to corrupted entries in the cache or TLB.
1292 config PL310_ERRATA_753970
1293 bool "PL310 errata: cache sync operation may be faulty"
1294 depends on CACHE_PL310
1296 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1298 Under some condition the effect of cache sync operation on
1299 the store buffer still remains when the operation completes.
1300 This means that the store buffer is always asked to drain and
1301 this prevents it from merging any further writes. The workaround
1302 is to replace the normal offset of cache sync operation (0x730)
1303 by another offset targeting an unmapped PL310 register 0x740.
1304 This has the same effect as the cache sync operation: store buffer
1305 drain and waiting for all buffers empty.
1307 config ARM_ERRATA_754322
1308 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1311 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1312 r3p*) erratum. A speculative memory access may cause a page table walk
1313 which starts prior to an ASID switch but completes afterwards. This
1314 can populate the micro-TLB with a stale entry which may be hit with
1315 the new ASID. This workaround places two dsb instructions in the mm
1316 switching code so that no page table walks can cross the ASID switch.
1318 config ARM_ERRATA_754327
1319 bool "ARM errata: no automatic Store Buffer drain"
1320 depends on CPU_V7 && SMP
1322 This option enables the workaround for the 754327 Cortex-A9 (prior to
1323 r2p0) erratum. The Store Buffer does not have any automatic draining
1324 mechanism and therefore a livelock may occur if an external agent
1325 continuously polls a memory location waiting to observe an update.
1326 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1327 written polling loops from denying visibility of updates to memory.
1329 config ARM_ERRATA_364296
1330 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1333 This options enables the workaround for the 364296 ARM1136
1334 r0p2 erratum (possible cache data corruption with
1335 hit-under-miss enabled). It sets the undocumented bit 31 in
1336 the auxiliary control register and the FI bit in the control
1337 register, thus disabling hit-under-miss without putting the
1338 processor into full low interrupt latency mode. ARM11MPCore
1341 config ARM_ERRATA_764369
1342 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1343 depends on CPU_V7 && SMP
1345 This option enables the workaround for erratum 764369
1346 affecting Cortex-A9 MPCore with two or more processors (all
1347 current revisions). Under certain timing circumstances, a data
1348 cache line maintenance operation by MVA targeting an Inner
1349 Shareable memory region may fail to proceed up to either the
1350 Point of Coherency or to the Point of Unification of the
1351 system. This workaround adds a DSB instruction before the
1352 relevant cache maintenance functions and sets a specific bit
1353 in the diagnostic control register of the SCU.
1355 config PL310_ERRATA_769419
1356 bool "PL310 errata: no automatic Store Buffer drain"
1357 depends on CACHE_L2X0
1359 On revisions of the PL310 prior to r3p2, the Store Buffer does
1360 not automatically drain. This can cause normal, non-cacheable
1361 writes to be retained when the memory system is idle, leading
1362 to suboptimal I/O performance for drivers using coherent DMA.
1363 This option adds a write barrier to the cpu_idle loop so that,
1364 on systems with an outer cache, the store buffer is drained
1367 config ARM_ERRATA_775420
1368 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1371 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1372 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1373 operation aborts with MMU exception, it might cause the processor
1374 to deadlock. This workaround puts DSB before executing ISB if
1375 an abort may occur on cache maintenance.
1377 config ARM_ERRATA_798181
1378 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1379 depends on CPU_V7 && SMP
1381 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1382 adequately shooting down all use of the old entries. This
1383 option enables the Linux kernel workaround for this erratum
1384 which sends an IPI to the CPUs that are running the same ASID
1385 as the one being invalidated.
1387 config ARM_ERRATA_773022
1388 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1391 This option enables the workaround for the 773022 Cortex-A15
1392 (up to r0p4) erratum. In certain rare sequences of code, the
1393 loop buffer may deliver incorrect instructions. This
1394 workaround disables the loop buffer to avoid the erratum.
1398 source "arch/arm/common/Kconfig"
1408 Find out whether you have ISA slots on your motherboard. ISA is the
1409 name of a bus system, i.e. the way the CPU talks to the other stuff
1410 inside your box. Other bus systems are PCI, EISA, MicroChannel
1411 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1412 newer boards don't support it. If you have ISA, say Y, otherwise N.
1414 # Select ISA DMA controller support
1419 # Select ISA DMA interface
1424 bool "PCI support" if MIGHT_HAVE_PCI
1426 Find out whether you have a PCI motherboard. PCI is the name of a
1427 bus system, i.e. the way the CPU talks to the other stuff inside
1428 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1429 VESA. If you have PCI, say Y, otherwise N.
1435 config PCI_NANOENGINE
1436 bool "BSE nanoEngine PCI support"
1437 depends on SA1100_NANOENGINE
1439 Enable PCI on the BSE nanoEngine board.
1444 config PCI_HOST_ITE8152
1446 depends on PCI && MACH_ARMCORE
1450 source "drivers/pci/Kconfig"
1451 source "drivers/pci/pcie/Kconfig"
1453 source "drivers/pcmcia/Kconfig"
1457 menu "Kernel Features"
1462 This option should be selected by machines which have an SMP-
1465 The only effect of this option is to make the SMP-related
1466 options available to the user for configuration.
1469 bool "Symmetric Multi-Processing"
1470 depends on CPU_V6K || CPU_V7
1471 depends on GENERIC_CLOCKEVENTS
1473 depends on MMU || ARM_MPU
1475 This enables support for systems with more than one CPU. If you have
1476 a system with only one CPU, say N. If you have a system with more
1477 than one CPU, say Y.
1479 If you say N here, the kernel will run on uni- and multiprocessor
1480 machines, but will use only one CPU of a multiprocessor machine. If
1481 you say Y here, the kernel will run on many, but not all,
1482 uniprocessor machines. On a uniprocessor machine, the kernel
1483 will run faster if you say N here.
1485 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1486 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1487 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1489 If you don't know what to do here, say N.
1492 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1493 depends on SMP && !XIP_KERNEL && MMU
1496 SMP kernels contain instructions which fail on non-SMP processors.
1497 Enabling this option allows the kernel to modify itself to make
1498 these instructions safe. Disabling it allows about 1K of space
1501 If you don't know what to do here, say Y.
1503 config ARM_CPU_TOPOLOGY
1504 bool "Support cpu topology definition"
1505 depends on SMP && CPU_V7
1508 Support ARM cpu topology definition. The MPIDR register defines
1509 affinity between processors which is then used to describe the cpu
1510 topology of an ARM System.
1513 bool "Multi-core scheduler support"
1514 depends on ARM_CPU_TOPOLOGY
1516 Multi-core scheduler support improves the CPU scheduler's decision
1517 making when dealing with multi-core CPU chips at a cost of slightly
1518 increased overhead in some places. If unsure say N here.
1521 bool "SMT scheduler support"
1522 depends on ARM_CPU_TOPOLOGY
1524 Improves the CPU scheduler's decision making when dealing with
1525 MultiThreading at a cost of slightly increased overhead in some
1526 places. If unsure say N here.
1531 This option enables support for the ARM system coherency unit
1533 config HAVE_ARM_ARCH_TIMER
1534 bool "Architected timer support"
1536 select ARM_ARCH_TIMER
1537 select GENERIC_CLOCKEVENTS
1539 This option enables support for the ARM architected timer
1544 select CLKSRC_OF if OF
1546 This options enables support for the ARM timer and watchdog unit
1549 bool "Multi-Cluster Power Management"
1550 depends on CPU_V7 && SMP
1552 This option provides the common power management infrastructure
1553 for (multi-)cluster based systems, such as big.LITTLE based
1557 bool "big.LITTLE support (Experimental)"
1558 depends on CPU_V7 && SMP
1561 This option enables support selections for the big.LITTLE
1562 system architecture.
1565 bool "big.LITTLE switcher support"
1566 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1568 select ARM_CPU_SUSPEND
1570 The big.LITTLE "switcher" provides the core functionality to
1571 transparently handle transition between a cluster of A15's
1572 and a cluster of A7's in a big.LITTLE system.
1574 config BL_SWITCHER_DUMMY_IF
1575 tristate "Simple big.LITTLE switcher user interface"
1576 depends on BL_SWITCHER && DEBUG_KERNEL
1578 This is a simple and dummy char dev interface to control
1579 the big.LITTLE switcher core code. It is meant for
1580 debugging purposes only.
1583 prompt "Memory split"
1587 Select the desired split between kernel and user memory.
1589 If you are not absolutely sure what you are doing, leave this
1593 bool "3G/1G user/kernel split"
1595 bool "2G/2G user/kernel split"
1597 bool "1G/3G user/kernel split"
1602 default PHYS_OFFSET if !MMU
1603 default 0x40000000 if VMSPLIT_1G
1604 default 0x80000000 if VMSPLIT_2G
1608 int "Maximum number of CPUs (2-32)"
1614 bool "Support for hot-pluggable CPUs"
1617 Say Y here to experiment with turning CPUs off and on. CPUs
1618 can be controlled through /sys/devices/system/cpu.
1621 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1624 Say Y here if you want Linux to communicate with system firmware
1625 implementing the PSCI specification for CPU-centric power
1626 management operations described in ARM document number ARM DEN
1627 0022A ("Power State Coordination Interface System Software on
1630 # The GPIO number here must be sorted by descending number. In case of
1631 # a multiplatform kernel, we just want the highest value required by the
1632 # selected platforms.
1635 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1636 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1637 default 392 if ARCH_U8500
1638 default 352 if ARCH_VT8500
1639 default 288 if ARCH_SUNXI
1640 default 264 if MACH_H4700
1643 Maximum number of GPIOs in the system.
1645 If unsure, leave the default value.
1647 source kernel/Kconfig.preempt
1651 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1652 ARCH_S5PV210 || ARCH_EXYNOS4
1653 default AT91_TIMER_HZ if ARCH_AT91
1654 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1658 depends on HZ_FIXED = 0
1659 prompt "Timer frequency"
1683 default HZ_FIXED if HZ_FIXED != 0
1684 default 100 if HZ_100
1685 default 200 if HZ_200
1686 default 250 if HZ_250
1687 default 300 if HZ_300
1688 default 500 if HZ_500
1692 def_bool HIGH_RES_TIMERS
1694 config THUMB2_KERNEL
1695 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1696 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1697 default y if CPU_THUMBONLY
1699 select ARM_ASM_UNIFIED
1702 By enabling this option, the kernel will be compiled in
1703 Thumb-2 mode. A compiler/assembler that understand the unified
1704 ARM-Thumb syntax is needed.
1708 config THUMB2_AVOID_R_ARM_THM_JUMP11
1709 bool "Work around buggy Thumb-2 short branch relocations in gas"
1710 depends on THUMB2_KERNEL && MODULES
1713 Various binutils versions can resolve Thumb-2 branches to
1714 locally-defined, preemptible global symbols as short-range "b.n"
1715 branch instructions.
1717 This is a problem, because there's no guarantee the final
1718 destination of the symbol, or any candidate locations for a
1719 trampoline, are within range of the branch. For this reason, the
1720 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1721 relocation in modules at all, and it makes little sense to add
1724 The symptom is that the kernel fails with an "unsupported
1725 relocation" error when loading some modules.
1727 Until fixed tools are available, passing
1728 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1729 code which hits this problem, at the cost of a bit of extra runtime
1730 stack usage in some cases.
1732 The problem is described in more detail at:
1733 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1735 Only Thumb-2 kernels are affected.
1737 Unless you are sure your tools don't have this problem, say Y.
1739 config ARM_ASM_UNIFIED
1743 bool "Use the ARM EABI to compile the kernel"
1745 This option allows for the kernel to be compiled using the latest
1746 ARM ABI (aka EABI). This is only useful if you are using a user
1747 space environment that is also compiled with EABI.
1749 Since there are major incompatibilities between the legacy ABI and
1750 EABI, especially with regard to structure member alignment, this
1751 option also changes the kernel syscall calling convention to
1752 disambiguate both ABIs and allow for backward compatibility support
1753 (selected with CONFIG_OABI_COMPAT).
1755 To use this you need GCC version 4.0.0 or later.
1758 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1759 depends on AEABI && !THUMB2_KERNEL
1761 This option preserves the old syscall interface along with the
1762 new (ARM EABI) one. It also provides a compatibility layer to
1763 intercept syscalls that have structure arguments which layout
1764 in memory differs between the legacy ABI and the new ARM EABI
1765 (only for non "thumb" binaries). This option adds a tiny
1766 overhead to all syscalls and produces a slightly larger kernel.
1768 The seccomp filter system will not be available when this is
1769 selected, since there is no way yet to sensibly distinguish
1770 between calling conventions during filtering.
1772 If you know you'll be using only pure EABI user space then you
1773 can say N here. If this option is not selected and you attempt
1774 to execute a legacy ABI binary then the result will be
1775 UNPREDICTABLE (in fact it can be predicted that it won't work
1776 at all). If in doubt say N.
1778 config ARCH_HAS_HOLES_MEMORYMODEL
1781 config ARCH_SPARSEMEM_ENABLE
1784 config ARCH_SPARSEMEM_DEFAULT
1785 def_bool ARCH_SPARSEMEM_ENABLE
1787 config ARCH_SELECT_MEMORY_MODEL
1788 def_bool ARCH_SPARSEMEM_ENABLE
1790 config HAVE_ARCH_PFN_VALID
1791 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1794 bool "High Memory Support"
1797 The address space of ARM processors is only 4 Gigabytes large
1798 and it has to accommodate user address space, kernel address
1799 space as well as some memory mapped IO. That means that, if you
1800 have a large amount of physical memory and/or IO, not all of the
1801 memory can be "permanently mapped" by the kernel. The physical
1802 memory that is not permanently mapped is called "high memory".
1804 Depending on the selected kernel/user memory split, minimum
1805 vmalloc space and actual amount of RAM, you may not need this
1806 option which should result in a slightly faster kernel.
1811 bool "Allocate 2nd-level pagetables from highmem"
1814 config HW_PERF_EVENTS
1815 bool "Enable hardware performance counter support for perf events"
1816 depends on PERF_EVENTS
1819 Enable hardware performance counter support for perf events. If
1820 disabled, perf events will use software events only.
1822 config SYS_SUPPORTS_HUGETLBFS
1826 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1830 config ARCH_WANT_GENERAL_HUGETLB
1835 config FORCE_MAX_ZONEORDER
1836 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1837 range 11 64 if ARCH_SHMOBILE_LEGACY
1838 default "12" if SOC_AM33XX
1839 default "9" if SA1111 || ARCH_EFM32
1842 The kernel memory allocator divides physically contiguous memory
1843 blocks into "zones", where each zone is a power of two number of
1844 pages. This option selects the largest power of two that the kernel
1845 keeps in the memory allocator. If you need to allocate very large
1846 blocks of physically contiguous memory, then you may need to
1847 increase this value.
1849 This config option is actually maximum order plus one. For example,
1850 a value of 11 means that the largest free memory block is 2^10 pages.
1852 config ALIGNMENT_TRAP
1854 depends on CPU_CP15_MMU
1855 default y if !ARCH_EBSA110
1856 select HAVE_PROC_CPU if PROC_FS
1858 ARM processors cannot fetch/store information which is not
1859 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1860 address divisible by 4. On 32-bit ARM processors, these non-aligned
1861 fetch/store instructions will be emulated in software if you say
1862 here, which has a severe performance impact. This is necessary for
1863 correct operation of some network protocols. With an IP-only
1864 configuration it is safe to say N, otherwise say Y.
1866 config UACCESS_WITH_MEMCPY
1867 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1869 default y if CPU_FEROCEON
1871 Implement faster copy_to_user and clear_user methods for CPU
1872 cores where a 8-word STM instruction give significantly higher
1873 memory write throughput than a sequence of individual 32bit stores.
1875 A possible side effect is a slight increase in scheduling latency
1876 between threads sharing the same address space if they invoke
1877 such copy operations with large buffers.
1879 However, if the CPU data cache is using a write-allocate mode,
1880 this option is unlikely to provide any performance gain.
1884 prompt "Enable seccomp to safely compute untrusted bytecode"
1886 This kernel feature is useful for number crunching applications
1887 that may need to compute untrusted bytecode during their
1888 execution. By using pipes or other transports made available to
1889 the process as file descriptors supporting the read/write
1890 syscalls, it's possible to isolate those applications in
1891 their own address space using seccomp. Once seccomp is
1892 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1893 and the task is only allowed to execute a few safe syscalls
1894 defined by each seccomp mode.
1907 bool "Xen guest support on ARM (EXPERIMENTAL)"
1908 depends on ARM && AEABI && OF
1909 depends on CPU_V7 && !CPU_V6
1910 depends on !GENERIC_ATOMIC64
1913 select ARCH_DMA_ADDR_T_64BIT
1915 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1922 bool "Flattened Device Tree support"
1925 select OF_EARLY_FLATTREE
1927 Include support for flattened device tree machine descriptions.
1930 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1933 This is the traditional way of passing data to the kernel at boot
1934 time. If you are solely relying on the flattened device tree (or
1935 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1936 to remove ATAGS support from your kernel binary. If unsure,
1939 config DEPRECATED_PARAM_STRUCT
1940 bool "Provide old way to pass kernel parameters"
1943 This was deprecated in 2001 and announced to live on for 5 years.
1944 Some old boot loaders still use this way.
1946 # Compressed boot loader in ROM. Yes, we really want to ask about
1947 # TEXT and BSS so we preserve their values in the config files.
1948 config ZBOOT_ROM_TEXT
1949 hex "Compressed ROM boot loader base address"
1952 The physical address at which the ROM-able zImage is to be
1953 placed in the target. Platforms which normally make use of
1954 ROM-able zImage formats normally set this to a suitable
1955 value in their defconfig file.
1957 If ZBOOT_ROM is not enabled, this has no effect.
1959 config ZBOOT_ROM_BSS
1960 hex "Compressed ROM boot loader BSS address"
1963 The base address of an area of read/write memory in the target
1964 for the ROM-able zImage which must be available while the
1965 decompressor is running. It must be large enough to hold the
1966 entire decompressed kernel plus an additional 128 KiB.
1967 Platforms which normally make use of ROM-able zImage formats
1968 normally set this to a suitable value in their defconfig file.
1970 If ZBOOT_ROM is not enabled, this has no effect.
1973 bool "Compressed boot loader in ROM/flash"
1974 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1975 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1977 Say Y here if you intend to execute your compressed kernel image
1978 (zImage) directly from ROM or flash. If unsure, say N.
1981 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1982 depends on ZBOOT_ROM && ARCH_SH7372
1983 default ZBOOT_ROM_NONE
1985 Include experimental SD/MMC loading code in the ROM-able zImage.
1986 With this enabled it is possible to write the ROM-able zImage
1987 kernel image to an MMC or SD card and boot the kernel straight
1988 from the reset vector. At reset the processor Mask ROM will load
1989 the first part of the ROM-able zImage which in turn loads the
1990 rest the kernel image to RAM.
1992 config ZBOOT_ROM_NONE
1993 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1995 Do not load image from SD or MMC
1997 config ZBOOT_ROM_MMCIF
1998 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
2000 Load image from MMCIF hardware block.
2002 config ZBOOT_ROM_SH_MOBILE_SDHI
2003 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2005 Load image from SDHI hardware block
2009 config ARM_APPENDED_DTB
2010 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2013 With this option, the boot code will look for a device tree binary
2014 (DTB) appended to zImage
2015 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2017 This is meant as a backward compatibility convenience for those
2018 systems with a bootloader that can't be upgraded to accommodate
2019 the documented boot protocol using a device tree.
2021 Beware that there is very little in terms of protection against
2022 this option being confused by leftover garbage in memory that might
2023 look like a DTB header after a reboot if no actual DTB is appended
2024 to zImage. Do not leave this option active in a production kernel
2025 if you don't intend to always append a DTB. Proper passing of the
2026 location into r2 of a bootloader provided DTB is always preferable
2029 config ARM_ATAG_DTB_COMPAT
2030 bool "Supplement the appended DTB with traditional ATAG information"
2031 depends on ARM_APPENDED_DTB
2033 Some old bootloaders can't be updated to a DTB capable one, yet
2034 they provide ATAGs with memory configuration, the ramdisk address,
2035 the kernel cmdline string, etc. Such information is dynamically
2036 provided by the bootloader and can't always be stored in a static
2037 DTB. To allow a device tree enabled kernel to be used with such
2038 bootloaders, this option allows zImage to extract the information
2039 from the ATAG list and store it at run time into the appended DTB.
2042 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2043 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2045 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2046 bool "Use bootloader kernel arguments if available"
2048 Uses the command-line options passed by the boot loader instead of
2049 the device tree bootargs property. If the boot loader doesn't provide
2050 any, the device tree bootargs property will be used.
2052 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2053 bool "Extend with bootloader kernel arguments"
2055 The command-line arguments provided by the boot loader will be
2056 appended to the the device tree bootargs property.
2061 string "Default kernel command string"
2064 On some architectures (EBSA110 and CATS), there is currently no way
2065 for the boot loader to pass arguments to the kernel. For these
2066 architectures, you should supply some command-line options at build
2067 time by entering them here. As a minimum, you should specify the
2068 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2071 prompt "Kernel command line type" if CMDLINE != ""
2072 default CMDLINE_FROM_BOOTLOADER
2075 config CMDLINE_FROM_BOOTLOADER
2076 bool "Use bootloader kernel arguments if available"
2078 Uses the command-line options passed by the boot loader. If
2079 the boot loader doesn't provide any, the default kernel command
2080 string provided in CMDLINE will be used.
2082 config CMDLINE_EXTEND
2083 bool "Extend bootloader kernel arguments"
2085 The command-line arguments provided by the boot loader will be
2086 appended to the default kernel command string.
2088 config CMDLINE_FORCE
2089 bool "Always use the default kernel command string"
2091 Always use the default kernel command string, even if the boot
2092 loader passes other arguments to the kernel.
2093 This is useful if you cannot or don't want to change the
2094 command-line options your boot loader passes to the kernel.
2098 bool "Kernel Execute-In-Place from ROM"
2099 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2101 Execute-In-Place allows the kernel to run from non-volatile storage
2102 directly addressable by the CPU, such as NOR flash. This saves RAM
2103 space since the text section of the kernel is not loaded from flash
2104 to RAM. Read-write sections, such as the data section and stack,
2105 are still copied to RAM. The XIP kernel is not compressed since
2106 it has to run directly from flash, so it will take more space to
2107 store it. The flash address used to link the kernel object files,
2108 and for storing it, is configuration dependent. Therefore, if you
2109 say Y here, you must know the proper physical address where to
2110 store the kernel image depending on your own flash memory usage.
2112 Also note that the make target becomes "make xipImage" rather than
2113 "make zImage" or "make Image". The final kernel binary to put in
2114 ROM memory will be arch/arm/boot/xipImage.
2118 config XIP_PHYS_ADDR
2119 hex "XIP Kernel Physical Location"
2120 depends on XIP_KERNEL
2121 default "0x00080000"
2123 This is the physical address in your flash memory the kernel will
2124 be linked for and stored to. This address is dependent on your
2128 bool "Kexec system call (EXPERIMENTAL)"
2129 depends on (!SMP || PM_SLEEP_SMP)
2131 kexec is a system call that implements the ability to shutdown your
2132 current kernel, and to start another kernel. It is like a reboot
2133 but it is independent of the system firmware. And like a reboot
2134 you can start any kernel with it, not just Linux.
2136 It is an ongoing process to be certain the hardware in a machine
2137 is properly shutdown, so do not be surprised if this code does not
2138 initially work for you.
2141 bool "Export atags in procfs"
2142 depends on ATAGS && KEXEC
2145 Should the atags used to boot the kernel be exported in an "atags"
2146 file in procfs. Useful with kexec.
2149 bool "Build kdump crash kernel (EXPERIMENTAL)"
2151 Generate crash dump after being started by kexec. This should
2152 be normally only set in special crash dump kernels which are
2153 loaded in the main kernel with kexec-tools into a specially
2154 reserved region and then later executed after a crash by
2155 kdump/kexec. The crash dump kernel must be compiled to a
2156 memory address not used by the main kernel
2158 For more details see Documentation/kdump/kdump.txt
2160 config AUTO_ZRELADDR
2161 bool "Auto calculation of the decompressed kernel image address"
2163 ZRELADDR is the physical address where the decompressed kernel
2164 image will be placed. If AUTO_ZRELADDR is selected, the address
2165 will be determined at run-time by masking the current IP with
2166 0xf8000000. This assumes the zImage being placed in the first 128MB
2167 from start of memory.
2171 menu "CPU Power Management"
2174 source "drivers/cpufreq/Kconfig"
2177 source "drivers/cpuidle/Kconfig"
2181 menu "Floating point emulation"
2183 comment "At least one emulation must be selected"
2186 bool "NWFPE math emulation"
2187 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2189 Say Y to include the NWFPE floating point emulator in the kernel.
2190 This is necessary to run most binaries. Linux does not currently
2191 support floating point hardware so you need to say Y here even if
2192 your machine has an FPA or floating point co-processor podule.
2194 You may say N here if you are going to load the Acorn FPEmulator
2195 early in the bootup.
2198 bool "Support extended precision"
2199 depends on FPE_NWFPE
2201 Say Y to include 80-bit support in the kernel floating-point
2202 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2203 Note that gcc does not generate 80-bit operations by default,
2204 so in most cases this option only enlarges the size of the
2205 floating point emulator without any good reason.
2207 You almost surely want to say N here.
2210 bool "FastFPE math emulation (EXPERIMENTAL)"
2211 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2213 Say Y here to include the FAST floating point emulator in the kernel.
2214 This is an experimental much faster emulator which now also has full
2215 precision for the mantissa. It does not support any exceptions.
2216 It is very simple, and approximately 3-6 times faster than NWFPE.
2218 It should be sufficient for most programs. It may be not suitable
2219 for scientific calculations, but you have to check this for yourself.
2220 If you do not feel you need a faster FP emulation you should better
2224 bool "VFP-format floating point maths"
2225 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2227 Say Y to include VFP support code in the kernel. This is needed
2228 if your hardware includes a VFP unit.
2230 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2231 release notes and additional status information.
2233 Say N if your target does not have VFP hardware.
2241 bool "Advanced SIMD (NEON) Extension support"
2242 depends on VFPv3 && CPU_V7
2244 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2247 config KERNEL_MODE_NEON
2248 bool "Support for NEON in kernel mode"
2249 depends on NEON && AEABI
2251 Say Y to include support for NEON in kernel mode.
2255 menu "Userspace binary formats"
2257 source "fs/Kconfig.binfmt"
2260 tristate "RISC OS personality"
2263 Say Y here to include the kernel code necessary if you want to run
2264 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2265 experimental; if this sounds frightening, say N and sleep in peace.
2266 You can also say M here to compile this support as a module (which
2267 will be called arthur).
2271 menu "Power management options"
2273 source "kernel/power/Kconfig"
2275 config ARCH_SUSPEND_POSSIBLE
2276 depends on !ARCH_S5PC100
2277 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2278 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2281 config ARM_CPU_SUSPEND
2286 source "net/Kconfig"
2288 source "drivers/Kconfig"
2292 source "arch/arm/Kconfig.debug"
2294 source "security/Kconfig"
2296 source "crypto/Kconfig"
2298 source "lib/Kconfig"
2300 source "arch/arm/kvm/Kconfig"