4 select ARCH_CLOCKSOURCE_DATA
5 select ARCH_HAS_DEBUG_VIRTUAL
6 select ARCH_HAS_DEVMEM_IS_ALLOWED
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_SET_MEMORY
9 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
10 select ARCH_HAS_STRICT_MODULE_RWX if MMU
11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
12 select ARCH_HAVE_CUSTOM_GPIO_H
13 select ARCH_HAS_GCOV_PROFILE_ALL
14 select ARCH_MIGHT_HAVE_PC_PARPORT
15 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
16 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
17 select ARCH_SUPPORTS_ATOMIC_RMW
18 select ARCH_USE_BUILTIN_BSWAP
19 select ARCH_USE_CMPXCHG_LOCKREF
20 select ARCH_WANT_IPC_PARSE_VERSION
21 select BUILDTIME_EXTABLE_SORT if MMU
22 select CLONE_BACKWARDS
23 select CPU_PM if (SUSPEND || CPU_IDLE)
24 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
26 select EDAC_ATOMIC_SCRUB
27 select GENERIC_ALLOCATOR
28 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
29 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
30 select GENERIC_EARLY_IOREMAP
31 select GENERIC_IDLE_POLL_SETUP
32 select GENERIC_IRQ_PROBE
33 select GENERIC_IRQ_SHOW
34 select GENERIC_IRQ_SHOW_LEVEL
35 select GENERIC_PCI_IOMAP
36 select GENERIC_SCHED_CLOCK
37 select GENERIC_SMP_IDLE_THREAD
38 select GENERIC_STRNCPY_FROM_USER
39 select GENERIC_STRNLEN_USER
40 select HANDLE_DOMAIN_IRQ
41 select HARDIRQS_SW_RESEND
42 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
43 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
44 select HAVE_ARCH_HARDENED_USERCOPY
45 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
46 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
47 select HAVE_ARCH_MMAP_RND_BITS if MMU
48 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
49 select HAVE_ARCH_TRACEHOOK
50 select HAVE_ARM_SMCCC if CPU_V7
52 select HAVE_CC_STACKPROTECTOR
53 select HAVE_CONTEXT_TRACKING
54 select HAVE_C_RECORDMCOUNT
55 select HAVE_DEBUG_KMEMLEAK
56 select HAVE_DMA_API_DEBUG
57 select HAVE_DMA_CONTIGUOUS if MMU
58 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
59 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
60 select HAVE_EXIT_THREAD
61 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
62 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
63 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
64 select HAVE_GCC_PLUGINS
65 select HAVE_GENERIC_DMA_COHERENT
66 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
67 select HAVE_IDE if PCI || ISA || PCMCIA
68 select HAVE_IRQ_TIME_ACCOUNTING
69 select HAVE_KERNEL_GZIP
70 select HAVE_KERNEL_LZ4
71 select HAVE_KERNEL_LZMA
72 select HAVE_KERNEL_LZO
74 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
75 select HAVE_KRETPROBES if (HAVE_KPROBES)
77 select HAVE_MOD_ARCH_SPECIFIC
79 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
80 select HAVE_OPTPROBES if !THUMB2_KERNEL
81 select HAVE_PERF_EVENTS
83 select HAVE_PERF_USER_STACK_DUMP
84 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
85 select HAVE_REGS_AND_STACK_ACCESS_API
86 select HAVE_SYSCALL_TRACEPOINTS
88 select HAVE_VIRT_CPU_ACCOUNTING_GEN
89 select IRQ_FORCED_THREADING
90 select MODULES_USE_ELF_REL
92 select OF_EARLY_FLATTREE if OF
93 select OF_RESERVED_MEM if OF
95 select OLD_SIGSUSPEND3
96 select PERF_USE_VMALLOC
98 select SYS_SUPPORTS_APM_EMULATION
99 # Above selects are sorted alphabetically; please add new ones
100 # according to that. Thanks.
102 The ARM series is a line of low-power-consumption RISC chip designs
103 licensed by ARM Ltd and targeted at embedded applications and
104 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
105 manufactured, but legacy ARM-based PC hardware remains popular in
106 Europe. There is an ARM Linux project with a web page at
107 <http://www.arm.linux.org.uk/>.
109 config ARM_HAS_SG_CHAIN
110 select ARCH_HAS_SG_CHAIN
113 config NEED_SG_DMA_LENGTH
116 config ARM_DMA_USE_IOMMU
118 select ARM_HAS_SG_CHAIN
119 select NEED_SG_DMA_LENGTH
123 config ARM_DMA_IOMMU_ALIGNMENT
124 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
128 DMA mapping framework by default aligns all buffers to the smallest
129 PAGE_SIZE order which is greater than or equal to the requested buffer
130 size. This works well for buffers up to a few hundreds kilobytes, but
131 for larger buffers it just a waste of address space. Drivers which has
132 relatively small addressing window (like 64Mib) might run out of
133 virtual space with just a few allocations.
135 With this parameter you can specify the maximum PAGE_SIZE order for
136 DMA IOMMU buffers. Larger buffers will be aligned only to this
137 specified order. The order is expressed as a power of two multiplied
142 config MIGHT_HAVE_PCI
145 config SYS_SUPPORTS_APM_EMULATION
150 select GENERIC_ALLOCATOR
161 The Extended Industry Standard Architecture (EISA) bus was
162 developed as an open alternative to the IBM MicroChannel bus.
164 The EISA bus provided some of the features of the IBM MicroChannel
165 bus while maintaining backward compatibility with cards made for
166 the older ISA bus. The EISA bus saw limited use between 1988 and
167 1995 when it was made obsolete by the PCI bus.
169 Say Y here if you are building a kernel for an EISA-based machine.
176 config STACKTRACE_SUPPORT
180 config LOCKDEP_SUPPORT
184 config TRACE_IRQFLAGS_SUPPORT
188 config RWSEM_XCHGADD_ALGORITHM
192 config ARCH_HAS_ILOG2_U32
195 config ARCH_HAS_ILOG2_U64
198 config ARCH_HAS_BANDGAP
201 config FIX_EARLYCON_MEM
204 config GENERIC_HWEIGHT
208 config GENERIC_CALIBRATE_DELAY
212 config ARCH_MAY_HAVE_PC_FDC
218 config NEED_DMA_MAP_STATE
221 config ARCH_SUPPORTS_UPROBES
224 config ARCH_HAS_DMA_SET_COHERENT_MASK
227 config GENERIC_ISA_DMA
233 config NEED_RET_TO_USER
241 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
242 default DRAM_BASE if REMAP_VECTORS_TO_RAM
245 The base address of exception vectors. This must be two pages
248 config ARM_PATCH_PHYS_VIRT
249 bool "Patch physical to virtual translations at runtime" if EMBEDDED
251 depends on !XIP_KERNEL && MMU
253 Patch phys-to-virt and virt-to-phys translation functions at
254 boot and module load time according to the position of the
255 kernel in system memory.
257 This can only be used with non-XIP MMU kernels where the base
258 of physical memory is at a 16MB boundary.
260 Only disable this option if you know that you do not require
261 this feature (eg, building a kernel for a single machine) and
262 you need to shrink the kernel to the minimal size.
264 config NEED_MACH_IO_H
267 Select this when mach/io.h is required to provide special
268 definitions for this platform. The need for mach/io.h should
269 be avoided when possible.
271 config NEED_MACH_MEMORY_H
274 Select this when mach/memory.h is required to provide special
275 definitions for this platform. The need for mach/memory.h should
276 be avoided when possible.
279 hex "Physical address of main memory" if MMU
280 depends on !ARM_PATCH_PHYS_VIRT
281 default DRAM_BASE if !MMU
282 default 0x00000000 if ARCH_EBSA110 || \
288 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
289 default 0x20000000 if ARCH_S5PV210
290 default 0xc0000000 if ARCH_SA1100
292 Please provide the physical address corresponding to the
293 location of main memory in your system.
299 config PGTABLE_LEVELS
301 default 3 if ARM_LPAE
304 source "init/Kconfig"
306 source "kernel/Kconfig.freezer"
311 bool "MMU-based Paged Memory Management Support"
314 Select if you want MMU-based virtualised addressing space
315 support by paged memory management. If unsure, say 'Y'.
317 config ARCH_MMAP_RND_BITS_MIN
320 config ARCH_MMAP_RND_BITS_MAX
321 default 14 if PAGE_OFFSET=0x40000000
322 default 15 if PAGE_OFFSET=0x80000000
326 # The "ARM system type" choice list is ordered alphabetically by option
327 # text. Please add new entries in the option alphabetic order.
330 prompt "ARM system type"
331 default ARM_SINGLE_ARMV7M if !MMU
332 default ARCH_MULTIPLATFORM if MMU
334 config ARCH_MULTIPLATFORM
335 bool "Allow multiple platforms to be selected"
337 select ARM_HAS_SG_CHAIN
338 select ARM_PATCH_PHYS_VIRT
342 select GENERIC_CLOCKEVENTS
343 select MIGHT_HAVE_PCI
344 select MULTI_IRQ_HANDLER
345 select PCI_DOMAINS if PCI
349 config ARM_SINGLE_ARMV7M
350 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
357 select GENERIC_CLOCKEVENTS
363 bool "Cortina Systems Gemini"
366 select GENERIC_CLOCKEVENTS
369 Support for the Cortina Systems Gemini family SoCs
373 select ARCH_USES_GETTIMEOFFSET
376 select NEED_MACH_IO_H
377 select NEED_MACH_MEMORY_H
380 This is an evaluation board for the StrongARM processor available
381 from Digital. It has limited hardware on-board, including an
382 Ethernet interface, two PCMCIA sockets, two serial ports and a
387 select ARCH_HAS_HOLES_MEMORYMODEL
389 select ARM_PATCH_PHYS_VIRT
395 select GENERIC_CLOCKEVENTS
398 This enables support for the Cirrus EP93xx series of CPUs.
400 config ARCH_FOOTBRIDGE
404 select GENERIC_CLOCKEVENTS
406 select NEED_MACH_IO_H if !MMU
407 select NEED_MACH_MEMORY_H
409 Support for systems based on the DC21285 companion chip
410 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
413 bool "Hilscher NetX based"
417 select GENERIC_CLOCKEVENTS
419 This enables support for systems based on the Hilscher NetX Soc
425 select NEED_MACH_MEMORY_H
426 select NEED_RET_TO_USER
432 Support for Intel's IOP13XX (XScale) family of processors.
440 select NEED_RET_TO_USER
444 Support for Intel's 80219 and IOP32X (XScale) family of
453 select NEED_RET_TO_USER
457 Support for Intel's IOP33X (XScale) family of processors.
462 select ARCH_HAS_DMA_SET_COHERENT_MASK
463 select ARCH_SUPPORTS_BIG_ENDIAN
466 select DMABOUNCE if PCI
467 select GENERIC_CLOCKEVENTS
469 select MIGHT_HAVE_PCI
470 select NEED_MACH_IO_H
471 select USB_EHCI_BIG_ENDIAN_DESC
472 select USB_EHCI_BIG_ENDIAN_MMIO
474 Support for Intel's IXP4XX (XScale) family of processors.
479 select GENERIC_CLOCKEVENTS
481 select MIGHT_HAVE_PCI
482 select MULTI_IRQ_HANDLER
486 select PLAT_ORION_LEGACY
488 select PM_GENERIC_DOMAINS if PM
490 Support for the Marvell Dove SoC 88AP510
493 bool "Micrel/Kendin KS8695"
496 select GENERIC_CLOCKEVENTS
498 select NEED_MACH_MEMORY_H
500 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
501 System-on-Chip devices.
504 bool "Nuvoton W90X900 CPU"
508 select GENERIC_CLOCKEVENTS
511 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
512 At present, the w90x900 has been renamed nuc900, regarding
513 the ARM series product line, you can login the following
514 link address to know more.
516 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
517 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
523 select CLKSRC_LPC32XX
526 select GENERIC_CLOCKEVENTS
528 select MULTI_IRQ_HANDLER
532 Support for the NXP LPC32XX family of processors
535 bool "PXA2xx/PXA3xx-based"
538 select ARM_CPU_SUSPEND if PM
545 select CPU_XSCALE if !CPU_XSC3
546 select GENERIC_CLOCKEVENTS
551 select MULTI_IRQ_HANDLER
555 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
561 select ARCH_MAY_HAVE_PC_FDC
562 select ARCH_SPARSEMEM_ENABLE
563 select ARCH_USES_GETTIMEOFFSET
567 select HAVE_PATA_PLATFORM
569 select NEED_MACH_IO_H
570 select NEED_MACH_MEMORY_H
573 On the Acorn Risc-PC, Linux can support the internal IDE disk and
574 CD-ROM interface, serial and parallel port, and the floppy drive.
579 select ARCH_SPARSEMEM_ENABLE
583 select CLKSRC_OF if OF
586 select GENERIC_CLOCKEVENTS
591 select MULTI_IRQ_HANDLER
592 select NEED_MACH_MEMORY_H
595 Support for StrongARM 11x0 based boards.
598 bool "Samsung S3C24XX SoCs"
601 select CLKSRC_SAMSUNG_PWM
602 select GENERIC_CLOCKEVENTS
605 select HAVE_S3C2410_I2C if I2C
606 select HAVE_S3C2410_WATCHDOG if WATCHDOG
607 select HAVE_S3C_RTC if RTC_CLASS
608 select MULTI_IRQ_HANDLER
609 select NEED_MACH_IO_H
612 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
613 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
614 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
615 Samsung SMDK2410 development board (and derivatives).
619 select ARCH_HAS_HOLES_MEMORYMODEL
622 select GENERIC_ALLOCATOR
623 select GENERIC_CLOCKEVENTS
624 select GENERIC_IRQ_CHIP
630 Support for TI's DaVinci platform.
635 select ARCH_HAS_HOLES_MEMORYMODEL
639 select GENERIC_CLOCKEVENTS
640 select GENERIC_IRQ_CHIP
644 select MULTI_IRQ_HANDLER
645 select NEED_MACH_IO_H if PCCARD
646 select NEED_MACH_MEMORY_H
649 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
653 menu "Multiple platform selection"
654 depends on ARCH_MULTIPLATFORM
656 comment "CPU Core family selection"
659 bool "ARMv4 based platforms (FA526)"
660 depends on !ARCH_MULTI_V6_V7
661 select ARCH_MULTI_V4_V5
664 config ARCH_MULTI_V4T
665 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
666 depends on !ARCH_MULTI_V6_V7
667 select ARCH_MULTI_V4_V5
668 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
669 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
670 CPU_ARM925T || CPU_ARM940T)
673 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
674 depends on !ARCH_MULTI_V6_V7
675 select ARCH_MULTI_V4_V5
676 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
677 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
678 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
680 config ARCH_MULTI_V4_V5
684 bool "ARMv6 based platforms (ARM11)"
685 select ARCH_MULTI_V6_V7
689 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
691 select ARCH_MULTI_V6_V7
695 config ARCH_MULTI_V6_V7
697 select MIGHT_HAVE_CACHE_L2X0
699 config ARCH_MULTI_CPU_AUTO
700 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
706 bool "Dummy Virtual Machine"
707 depends on ARCH_MULTI_V7
710 select ARM_GIC_V2M if PCI
712 select ARM_GIC_V3_ITS if PCI
714 select HAVE_ARM_ARCH_TIMER
717 # This is sorted alphabetically by mach-* pathname. However, plat-*
718 # Kconfigs may be included either alphabetically (according to the
719 # plat- suffix) or along side the corresponding mach-* source.
721 source "arch/arm/mach-mvebu/Kconfig"
723 source "arch/arm/mach-alpine/Kconfig"
725 source "arch/arm/mach-artpec/Kconfig"
727 source "arch/arm/mach-asm9260/Kconfig"
729 source "arch/arm/mach-at91/Kconfig"
731 source "arch/arm/mach-axxia/Kconfig"
733 source "arch/arm/mach-bcm/Kconfig"
735 source "arch/arm/mach-berlin/Kconfig"
737 source "arch/arm/mach-clps711x/Kconfig"
739 source "arch/arm/mach-cns3xxx/Kconfig"
741 source "arch/arm/mach-davinci/Kconfig"
743 source "arch/arm/mach-digicolor/Kconfig"
745 source "arch/arm/mach-dove/Kconfig"
747 source "arch/arm/mach-ep93xx/Kconfig"
749 source "arch/arm/mach-footbridge/Kconfig"
751 source "arch/arm/mach-gemini/Kconfig"
753 source "arch/arm/mach-highbank/Kconfig"
755 source "arch/arm/mach-hisi/Kconfig"
757 source "arch/arm/mach-integrator/Kconfig"
759 source "arch/arm/mach-iop32x/Kconfig"
761 source "arch/arm/mach-iop33x/Kconfig"
763 source "arch/arm/mach-iop13xx/Kconfig"
765 source "arch/arm/mach-ixp4xx/Kconfig"
767 source "arch/arm/mach-keystone/Kconfig"
769 source "arch/arm/mach-ks8695/Kconfig"
771 source "arch/arm/mach-meson/Kconfig"
773 source "arch/arm/mach-moxart/Kconfig"
775 source "arch/arm/mach-aspeed/Kconfig"
777 source "arch/arm/mach-mv78xx0/Kconfig"
779 source "arch/arm/mach-imx/Kconfig"
781 source "arch/arm/mach-mediatek/Kconfig"
783 source "arch/arm/mach-mxs/Kconfig"
785 source "arch/arm/mach-netx/Kconfig"
787 source "arch/arm/mach-nomadik/Kconfig"
789 source "arch/arm/mach-nspire/Kconfig"
791 source "arch/arm/plat-omap/Kconfig"
793 source "arch/arm/mach-omap1/Kconfig"
795 source "arch/arm/mach-omap2/Kconfig"
797 source "arch/arm/mach-orion5x/Kconfig"
799 source "arch/arm/mach-picoxcell/Kconfig"
801 source "arch/arm/mach-pxa/Kconfig"
802 source "arch/arm/plat-pxa/Kconfig"
804 source "arch/arm/mach-mmp/Kconfig"
806 source "arch/arm/mach-oxnas/Kconfig"
808 source "arch/arm/mach-qcom/Kconfig"
810 source "arch/arm/mach-realview/Kconfig"
812 source "arch/arm/mach-rockchip/Kconfig"
814 source "arch/arm/mach-sa1100/Kconfig"
816 source "arch/arm/mach-socfpga/Kconfig"
818 source "arch/arm/mach-spear/Kconfig"
820 source "arch/arm/mach-sti/Kconfig"
822 source "arch/arm/mach-s3c24xx/Kconfig"
824 source "arch/arm/mach-s3c64xx/Kconfig"
826 source "arch/arm/mach-s5pv210/Kconfig"
828 source "arch/arm/mach-exynos/Kconfig"
829 source "arch/arm/plat-samsung/Kconfig"
831 source "arch/arm/mach-shmobile/Kconfig"
833 source "arch/arm/mach-sunxi/Kconfig"
835 source "arch/arm/mach-prima2/Kconfig"
837 source "arch/arm/mach-tango/Kconfig"
839 source "arch/arm/mach-tegra/Kconfig"
841 source "arch/arm/mach-u300/Kconfig"
843 source "arch/arm/mach-uniphier/Kconfig"
845 source "arch/arm/mach-ux500/Kconfig"
847 source "arch/arm/mach-versatile/Kconfig"
849 source "arch/arm/mach-vexpress/Kconfig"
850 source "arch/arm/plat-versatile/Kconfig"
852 source "arch/arm/mach-vt8500/Kconfig"
854 source "arch/arm/mach-w90x900/Kconfig"
856 source "arch/arm/mach-zx/Kconfig"
858 source "arch/arm/mach-zynq/Kconfig"
860 # ARMv7-M architecture
862 bool "Energy Micro efm32"
863 depends on ARM_SINGLE_ARMV7M
866 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
870 bool "NXP LPC18xx/LPC43xx"
871 depends on ARM_SINGLE_ARMV7M
872 select ARCH_HAS_RESET_CONTROLLER
874 select CLKSRC_LPC32XX
877 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
878 high performance microcontrollers.
881 bool "STMicrolectronics STM32"
882 depends on ARM_SINGLE_ARMV7M
883 select ARCH_HAS_RESET_CONTROLLER
884 select ARMV7M_SYSTICK
887 select RESET_CONTROLLER
890 Support for STMicroelectronics STM32 processors.
892 config MACH_STM32F429
893 bool "STMicrolectronics STM32F429"
894 depends on ARCH_STM32
897 config MACH_STM32F746
898 bool "STMicrolectronics STM32F746"
899 depends on ARCH_STM32
903 bool "ARM MPS2 platform"
904 depends on ARM_SINGLE_ARMV7M
908 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
909 with a range of available cores like Cortex-M3/M4/M7.
911 Please, note that depends which Application Note is used memory map
912 for the platform may vary, so adjustment of RAM base might be needed.
914 # Definitions to make life easier
920 select GENERIC_CLOCKEVENTS
926 select GENERIC_IRQ_CHIP
929 config PLAT_ORION_LEGACY
936 config PLAT_VERSATILE
939 source "arch/arm/firmware/Kconfig"
941 source arch/arm/mm/Kconfig
944 bool "Enable iWMMXt support"
945 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
946 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
948 Enable support for iWMMXt context switching at run time if
949 running on a CPU that supports it.
951 config MULTI_IRQ_HANDLER
954 Allow each machine to specify it's own IRQ handler at run time.
957 source "arch/arm/Kconfig-nommu"
960 config PJ4B_ERRATA_4742
961 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
962 depends on CPU_PJ4B && MACH_ARMADA_370
965 When coming out of either a Wait for Interrupt (WFI) or a Wait for
966 Event (WFE) IDLE states, a specific timing sensitivity exists between
967 the retiring WFI/WFE instructions and the newly issued subsequent
968 instructions. This sensitivity can result in a CPU hang scenario.
970 The software must insert either a Data Synchronization Barrier (DSB)
971 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
974 config ARM_ERRATA_326103
975 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
978 Executing a SWP instruction to read-only memory does not set bit 11
979 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
980 treat the access as a read, preventing a COW from occurring and
981 causing the faulting task to livelock.
983 config ARM_ERRATA_411920
984 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
985 depends on CPU_V6 || CPU_V6K
987 Invalidation of the Instruction Cache operation can
988 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
989 It does not affect the MPCore. This option enables the ARM Ltd.
990 recommended workaround.
992 config ARM_ERRATA_430973
993 bool "ARM errata: Stale prediction on replaced interworking branch"
996 This option enables the workaround for the 430973 Cortex-A8
997 r1p* erratum. If a code sequence containing an ARM/Thumb
998 interworking branch is replaced with another code sequence at the
999 same virtual address, whether due to self-modifying code or virtual
1000 to physical address re-mapping, Cortex-A8 does not recover from the
1001 stale interworking branch prediction. This results in Cortex-A8
1002 executing the new code sequence in the incorrect ARM or Thumb state.
1003 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1004 and also flushes the branch target cache at every context switch.
1005 Note that setting specific bits in the ACTLR register may not be
1006 available in non-secure mode.
1008 config ARM_ERRATA_458693
1009 bool "ARM errata: Processor deadlock when a false hazard is created"
1011 depends on !ARCH_MULTIPLATFORM
1013 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1014 erratum. For very specific sequences of memory operations, it is
1015 possible for a hazard condition intended for a cache line to instead
1016 be incorrectly associated with a different cache line. This false
1017 hazard might then cause a processor deadlock. The workaround enables
1018 the L1 caching of the NEON accesses and disables the PLD instruction
1019 in the ACTLR register. Note that setting specific bits in the ACTLR
1020 register may not be available in non-secure mode.
1022 config ARM_ERRATA_460075
1023 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1025 depends on !ARCH_MULTIPLATFORM
1027 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1028 erratum. Any asynchronous access to the L2 cache may encounter a
1029 situation in which recent store transactions to the L2 cache are lost
1030 and overwritten with stale memory contents from external memory. The
1031 workaround disables the write-allocate mode for the L2 cache via the
1032 ACTLR register. Note that setting specific bits in the ACTLR register
1033 may not be available in non-secure mode.
1035 config ARM_ERRATA_742230
1036 bool "ARM errata: DMB operation may be faulty"
1037 depends on CPU_V7 && SMP
1038 depends on !ARCH_MULTIPLATFORM
1040 This option enables the workaround for the 742230 Cortex-A9
1041 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1042 between two write operations may not ensure the correct visibility
1043 ordering of the two writes. This workaround sets a specific bit in
1044 the diagnostic register of the Cortex-A9 which causes the DMB
1045 instruction to behave as a DSB, ensuring the correct behaviour of
1048 config ARM_ERRATA_742231
1049 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1050 depends on CPU_V7 && SMP
1051 depends on !ARCH_MULTIPLATFORM
1053 This option enables the workaround for the 742231 Cortex-A9
1054 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1055 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1056 accessing some data located in the same cache line, may get corrupted
1057 data due to bad handling of the address hazard when the line gets
1058 replaced from one of the CPUs at the same time as another CPU is
1059 accessing it. This workaround sets specific bits in the diagnostic
1060 register of the Cortex-A9 which reduces the linefill issuing
1061 capabilities of the processor.
1063 config ARM_ERRATA_643719
1064 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1065 depends on CPU_V7 && SMP
1068 This option enables the workaround for the 643719 Cortex-A9 (prior to
1069 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1070 register returns zero when it should return one. The workaround
1071 corrects this value, ensuring cache maintenance operations which use
1072 it behave as intended and avoiding data corruption.
1074 config ARM_ERRATA_720789
1075 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1078 This option enables the workaround for the 720789 Cortex-A9 (prior to
1079 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1080 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1081 As a consequence of this erratum, some TLB entries which should be
1082 invalidated are not, resulting in an incoherency in the system page
1083 tables. The workaround changes the TLB flushing routines to invalidate
1084 entries regardless of the ASID.
1086 config ARM_ERRATA_743622
1087 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1089 depends on !ARCH_MULTIPLATFORM
1091 This option enables the workaround for the 743622 Cortex-A9
1092 (r2p*) erratum. Under very rare conditions, a faulty
1093 optimisation in the Cortex-A9 Store Buffer may lead to data
1094 corruption. This workaround sets a specific bit in the diagnostic
1095 register of the Cortex-A9 which disables the Store Buffer
1096 optimisation, preventing the defect from occurring. This has no
1097 visible impact on the overall performance or power consumption of the
1100 config ARM_ERRATA_751472
1101 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1103 depends on !ARCH_MULTIPLATFORM
1105 This option enables the workaround for the 751472 Cortex-A9 (prior
1106 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1107 completion of a following broadcasted operation if the second
1108 operation is received by a CPU before the ICIALLUIS has completed,
1109 potentially leading to corrupted entries in the cache or TLB.
1111 config ARM_ERRATA_754322
1112 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1115 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1116 r3p*) erratum. A speculative memory access may cause a page table walk
1117 which starts prior to an ASID switch but completes afterwards. This
1118 can populate the micro-TLB with a stale entry which may be hit with
1119 the new ASID. This workaround places two dsb instructions in the mm
1120 switching code so that no page table walks can cross the ASID switch.
1122 config ARM_ERRATA_754327
1123 bool "ARM errata: no automatic Store Buffer drain"
1124 depends on CPU_V7 && SMP
1126 This option enables the workaround for the 754327 Cortex-A9 (prior to
1127 r2p0) erratum. The Store Buffer does not have any automatic draining
1128 mechanism and therefore a livelock may occur if an external agent
1129 continuously polls a memory location waiting to observe an update.
1130 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1131 written polling loops from denying visibility of updates to memory.
1133 config ARM_ERRATA_364296
1134 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1137 This options enables the workaround for the 364296 ARM1136
1138 r0p2 erratum (possible cache data corruption with
1139 hit-under-miss enabled). It sets the undocumented bit 31 in
1140 the auxiliary control register and the FI bit in the control
1141 register, thus disabling hit-under-miss without putting the
1142 processor into full low interrupt latency mode. ARM11MPCore
1145 config ARM_ERRATA_764369
1146 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1147 depends on CPU_V7 && SMP
1149 This option enables the workaround for erratum 764369
1150 affecting Cortex-A9 MPCore with two or more processors (all
1151 current revisions). Under certain timing circumstances, a data
1152 cache line maintenance operation by MVA targeting an Inner
1153 Shareable memory region may fail to proceed up to either the
1154 Point of Coherency or to the Point of Unification of the
1155 system. This workaround adds a DSB instruction before the
1156 relevant cache maintenance functions and sets a specific bit
1157 in the diagnostic control register of the SCU.
1159 config ARM_ERRATA_775420
1160 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1163 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1164 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1165 operation aborts with MMU exception, it might cause the processor
1166 to deadlock. This workaround puts DSB before executing ISB if
1167 an abort may occur on cache maintenance.
1169 config ARM_ERRATA_798181
1170 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1171 depends on CPU_V7 && SMP
1173 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1174 adequately shooting down all use of the old entries. This
1175 option enables the Linux kernel workaround for this erratum
1176 which sends an IPI to the CPUs that are running the same ASID
1177 as the one being invalidated.
1179 config ARM_ERRATA_773022
1180 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1183 This option enables the workaround for the 773022 Cortex-A15
1184 (up to r0p4) erratum. In certain rare sequences of code, the
1185 loop buffer may deliver incorrect instructions. This
1186 workaround disables the loop buffer to avoid the erratum.
1188 config ARM_ERRATA_818325_852422
1189 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1192 This option enables the workaround for:
1193 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1194 instruction might deadlock. Fixed in r0p1.
1195 - Cortex-A12 852422: Execution of a sequence of instructions might
1196 lead to either a data corruption or a CPU deadlock. Not fixed in
1197 any Cortex-A12 cores yet.
1198 This workaround for all both errata involves setting bit[12] of the
1199 Feature Register. This bit disables an optimisation applied to a
1200 sequence of 2 instructions that use opposing condition codes.
1202 config ARM_ERRATA_821420
1203 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1206 This option enables the workaround for the 821420 Cortex-A12
1207 (all revs) erratum. In very rare timing conditions, a sequence
1208 of VMOV to Core registers instructions, for which the second
1209 one is in the shadow of a branch or abort, can lead to a
1210 deadlock when the VMOV instructions are issued out-of-order.
1212 config ARM_ERRATA_825619
1213 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1216 This option enables the workaround for the 825619 Cortex-A12
1217 (all revs) erratum. Within rare timing constraints, executing a
1218 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1219 and Device/Strongly-Ordered loads and stores might cause deadlock
1221 config ARM_ERRATA_852421
1222 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1225 This option enables the workaround for the 852421 Cortex-A17
1226 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1227 execution of a DMB ST instruction might fail to properly order
1228 stores from GroupA and stores from GroupB.
1230 config ARM_ERRATA_852423
1231 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1234 This option enables the workaround for:
1235 - Cortex-A17 852423: Execution of a sequence of instructions might
1236 lead to either a data corruption or a CPU deadlock. Not fixed in
1237 any Cortex-A17 cores yet.
1238 This is identical to Cortex-A12 erratum 852422. It is a separate
1239 config option from the A12 erratum due to the way errata are checked
1244 source "arch/arm/common/Kconfig"
1251 Find out whether you have ISA slots on your motherboard. ISA is the
1252 name of a bus system, i.e. the way the CPU talks to the other stuff
1253 inside your box. Other bus systems are PCI, EISA, MicroChannel
1254 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1255 newer boards don't support it. If you have ISA, say Y, otherwise N.
1257 # Select ISA DMA controller support
1262 # Select ISA DMA interface
1267 bool "PCI support" if MIGHT_HAVE_PCI
1269 Find out whether you have a PCI motherboard. PCI is the name of a
1270 bus system, i.e. the way the CPU talks to the other stuff inside
1271 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1272 VESA. If you have PCI, say Y, otherwise N.
1278 config PCI_DOMAINS_GENERIC
1279 def_bool PCI_DOMAINS
1281 config PCI_NANOENGINE
1282 bool "BSE nanoEngine PCI support"
1283 depends on SA1100_NANOENGINE
1285 Enable PCI on the BSE nanoEngine board.
1290 config PCI_HOST_ITE8152
1292 depends on PCI && MACH_ARMCORE
1296 source "drivers/pci/Kconfig"
1298 source "drivers/pcmcia/Kconfig"
1302 menu "Kernel Features"
1307 This option should be selected by machines which have an SMP-
1310 The only effect of this option is to make the SMP-related
1311 options available to the user for configuration.
1314 bool "Symmetric Multi-Processing"
1315 depends on CPU_V6K || CPU_V7
1316 depends on GENERIC_CLOCKEVENTS
1318 depends on MMU || ARM_MPU
1321 This enables support for systems with more than one CPU. If you have
1322 a system with only one CPU, say N. If you have a system with more
1323 than one CPU, say Y.
1325 If you say N here, the kernel will run on uni- and multiprocessor
1326 machines, but will use only one CPU of a multiprocessor machine. If
1327 you say Y here, the kernel will run on many, but not all,
1328 uniprocessor machines. On a uniprocessor machine, the kernel
1329 will run faster if you say N here.
1331 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1332 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1333 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1335 If you don't know what to do here, say N.
1338 bool "Allow booting SMP kernel on uniprocessor systems"
1339 depends on SMP && !XIP_KERNEL && MMU
1342 SMP kernels contain instructions which fail on non-SMP processors.
1343 Enabling this option allows the kernel to modify itself to make
1344 these instructions safe. Disabling it allows about 1K of space
1347 If you don't know what to do here, say Y.
1349 config ARM_CPU_TOPOLOGY
1350 bool "Support cpu topology definition"
1351 depends on SMP && CPU_V7
1354 Support ARM cpu topology definition. The MPIDR register defines
1355 affinity between processors which is then used to describe the cpu
1356 topology of an ARM System.
1359 bool "Multi-core scheduler support"
1360 depends on ARM_CPU_TOPOLOGY
1362 Multi-core scheduler support improves the CPU scheduler's decision
1363 making when dealing with multi-core CPU chips at a cost of slightly
1364 increased overhead in some places. If unsure say N here.
1367 bool "SMT scheduler support"
1368 depends on ARM_CPU_TOPOLOGY
1370 Improves the CPU scheduler's decision making when dealing with
1371 MultiThreading at a cost of slightly increased overhead in some
1372 places. If unsure say N here.
1377 This option enables support for the ARM system coherency unit
1379 config HAVE_ARM_ARCH_TIMER
1380 bool "Architected timer support"
1382 select ARM_ARCH_TIMER
1383 select GENERIC_CLOCKEVENTS
1385 This option enables support for the ARM architected timer
1389 select CLKSRC_OF if OF
1391 This options enables support for the ARM timer and watchdog unit
1394 bool "Multi-Cluster Power Management"
1395 depends on CPU_V7 && SMP
1397 This option provides the common power management infrastructure
1398 for (multi-)cluster based systems, such as big.LITTLE based
1401 config MCPM_QUAD_CLUSTER
1405 To avoid wasting resources unnecessarily, MCPM only supports up
1406 to 2 clusters by default.
1407 Platforms with 3 or 4 clusters that use MCPM must select this
1408 option to allow the additional clusters to be managed.
1411 bool "big.LITTLE support (Experimental)"
1412 depends on CPU_V7 && SMP
1415 This option enables support selections for the big.LITTLE
1416 system architecture.
1419 bool "big.LITTLE switcher support"
1420 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1423 The big.LITTLE "switcher" provides the core functionality to
1424 transparently handle transition between a cluster of A15's
1425 and a cluster of A7's in a big.LITTLE system.
1427 config BL_SWITCHER_DUMMY_IF
1428 tristate "Simple big.LITTLE switcher user interface"
1429 depends on BL_SWITCHER && DEBUG_KERNEL
1431 This is a simple and dummy char dev interface to control
1432 the big.LITTLE switcher core code. It is meant for
1433 debugging purposes only.
1436 prompt "Memory split"
1440 Select the desired split between kernel and user memory.
1442 If you are not absolutely sure what you are doing, leave this
1446 bool "3G/1G user/kernel split"
1447 config VMSPLIT_3G_OPT
1448 bool "3G/1G user/kernel split (for full 1G low memory)"
1450 bool "2G/2G user/kernel split"
1452 bool "1G/3G user/kernel split"
1457 default PHYS_OFFSET if !MMU
1458 default 0x40000000 if VMSPLIT_1G
1459 default 0x80000000 if VMSPLIT_2G
1460 default 0xB0000000 if VMSPLIT_3G_OPT
1464 int "Maximum number of CPUs (2-32)"
1470 bool "Support for hot-pluggable CPUs"
1473 Say Y here to experiment with turning CPUs off and on. CPUs
1474 can be controlled through /sys/devices/system/cpu.
1477 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1478 depends on HAVE_ARM_SMCCC
1481 Say Y here if you want Linux to communicate with system firmware
1482 implementing the PSCI specification for CPU-centric power
1483 management operations described in ARM document number ARM DEN
1484 0022A ("Power State Coordination Interface System Software on
1487 # The GPIO number here must be sorted by descending number. In case of
1488 # a multiplatform kernel, we just want the highest value required by the
1489 # selected platforms.
1492 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1494 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1495 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1496 default 416 if ARCH_SUNXI
1497 default 392 if ARCH_U8500
1498 default 352 if ARCH_VT8500
1499 default 288 if ARCH_ROCKCHIP
1500 default 264 if MACH_H4700
1503 Maximum number of GPIOs in the system.
1505 If unsure, leave the default value.
1507 source kernel/Kconfig.preempt
1511 default 200 if ARCH_EBSA110
1512 default 128 if SOC_AT91RM9200
1516 depends on HZ_FIXED = 0
1517 prompt "Timer frequency"
1541 default HZ_FIXED if HZ_FIXED != 0
1542 default 100 if HZ_100
1543 default 200 if HZ_200
1544 default 250 if HZ_250
1545 default 300 if HZ_300
1546 default 500 if HZ_500
1550 def_bool HIGH_RES_TIMERS
1552 config THUMB2_KERNEL
1553 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1554 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1555 default y if CPU_THUMBONLY
1557 select ARM_ASM_UNIFIED
1560 By enabling this option, the kernel will be compiled in
1561 Thumb-2 mode. A compiler/assembler that understand the unified
1562 ARM-Thumb syntax is needed.
1566 config THUMB2_AVOID_R_ARM_THM_JUMP11
1567 bool "Work around buggy Thumb-2 short branch relocations in gas"
1568 depends on THUMB2_KERNEL && MODULES
1571 Various binutils versions can resolve Thumb-2 branches to
1572 locally-defined, preemptible global symbols as short-range "b.n"
1573 branch instructions.
1575 This is a problem, because there's no guarantee the final
1576 destination of the symbol, or any candidate locations for a
1577 trampoline, are within range of the branch. For this reason, the
1578 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1579 relocation in modules at all, and it makes little sense to add
1582 The symptom is that the kernel fails with an "unsupported
1583 relocation" error when loading some modules.
1585 Until fixed tools are available, passing
1586 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1587 code which hits this problem, at the cost of a bit of extra runtime
1588 stack usage in some cases.
1590 The problem is described in more detail at:
1591 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1593 Only Thumb-2 kernels are affected.
1595 Unless you are sure your tools don't have this problem, say Y.
1597 config ARM_ASM_UNIFIED
1600 config ARM_PATCH_IDIV
1601 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1602 depends on CPU_32v7 && !XIP_KERNEL
1605 The ARM compiler inserts calls to __aeabi_idiv() and
1606 __aeabi_uidiv() when it needs to perform division on signed
1607 and unsigned integers. Some v7 CPUs have support for the sdiv
1608 and udiv instructions that can be used to implement those
1611 Enabling this option allows the kernel to modify itself to
1612 replace the first two instructions of these library functions
1613 with the sdiv or udiv plus "bx lr" instructions when the CPU
1614 it is running on supports them. Typically this will be faster
1615 and less power intensive than running the original library
1616 code to do integer division.
1619 bool "Use the ARM EABI to compile the kernel"
1621 This option allows for the kernel to be compiled using the latest
1622 ARM ABI (aka EABI). This is only useful if you are using a user
1623 space environment that is also compiled with EABI.
1625 Since there are major incompatibilities between the legacy ABI and
1626 EABI, especially with regard to structure member alignment, this
1627 option also changes the kernel syscall calling convention to
1628 disambiguate both ABIs and allow for backward compatibility support
1629 (selected with CONFIG_OABI_COMPAT).
1631 To use this you need GCC version 4.0.0 or later.
1634 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1635 depends on AEABI && !THUMB2_KERNEL
1637 This option preserves the old syscall interface along with the
1638 new (ARM EABI) one. It also provides a compatibility layer to
1639 intercept syscalls that have structure arguments which layout
1640 in memory differs between the legacy ABI and the new ARM EABI
1641 (only for non "thumb" binaries). This option adds a tiny
1642 overhead to all syscalls and produces a slightly larger kernel.
1644 The seccomp filter system will not be available when this is
1645 selected, since there is no way yet to sensibly distinguish
1646 between calling conventions during filtering.
1648 If you know you'll be using only pure EABI user space then you
1649 can say N here. If this option is not selected and you attempt
1650 to execute a legacy ABI binary then the result will be
1651 UNPREDICTABLE (in fact it can be predicted that it won't work
1652 at all). If in doubt say N.
1654 config ARCH_HAS_HOLES_MEMORYMODEL
1657 config ARCH_SPARSEMEM_ENABLE
1660 config ARCH_SPARSEMEM_DEFAULT
1661 def_bool ARCH_SPARSEMEM_ENABLE
1663 config ARCH_SELECT_MEMORY_MODEL
1664 def_bool ARCH_SPARSEMEM_ENABLE
1666 config HAVE_ARCH_PFN_VALID
1667 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1669 config HAVE_GENERIC_RCU_GUP
1674 bool "High Memory Support"
1677 The address space of ARM processors is only 4 Gigabytes large
1678 and it has to accommodate user address space, kernel address
1679 space as well as some memory mapped IO. That means that, if you
1680 have a large amount of physical memory and/or IO, not all of the
1681 memory can be "permanently mapped" by the kernel. The physical
1682 memory that is not permanently mapped is called "high memory".
1684 Depending on the selected kernel/user memory split, minimum
1685 vmalloc space and actual amount of RAM, you may not need this
1686 option which should result in a slightly faster kernel.
1691 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1695 The VM uses one page of physical memory for each page table.
1696 For systems with a lot of processes, this can use a lot of
1697 precious low memory, eventually leading to low memory being
1698 consumed by page tables. Setting this option will allow
1699 user-space 2nd level page tables to reside in high memory.
1701 config CPU_SW_DOMAIN_PAN
1702 bool "Enable use of CPU domains to implement privileged no-access"
1703 depends on MMU && !ARM_LPAE
1706 Increase kernel security by ensuring that normal kernel accesses
1707 are unable to access userspace addresses. This can help prevent
1708 use-after-free bugs becoming an exploitable privilege escalation
1709 by ensuring that magic values (such as LIST_POISON) will always
1710 fault when dereferenced.
1712 CPUs with low-vector mappings use a best-efforts implementation.
1713 Their lower 1MB needs to remain accessible for the vectors, but
1714 the remainder of userspace will become appropriately inaccessible.
1716 config HW_PERF_EVENTS
1720 config SYS_SUPPORTS_HUGETLBFS
1724 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1728 config ARCH_WANT_GENERAL_HUGETLB
1731 config ARM_MODULE_PLTS
1732 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1735 Allocate PLTs when loading modules so that jumps and calls whose
1736 targets are too far away for their relative offsets to be encoded
1737 in the instructions themselves can be bounced via veneers in the
1738 module's PLT. This allows modules to be allocated in the generic
1739 vmalloc area after the dedicated module memory area has been
1740 exhausted. The modules will use slightly more memory, but after
1741 rounding up to page size, the actual memory footprint is usually
1744 Say y if you are getting out of memory errors while loading modules
1748 config FORCE_MAX_ZONEORDER
1749 int "Maximum zone order"
1750 default "12" if SOC_AM33XX
1751 default "9" if SA1111 || ARCH_EFM32
1754 The kernel memory allocator divides physically contiguous memory
1755 blocks into "zones", where each zone is a power of two number of
1756 pages. This option selects the largest power of two that the kernel
1757 keeps in the memory allocator. If you need to allocate very large
1758 blocks of physically contiguous memory, then you may need to
1759 increase this value.
1761 This config option is actually maximum order plus one. For example,
1762 a value of 11 means that the largest free memory block is 2^10 pages.
1764 config ALIGNMENT_TRAP
1766 depends on CPU_CP15_MMU
1767 default y if !ARCH_EBSA110
1768 select HAVE_PROC_CPU if PROC_FS
1770 ARM processors cannot fetch/store information which is not
1771 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1772 address divisible by 4. On 32-bit ARM processors, these non-aligned
1773 fetch/store instructions will be emulated in software if you say
1774 here, which has a severe performance impact. This is necessary for
1775 correct operation of some network protocols. With an IP-only
1776 configuration it is safe to say N, otherwise say Y.
1778 config UACCESS_WITH_MEMCPY
1779 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1781 default y if CPU_FEROCEON
1783 Implement faster copy_to_user and clear_user methods for CPU
1784 cores where a 8-word STM instruction give significantly higher
1785 memory write throughput than a sequence of individual 32bit stores.
1787 A possible side effect is a slight increase in scheduling latency
1788 between threads sharing the same address space if they invoke
1789 such copy operations with large buffers.
1791 However, if the CPU data cache is using a write-allocate mode,
1792 this option is unlikely to provide any performance gain.
1796 prompt "Enable seccomp to safely compute untrusted bytecode"
1798 This kernel feature is useful for number crunching applications
1799 that may need to compute untrusted bytecode during their
1800 execution. By using pipes or other transports made available to
1801 the process as file descriptors supporting the read/write
1802 syscalls, it's possible to isolate those applications in
1803 their own address space using seccomp. Once seccomp is
1804 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1805 and the task is only allowed to execute a few safe syscalls
1806 defined by each seccomp mode.
1815 bool "Enable paravirtualization code"
1817 This changes the kernel so it can modify itself when it is run
1818 under a hypervisor, potentially improving performance significantly
1819 over full virtualization.
1821 config PARAVIRT_TIME_ACCOUNTING
1822 bool "Paravirtual steal time accounting"
1826 Select this option to enable fine granularity task steal time
1827 accounting. Time spent executing other tasks in parallel with
1828 the current vCPU is discounted from the vCPU power. To account for
1829 that, there can be a small performance impact.
1831 If in doubt, say N here.
1838 bool "Xen guest support on ARM"
1839 depends on ARM && AEABI && OF
1840 depends on CPU_V7 && !CPU_V6
1841 depends on !GENERIC_ATOMIC64
1843 select ARCH_DMA_ADDR_T_64BIT
1848 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1855 bool "Flattened Device Tree support"
1859 Include support for flattened device tree machine descriptions.
1862 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1865 This is the traditional way of passing data to the kernel at boot
1866 time. If you are solely relying on the flattened device tree (or
1867 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1868 to remove ATAGS support from your kernel binary. If unsure,
1871 config DEPRECATED_PARAM_STRUCT
1872 bool "Provide old way to pass kernel parameters"
1875 This was deprecated in 2001 and announced to live on for 5 years.
1876 Some old boot loaders still use this way.
1878 # Compressed boot loader in ROM. Yes, we really want to ask about
1879 # TEXT and BSS so we preserve their values in the config files.
1880 config ZBOOT_ROM_TEXT
1881 hex "Compressed ROM boot loader base address"
1884 The physical address at which the ROM-able zImage is to be
1885 placed in the target. Platforms which normally make use of
1886 ROM-able zImage formats normally set this to a suitable
1887 value in their defconfig file.
1889 If ZBOOT_ROM is not enabled, this has no effect.
1891 config ZBOOT_ROM_BSS
1892 hex "Compressed ROM boot loader BSS address"
1895 The base address of an area of read/write memory in the target
1896 for the ROM-able zImage which must be available while the
1897 decompressor is running. It must be large enough to hold the
1898 entire decompressed kernel plus an additional 128 KiB.
1899 Platforms which normally make use of ROM-able zImage formats
1900 normally set this to a suitable value in their defconfig file.
1902 If ZBOOT_ROM is not enabled, this has no effect.
1905 bool "Compressed boot loader in ROM/flash"
1906 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1907 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1909 Say Y here if you intend to execute your compressed kernel image
1910 (zImage) directly from ROM or flash. If unsure, say N.
1912 config ARM_APPENDED_DTB
1913 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1916 With this option, the boot code will look for a device tree binary
1917 (DTB) appended to zImage
1918 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1920 This is meant as a backward compatibility convenience for those
1921 systems with a bootloader that can't be upgraded to accommodate
1922 the documented boot protocol using a device tree.
1924 Beware that there is very little in terms of protection against
1925 this option being confused by leftover garbage in memory that might
1926 look like a DTB header after a reboot if no actual DTB is appended
1927 to zImage. Do not leave this option active in a production kernel
1928 if you don't intend to always append a DTB. Proper passing of the
1929 location into r2 of a bootloader provided DTB is always preferable
1932 config ARM_ATAG_DTB_COMPAT
1933 bool "Supplement the appended DTB with traditional ATAG information"
1934 depends on ARM_APPENDED_DTB
1936 Some old bootloaders can't be updated to a DTB capable one, yet
1937 they provide ATAGs with memory configuration, the ramdisk address,
1938 the kernel cmdline string, etc. Such information is dynamically
1939 provided by the bootloader and can't always be stored in a static
1940 DTB. To allow a device tree enabled kernel to be used with such
1941 bootloaders, this option allows zImage to extract the information
1942 from the ATAG list and store it at run time into the appended DTB.
1945 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1946 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1948 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1949 bool "Use bootloader kernel arguments if available"
1951 Uses the command-line options passed by the boot loader instead of
1952 the device tree bootargs property. If the boot loader doesn't provide
1953 any, the device tree bootargs property will be used.
1955 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1956 bool "Extend with bootloader kernel arguments"
1958 The command-line arguments provided by the boot loader will be
1959 appended to the the device tree bootargs property.
1964 string "Default kernel command string"
1967 On some architectures (EBSA110 and CATS), there is currently no way
1968 for the boot loader to pass arguments to the kernel. For these
1969 architectures, you should supply some command-line options at build
1970 time by entering them here. As a minimum, you should specify the
1971 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1974 prompt "Kernel command line type" if CMDLINE != ""
1975 default CMDLINE_FROM_BOOTLOADER
1978 config CMDLINE_FROM_BOOTLOADER
1979 bool "Use bootloader kernel arguments if available"
1981 Uses the command-line options passed by the boot loader. If
1982 the boot loader doesn't provide any, the default kernel command
1983 string provided in CMDLINE will be used.
1985 config CMDLINE_EXTEND
1986 bool "Extend bootloader kernel arguments"
1988 The command-line arguments provided by the boot loader will be
1989 appended to the default kernel command string.
1991 config CMDLINE_FORCE
1992 bool "Always use the default kernel command string"
1994 Always use the default kernel command string, even if the boot
1995 loader passes other arguments to the kernel.
1996 This is useful if you cannot or don't want to change the
1997 command-line options your boot loader passes to the kernel.
2001 bool "Kernel Execute-In-Place from ROM"
2002 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2004 Execute-In-Place allows the kernel to run from non-volatile storage
2005 directly addressable by the CPU, such as NOR flash. This saves RAM
2006 space since the text section of the kernel is not loaded from flash
2007 to RAM. Read-write sections, such as the data section and stack,
2008 are still copied to RAM. The XIP kernel is not compressed since
2009 it has to run directly from flash, so it will take more space to
2010 store it. The flash address used to link the kernel object files,
2011 and for storing it, is configuration dependent. Therefore, if you
2012 say Y here, you must know the proper physical address where to
2013 store the kernel image depending on your own flash memory usage.
2015 Also note that the make target becomes "make xipImage" rather than
2016 "make zImage" or "make Image". The final kernel binary to put in
2017 ROM memory will be arch/arm/boot/xipImage.
2021 config XIP_PHYS_ADDR
2022 hex "XIP Kernel Physical Location"
2023 depends on XIP_KERNEL
2024 default "0x00080000"
2026 This is the physical address in your flash memory the kernel will
2027 be linked for and stored to. This address is dependent on your
2031 bool "Kexec system call (EXPERIMENTAL)"
2032 depends on (!SMP || PM_SLEEP_SMP)
2036 kexec is a system call that implements the ability to shutdown your
2037 current kernel, and to start another kernel. It is like a reboot
2038 but it is independent of the system firmware. And like a reboot
2039 you can start any kernel with it, not just Linux.
2041 It is an ongoing process to be certain the hardware in a machine
2042 is properly shutdown, so do not be surprised if this code does not
2043 initially work for you.
2046 bool "Export atags in procfs"
2047 depends on ATAGS && KEXEC
2050 Should the atags used to boot the kernel be exported in an "atags"
2051 file in procfs. Useful with kexec.
2054 bool "Build kdump crash kernel (EXPERIMENTAL)"
2056 Generate crash dump after being started by kexec. This should
2057 be normally only set in special crash dump kernels which are
2058 loaded in the main kernel with kexec-tools into a specially
2059 reserved region and then later executed after a crash by
2060 kdump/kexec. The crash dump kernel must be compiled to a
2061 memory address not used by the main kernel
2063 For more details see Documentation/kdump/kdump.txt
2065 config AUTO_ZRELADDR
2066 bool "Auto calculation of the decompressed kernel image address"
2068 ZRELADDR is the physical address where the decompressed kernel
2069 image will be placed. If AUTO_ZRELADDR is selected, the address
2070 will be determined at run-time by masking the current IP with
2071 0xf8000000. This assumes the zImage being placed in the first 128MB
2072 from start of memory.
2078 bool "UEFI runtime support"
2079 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2081 select EFI_PARAMS_FROM_FDT
2084 select EFI_RUNTIME_WRAPPERS
2086 This option provides support for runtime services provided
2087 by UEFI firmware (such as non-volatile variables, realtime
2088 clock, and platform reset). A UEFI stub is also provided to
2089 allow the kernel to be booted as an EFI application. This
2090 is only useful for kernels that may run on systems that have
2095 menu "CPU Power Management"
2097 source "drivers/cpufreq/Kconfig"
2099 source "drivers/cpuidle/Kconfig"
2103 menu "Floating point emulation"
2105 comment "At least one emulation must be selected"
2108 bool "NWFPE math emulation"
2109 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2111 Say Y to include the NWFPE floating point emulator in the kernel.
2112 This is necessary to run most binaries. Linux does not currently
2113 support floating point hardware so you need to say Y here even if
2114 your machine has an FPA or floating point co-processor podule.
2116 You may say N here if you are going to load the Acorn FPEmulator
2117 early in the bootup.
2120 bool "Support extended precision"
2121 depends on FPE_NWFPE
2123 Say Y to include 80-bit support in the kernel floating-point
2124 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2125 Note that gcc does not generate 80-bit operations by default,
2126 so in most cases this option only enlarges the size of the
2127 floating point emulator without any good reason.
2129 You almost surely want to say N here.
2132 bool "FastFPE math emulation (EXPERIMENTAL)"
2133 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2135 Say Y here to include the FAST floating point emulator in the kernel.
2136 This is an experimental much faster emulator which now also has full
2137 precision for the mantissa. It does not support any exceptions.
2138 It is very simple, and approximately 3-6 times faster than NWFPE.
2140 It should be sufficient for most programs. It may be not suitable
2141 for scientific calculations, but you have to check this for yourself.
2142 If you do not feel you need a faster FP emulation you should better
2146 bool "VFP-format floating point maths"
2147 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2149 Say Y to include VFP support code in the kernel. This is needed
2150 if your hardware includes a VFP unit.
2152 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2153 release notes and additional status information.
2155 Say N if your target does not have VFP hardware.
2163 bool "Advanced SIMD (NEON) Extension support"
2164 depends on VFPv3 && CPU_V7
2166 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2169 config KERNEL_MODE_NEON
2170 bool "Support for NEON in kernel mode"
2171 depends on NEON && AEABI
2173 Say Y to include support for NEON in kernel mode.
2177 menu "Userspace binary formats"
2179 source "fs/Kconfig.binfmt"
2183 menu "Power management options"
2185 source "kernel/power/Kconfig"
2187 config ARCH_SUSPEND_POSSIBLE
2188 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2189 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2192 config ARM_CPU_SUSPEND
2193 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2194 depends on ARCH_SUSPEND_POSSIBLE
2196 config ARCH_HIBERNATION_POSSIBLE
2199 default y if ARCH_SUSPEND_POSSIBLE
2203 source "net/Kconfig"
2205 source "drivers/Kconfig"
2207 source "drivers/firmware/Kconfig"
2211 source "arch/arm/Kconfig.debug"
2213 source "security/Kconfig"
2215 source "crypto/Kconfig"
2217 source "arch/arm/crypto/Kconfig"
2220 source "lib/Kconfig"
2222 source "arch/arm/kvm/Kconfig"