9 #define FIO_ARCH (arch_ppc)
11 #define nop do { } while (0)
14 #define read_barrier() __asm__ __volatile__ ("lwsync" : : : "memory")
16 #define read_barrier() __asm__ __volatile__ ("sync" : : : "memory")
19 #define write_barrier() __asm__ __volatile__ ("sync" : : : "memory")
22 #define PPC_CNTLZL "cntlzd"
24 #define PPC_CNTLZL "cntlzw"
27 static inline int __ilog2(unsigned long bitmask)
31 asm (PPC_CNTLZL " %0,%1" : "=r" (lz) : "r" (bitmask));
32 return BITS_PER_LONG - 1 - lz;
35 static inline int arch_ffz(unsigned long bitmask)
37 if ((bitmask = ~bitmask) == 0)
39 return __ilog2(bitmask & -bitmask);
42 static inline unsigned int mfspr(unsigned int reg)
46 asm volatile("mfspr %0,%1": "=r" (val) : "K" (reg));
50 #define SPRN_TBRL 0x10C /* Time Base Register Lower */
51 #define SPRN_TBRU 0x10D /* Time Base Register Upper */
52 #define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
53 #define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
56 static inline unsigned long long get_cpu_clock(void)
58 unsigned long long rval;
70 static inline unsigned long long get_cpu_clock(void)
72 unsigned int tbl, tbu0, tbu1;
73 unsigned long long ret;
76 if (arch_flags & ARCH_FLAG_1) {
77 tbu0 = mfspr(SPRN_ATBU);
78 tbl = mfspr(SPRN_ATBL);
79 tbu1 = mfspr(SPRN_ATBU);
81 tbu0 = mfspr(SPRN_TBRU);
82 tbl = mfspr(SPRN_TBRL);
83 tbu1 = mfspr(SPRN_TBRU);
85 } while (tbu0 != tbu1);
87 ret = (((unsigned long long)tbu0) << 32) | tbl;
93 static void atb_child(void)
95 arch_flags |= ARCH_FLAG_1;
100 static void atb_clocktest(void)
107 else if (pid != -1) {
111 if (pid == -1 || !WIFEXITED(status))
112 arch_flags &= ~ARCH_FLAG_1;
114 arch_flags |= ARCH_FLAG_1;
119 #define ARCH_HAVE_INIT
120 extern bool tsc_reliable;
122 static inline int arch_init(char *envp[])
131 #define ARCH_HAVE_FFZ
134 * We don't have it on all platforms, lets comment this out until we
135 * can handle it more intelligently.
137 * #define ARCH_HAVE_CPU_CLOCK
141 * Let's have it defined for ppc64
145 #define ARCH_HAVE_CPU_CLOCK