4 #define FIO_ARCH (arch_ppc)
6 #ifndef __NR_ioprio_set
7 #define __NR_ioprio_set 273
8 #define __NR_ioprio_get 274
11 #ifndef __NR_fadvise64
12 #define __NR_fadvise64 233
15 #ifndef __NR_sys_splice
16 #define __NR_sys_splice 283
17 #define __NR_sys_tee 284
18 #define __NR_sys_vmsplice 285
21 #define nop do { } while (0)
24 #define read_barrier() __asm__ __volatile__ ("lwsync" : : : "memory")
26 #define read_barrier() __asm__ __volatile__ ("sync" : : : "memory")
29 #define write_barrier() __asm__ __volatile__ ("sync" : : : "memory")
31 static inline int __ilog2(unsigned long bitmask)
35 asm ("cntlzw %0,%1" : "=r" (lz) : "r" (bitmask));
39 static inline int arch_ffz(unsigned long bitmask)
41 if ((bitmask = ~bitmask) == 0)
43 return __ilog2(bitmask & -bitmask);
46 static inline unsigned long long get_cpu_clock(void)
48 unsigned int tbl, tbu0, tbu1;
49 unsigned long long ret;
52 __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0));
53 __asm__ __volatile__ ("mftb %0" : "=r"(tbl) );
54 __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1));
55 } while (tbu0 != tbu1);
57 ret = (((unsigned long long)tbu0) << 32) | tbl;
62 #define ARCH_HAVE_CPU_CLOCK