9 #define FIO_ARCH (arch_ppc)
11 #ifndef __NR_ioprio_set
12 #define __NR_ioprio_set 273
13 #define __NR_ioprio_get 274
16 #ifndef __NR_fadvise64
17 #define __NR_fadvise64 233
20 #ifndef __NR_sys_splice
21 #define __NR_sys_splice 283
22 #define __NR_sys_tee 284
23 #define __NR_sys_vmsplice 285
26 #define nop do { } while (0)
29 #define read_barrier() __asm__ __volatile__ ("lwsync" : : : "memory")
31 #define read_barrier() __asm__ __volatile__ ("sync" : : : "memory")
34 #define write_barrier() __asm__ __volatile__ ("sync" : : : "memory")
36 static inline int __ilog2(unsigned long bitmask)
40 asm ("cntlzw %0,%1" : "=r" (lz) : "r" (bitmask));
44 static inline int arch_ffz(unsigned long bitmask)
46 if ((bitmask = ~bitmask) == 0)
48 return __ilog2(bitmask & -bitmask);
51 static inline unsigned int mfspr(unsigned int reg)
55 asm volatile("mfspr %0,%1": "=r" (val) : "K" (reg));
59 #define SPRN_TBRL 0x10C /* Time Base Register Lower */
60 #define SPRN_TBRU 0x10D /* Time Base Register Upper */
61 #define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
62 #define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
64 static inline unsigned long long get_cpu_clock(void)
66 unsigned int tbl, tbu0, tbu1;
67 unsigned long long ret;
70 if (arch_flags & ARCH_FLAG_1) {
71 tbu0 = mfspr(SPRN_ATBU);
72 tbl = mfspr(SPRN_ATBL);
73 tbu1 = mfspr(SPRN_ATBU);
75 tbu0 = mfspr(SPRN_TBRU);
76 tbl = mfspr(SPRN_TBRL);
77 tbu1 = mfspr(SPRN_TBRU);
79 } while (tbu0 != tbu1);
81 ret = (((unsigned long long)tbu0) << 32) | tbl;
85 static void atb_child(void)
87 arch_flags |= ARCH_FLAG_1;
92 static void atb_clocktest(void)
103 if (pid == -1 || !WIFEXITED(status))
104 arch_flags &= ~ARCH_FLAG_1;
106 arch_flags |= ARCH_FLAG_1;
110 #define ARCH_HAVE_INIT
111 extern int tsc_reliable;
113 static inline int arch_init(char *envp[])
120 #define ARCH_HAVE_FFZ
121 #define ARCH_HAVE_CPU_CLOCK