4 #define ARCH (arch_ia64)
6 #ifndef __NR_ioprio_set
7 #define __NR_ioprio_set 1274
8 #define __NR_ioprio_get 1275
11 #ifndef __NR_fadvise64
12 #define __NR_fadvise64 1234
15 #ifndef __NR_sys_splice
16 #define __NR_sys_splice 1297
17 #define __NR_sys_tee 1301
18 #define __NR_sys_vmsplice 1302
21 #define nop asm volatile ("hint @pause" ::: "memory");
22 #define read_barrier() asm volatile ("mf" ::: "memory")
23 #define writebarrier() asm volatile ("mf" ::: "memory")
25 #define ia64_popcnt(x) \
27 unsigned long ia64_intri_res; \
28 asm ("popcnt %0=%1" : "=r" (ia64_intri_res) : "r" (x)); \
32 static inline unsigned long arch_ffz(unsigned long bitmask)
34 return ia64_popcnt(bitmask & (~bitmask - 1));
39 volatile unsigned int lock;
42 #define IA64_SPINLOCK_CLOBBERS "ar.ccv", "ar.pfs", "p14", "p15", "r27", "r28", "r29", "r30", "b6", "memory"
44 static inline void spin_lock(spinlock_t *lock)
46 register volatile unsigned int *ptr asm ("r31") = &lock->lock;
47 unsigned long flags = 0;
49 __asm__ __volatile__("{\n\t"
50 " mov ar.ccv = r0\n\t"
54 "cmpxchg4.acq r30 = [%1], r30, ar.ccv\n\t"
55 "movl r29 = ia64_spinlock_contention_pre3_4;;\n\t"
56 "cmp4.ne p14, p0 = r30, r0\n\t"
59 "(p14) br.cond.spnt.many b6"
60 : "=r"(ptr) : "r"(ptr), "r" (flags)
61 : IA64_SPINLOCK_CLOBBERS);
64 static inline void spin_unlock(spinlock_t *lock)
67 __asm__ __volatile__("st4.rel.nta [%0] = r0\n\t" :: "r" (lock));
70 #define __SPIN_LOCK_UNLOCKED { 0 }