2 * ARC ARConnect (MultiCore IP) support (formerly known as MCIP)
4 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/smp.h>
12 #include <linux/irq.h>
13 #include <linux/spinlock.h>
14 #include <asm/irqflags-arcv2.h>
16 #include <asm/setup.h>
18 static DEFINE_RAW_SPINLOCK(mcip_lock);
22 static char smp_cpuinfo_buf[128];
24 static void mcip_setup_per_cpu(int cpu)
26 smp_ipi_irq_setup(cpu, IPI_IRQ);
27 smp_ipi_irq_setup(cpu, SOFTIRQ_IRQ);
30 static void mcip_ipi_send(int cpu)
35 /* ARConnect can only send IPI to others */
36 if (unlikely(cpu == raw_smp_processor_id())) {
37 arc_softirq_trigger(SOFTIRQ_IRQ);
41 raw_spin_lock_irqsave(&mcip_lock, flags);
44 * If receiver already has a pending interrupt, elide sending this one.
45 * Linux cross core calling works well with concurrent IPIs
47 * see arch/arc/kernel/smp.c: ipi_send_msg_one()
49 __mcip_cmd(CMD_INTRPT_READ_STATUS, cpu);
50 ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK);
52 __mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu);
54 raw_spin_unlock_irqrestore(&mcip_lock, flags);
57 static void mcip_ipi_clear(int irq)
62 if (unlikely(irq == SOFTIRQ_IRQ)) {
63 arc_softirq_clear(irq);
67 raw_spin_lock_irqsave(&mcip_lock, flags);
69 /* Who sent the IPI */
70 __mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0);
72 cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */
75 * In rare case, multiple concurrent IPIs sent to same target can
76 * possibly be coalesced by MCIP into 1 asserted IRQ, so @cpus can be
77 * "vectored" (multiple bits sets) as opposed to typical single bit
80 c = __ffs(cpu); /* 0,1,2,3 */
81 __mcip_cmd(CMD_INTRPT_GENERATE_ACK, c);
85 raw_spin_unlock_irqrestore(&mcip_lock, flags);
88 static void mcip_probe_n_setup(void)
92 READ_BCR(ARC_REG_MCIP_BCR, mp);
94 sprintf(smp_cpuinfo_buf,
95 "Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s%s\n",
97 IS_AVAIL1(mp.ipi, "IPI "),
98 IS_AVAIL1(mp.idu, "IDU "),
99 IS_AVAIL1(mp.llm, "LLM "),
100 IS_AVAIL1(mp.dbg, "DEBUG "),
101 IS_AVAIL1(mp.gfrc, "GFRC"));
103 cpuinfo_arc700[0].extn.gfrc = mp.gfrc;
106 __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf);
107 __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
111 struct plat_smp_ops plat_smp_ops = {
112 .info = smp_cpuinfo_buf,
113 .init_early_smp = mcip_probe_n_setup,
114 .init_per_cpu = mcip_setup_per_cpu,
115 .ipi_send = mcip_ipi_send,
116 .ipi_clear = mcip_ipi_clear,
121 /***************************************************************************
122 * ARCv2 Interrupt Distribution Unit (IDU)
124 * Connects external "COMMON" IRQs to core intc, providing:
125 * -dynamic routing (IRQ affinity)
126 * -load balancing (Round Robin interrupt distribution)
129 * It physically resides in the MCIP hw block
132 #include <linux/irqchip.h>
133 #include <linux/of.h>
134 #include <linux/of_irq.h>
137 * Set the DEST for @cmn_irq to @cpu_mask (1 bit per core)
139 static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask)
141 __mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask);
144 static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
150 unsigned int distr:2, pad:2, lvl:1, pad2:27;
156 __mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
159 static void idu_irq_mask(struct irq_data *data)
163 raw_spin_lock_irqsave(&mcip_lock, flags);
164 __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
165 raw_spin_unlock_irqrestore(&mcip_lock, flags);
168 static void idu_irq_unmask(struct irq_data *data)
172 raw_spin_lock_irqsave(&mcip_lock, flags);
173 __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0);
174 raw_spin_unlock_irqrestore(&mcip_lock, flags);
179 idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
185 /* errout if no online cpu per @cpumask */
186 if (!cpumask_and(&online, cpumask, cpu_online_mask))
189 raw_spin_lock_irqsave(&mcip_lock, flags);
191 idu_set_dest(data->hwirq, cpumask_bits(&online)[0]);
192 idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);
194 raw_spin_unlock_irqrestore(&mcip_lock, flags);
196 return IRQ_SET_MASK_OK;
200 static struct irq_chip idu_irq_chip = {
201 .name = "MCIP IDU Intc",
202 .irq_mask = idu_irq_mask,
203 .irq_unmask = idu_irq_unmask,
205 .irq_set_affinity = idu_irq_set_affinity,
210 static int idu_first_irq;
212 static void idu_cascade_isr(struct irq_desc *desc)
214 struct irq_domain *domain = irq_desc_get_handler_data(desc);
215 unsigned int core_irq = irq_desc_get_irq(desc);
216 unsigned int idu_irq;
218 idu_irq = core_irq - idu_first_irq;
219 generic_handle_irq(irq_find_mapping(domain, idu_irq));
222 static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq)
224 irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq);
225 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
230 static int idu_irq_xlate(struct irq_domain *d, struct device_node *n,
231 const u32 *intspec, unsigned int intsize,
232 irq_hw_number_t *out_hwirq, unsigned int *out_type)
234 irq_hw_number_t hwirq = *out_hwirq = intspec[0];
235 int distri = intspec[1];
238 *out_type = IRQ_TYPE_NONE;
240 /* XXX: validate distribution scheme again online cpu mask */
242 /* 0 - Round Robin to all cpus, otherwise 1 bit per core */
243 raw_spin_lock_irqsave(&mcip_lock, flags);
244 idu_set_dest(hwirq, BIT(num_online_cpus()) - 1);
245 idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);
246 raw_spin_unlock_irqrestore(&mcip_lock, flags);
249 * DEST based distribution for Level Triggered intr can only
250 * have 1 CPU, so generalize it to always contain 1 cpu
252 int cpu = ffs(distri);
254 if (cpu != fls(distri))
255 pr_warn("IDU irq %lx distri mode set to cpu %x\n",
258 raw_spin_lock_irqsave(&mcip_lock, flags);
259 idu_set_dest(hwirq, cpu);
260 idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_DEST);
261 raw_spin_unlock_irqrestore(&mcip_lock, flags);
267 static const struct irq_domain_ops idu_irq_ops = {
268 .xlate = idu_irq_xlate,
273 * [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI)
274 * [24, 23+C]: If C > 0 then "C" common IRQs
275 * [24+C, N]: Not statically assigned, private-per-core
280 idu_of_init(struct device_node *intc, struct device_node *parent)
282 struct irq_domain *domain;
283 /* Read IDU BCR to confirm nr_irqs */
284 int nr_irqs = of_irq_count(intc);
288 READ_BCR(ARC_REG_MCIP_BCR, mp);
291 panic("IDU not detected, but DeviceTree using it");
293 pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs);
295 domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL);
297 /* Parent interrupts (core-intc) are already mapped */
299 for (i = 0; i < nr_irqs; i++) {
301 * Return parent uplink IRQs (towards core intc) 24,25,.....
302 * this step has been done before already
303 * however we need it to get the parent virq and set IDU handler
306 irq = irq_of_parse_and_map(intc, i);
310 irq_set_chained_handler_and_data(irq, idu_cascade_isr, domain);
313 __mcip_cmd(CMD_IDU_ENABLE, 0);
317 IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init);