2 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * Device Tree for ARC HS Development Kit
14 #include <dt-bindings/net/ti-dp83867.h>
15 #include <dt-bindings/reset/snps,hsdk-reset.h>
19 compatible = "snps,hsdk";
25 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
38 compatible = "snps,archs38";
45 compatible = "snps,archs38";
52 compatible = "snps,archs38";
59 compatible = "snps,archs38";
65 input_clk: input-clk {
67 compatible = "fixed-clock";
68 clock-frequency = <33333333>;
71 cpu_intc: cpu-interrupt-controller {
72 compatible = "snps,archs-intc";
74 #interrupt-cells = <1>;
77 idu_intc: idu-interrupt-controller {
78 compatible = "snps,archs-idu-intc";
80 #interrupt-cells = <1>;
81 interrupt-parent = <&cpu_intc>;
85 compatible = "snps,archs-pct";
88 /* TIMER0 with interrupt for clockevent */
90 compatible = "snps,arc-timer";
92 interrupt-parent = <&cpu_intc>;
96 /* 64-bit Global Free Running Counter */
98 compatible = "snps,archs-timer-gfrc";
103 compatible = "simple-bus";
104 #address-cells = <1>;
106 interrupt-parent = <&idu_intc>;
108 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
110 cgu_rst: reset-controller@8a0 {
111 compatible = "snps,hsdk-reset";
113 reg = <0x8a0 0x4>, <0xff0 0x4>;
116 core_clk: core-clk@0 {
117 compatible = "snps,hsdk-core-pll-clock";
118 reg = <0x00 0x10>, <0x14b8 0x4>;
120 clocks = <&input_clk>;
123 * Set initial core pll output frequency to 1GHz.
124 * It will be applied at the core pll driver probing
127 assigned-clocks = <&core_clk>;
128 assigned-clock-rates = <1000000000>;
131 serial: serial@5000 {
132 compatible = "snps,dw-apb-uart";
133 reg = <0x5000 0x100>;
134 clock-frequency = <33330000>;
142 compatible = "fixed-clock";
143 clock-frequency = <400000000>;
147 mmcclk_ciu: mmcclk-ciu {
148 compatible = "fixed-clock";
150 * DW sdio controller has external ciu clock divider
151 * controlled via register in SDIO IP. Due to its
152 * unexpected default value (it should divide by 1
153 * but it divides by 8) SDIO IP uses wrong clock and
154 * works unstable (see STAR 9001204800)
155 * We switched to the minimum possible value of the
156 * divisor (div-by-2) in HSDK platform code.
157 * So add temporary fix and change clock frequency
158 * to 50000000 Hz until we fix dw sdio driver itself.
160 clock-frequency = <50000000>;
164 mmcclk_biu: mmcclk-biu {
165 compatible = "fixed-clock";
166 clock-frequency = <400000000>;
170 dmac_core_clk: dmac-core-clk {
171 compatible = "fixed-clock";
172 clock-frequency = <400000000>;
176 dmac_cfg_clk: dmac-gpu-cfg-clk {
177 compatible = "fixed-clock";
178 clock-frequency = <200000000>;
182 gmac: ethernet@8000 {
183 #interrupt-cells = <1>;
184 compatible = "snps,dwmac";
185 reg = <0x8000 0x2000>;
187 interrupt-names = "macirq";
191 clock-names = "stmmaceth";
192 phy-handle = <&phy0>;
193 resets = <&cgu_rst HSDK_ETH_RESET>;
194 reset-names = "stmmaceth";
195 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
199 #address-cells = <1>;
201 compatible = "snps,dwmac-mdio";
202 phy0: ethernet-phy@0 {
204 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
205 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
206 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
212 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
213 reg = <0x60000 0x100>;
215 resets = <&cgu_rst HSDK_USB_RESET>;
220 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
221 reg = <0x40000 0x100>;
223 resets = <&cgu_rst HSDK_USB_RESET>;
228 compatible = "altr,socfpga-dw-mshc";
229 reg = <0xa000 0x400>;
232 card-detect-delay = <200>;
233 clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
234 clock-names = "biu", "ciu";
241 compatible = "snps,dw-apb-gpio";
243 #address-cells = <1>;
246 gpio_port_a: gpio-controller@0 {
247 compatible = "snps,dw-apb-gpio-port";
250 snps,nr-gpios = <24>;
256 compatible = "snps,axi-dma-1.01a";
257 reg = <0x80000 0x400>;
259 clocks = <&dmac_core_clk>, <&dmac_cfg_clk>;
260 clock-names = "core-clk", "cfgr-clk";
263 snps,dma-masters = <2>;
264 snps,data-width = <3>;
265 snps,block-size = <4096 4096 4096 4096>;
266 snps,priority = <0 1 2 3>;
267 snps,axi-max-burst-len = <16>;
272 #address-cells = <2>;
274 device_type = "memory";
275 reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */
276 /* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */