2 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * Device Tree for ARC HS Development Kit
14 #include <dt-bindings/net/ti-dp83867.h>
15 #include <dt-bindings/reset/snps,hsdk-reset.h>
19 compatible = "snps,hsdk";
25 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
34 compatible = "snps,archs38";
41 compatible = "snps,archs38";
48 compatible = "snps,archs38";
55 compatible = "snps,archs38";
61 input_clk: input-clk {
63 compatible = "fixed-clock";
64 clock-frequency = <33333333>;
67 cpu_intc: cpu-interrupt-controller {
68 compatible = "snps,archs-intc";
70 #interrupt-cells = <1>;
73 idu_intc: idu-interrupt-controller {
74 compatible = "snps,archs-idu-intc";
76 #interrupt-cells = <1>;
77 interrupt-parent = <&cpu_intc>;
81 compatible = "snps,archs-pct";
84 /* TIMER0 with interrupt for clockevent */
86 compatible = "snps,arc-timer";
88 interrupt-parent = <&cpu_intc>;
92 /* 64-bit Global Free Running Counter */
94 compatible = "snps,archs-timer-gfrc";
99 compatible = "simple-bus";
100 #address-cells = <1>;
102 interrupt-parent = <&idu_intc>;
104 ranges = <0x00000000 0xf0000000 0x10000000>;
106 cgu_rst: reset-controller@8a0 {
107 compatible = "snps,hsdk-reset";
109 reg = <0x8A0 0x4>, <0xFF0 0x4>;
112 core_clk: core-clk@0 {
113 compatible = "snps,hsdk-core-pll-clock";
114 reg = <0x00 0x10>, <0x14B8 0x4>;
116 clocks = <&input_clk>;
119 * Set initial core pll output frequency to 1GHz.
120 * It will be applied at the core pll driver probing
123 assigned-clocks = <&core_clk>;
124 assigned-clock-rates = <1000000000>;
127 serial: serial@5000 {
128 compatible = "snps,dw-apb-uart";
129 reg = <0x5000 0x100>;
130 clock-frequency = <33330000>;
138 compatible = "fixed-clock";
139 clock-frequency = <400000000>;
143 mmcclk_ciu: mmcclk-ciu {
144 compatible = "fixed-clock";
146 * DW sdio controller has external ciu clock divider
147 * controlled via register in SDIO IP. Due to its
148 * unexpected default value (it should divide by 1
149 * but it divides by 8) SDIO IP uses wrong clock and
150 * works unstable (see STAR 9001204800)
151 * We switched to the minimum possible value of the
152 * divisor (div-by-2) in HSDK platform code.
153 * So add temporary fix and change clock frequency
154 * to 50000000 Hz until we fix dw sdio driver itself.
156 clock-frequency = <50000000>;
160 mmcclk_biu: mmcclk-biu {
161 compatible = "fixed-clock";
162 clock-frequency = <400000000>;
167 #interrupt-cells = <1>;
168 compatible = "snps,dwmac";
169 reg = <0x8000 0x2000>;
171 interrupt-names = "macirq";
175 clock-names = "stmmaceth";
176 phy-handle = <&phy0>;
177 resets = <&cgu_rst HSDK_ETH_RESET>;
178 reset-names = "stmmaceth";
181 #address-cells = <1>;
183 compatible = "snps,dwmac-mdio";
184 phy0: ethernet-phy@0 {
186 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
187 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
188 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
194 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
195 reg = <0x60000 0x100>;
200 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
201 reg = <0x40000 0x100>;
206 compatible = "altr,socfpga-dw-mshc";
207 reg = <0xa000 0x400>;
210 card-detect-delay = <200>;
211 clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
212 clock-names = "biu", "ciu";
219 #address-cells = <1>;
221 device_type = "memory";
222 reg = <0x80000000 0x40000000>; /* 1 GiB */