2 * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
13 /include/ "skeleton_hs_idu.dtsi"
16 compatible = "snps,arc";
17 clock-frequency = <90000000>;
22 compatible = "simple-bus";
26 ranges = <0x00000000 0xf0000000 0x10000000>;
30 compatible = "fixed-clock";
31 clock-frequency = <100000000>;
34 core_intc: archs-intc@cpu {
35 compatible = "snps,archs-intc";
37 #interrupt-cells = <1>;
40 idu_intc: idu-interrupt-controller {
41 compatible = "snps,archs-idu-intc";
43 interrupt-parent = <&core_intc>;
46 * <hwirq distribution>
47 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
49 #interrupt-cells = <2>;
52 * upstream irqs to core intc - downstream these are
59 * this GPIO block ORs all interrupts on CPU card (creg,..)
60 * to uplink only 1 IRQ to ARC core intc
63 compatible = "snps,dw-apb-gpio";
64 reg = < 0x2000 0x80 >;
68 ictl_intc: gpio-controller@0 {
69 compatible = "snps,dw-apb-gpio-port";
75 #interrupt-cells = <2>;
76 interrupt-parent = <&idu_intc>;
79 * cmn irq 1 -> cpu irq 25
80 * Distribute to cpu0 only
86 debug_uart: dw-apb-uart@0x5000 {
87 compatible = "snps,dw-apb-uart";
89 clock-frequency = <33333000>;
90 interrupt-parent = <&ictl_intc>;
98 compatible = "snps,archs-pct";
99 #interrupt-cells = <1>;
100 interrupt-parent = <&core_intc>;
106 * This INTC is actually connected to DW APB GPIO
107 * which acts as a wire between MB INTC and CPU INTC.
108 * GPIO INTC is configured in platform init code
109 * and here we mimic direct connection from MB INTC to
110 * CPU INTC, thus we set "interrupts = <0 1>" instead of
111 * "interrupts = <12>"
113 * This intc actually resides on MB, but we move it here to
114 * avoid duplicating the MB dtsi file given that IRQ from
115 * this intc to cpu intc are different for axs101 and axs103
117 mb_intc: dw-apb-ictl@0xe0012000 {
118 #interrupt-cells = <1>;
119 compatible = "snps,dw-apb-ictl";
120 reg = < 0xe0012000 0x200 >;
121 interrupt-controller;
122 interrupt-parent = <&idu_intc>;
123 interrupts = <0 1>; /* cmn irq 0 -> cpu irq 24
124 distribute to cpu0 only */
128 #address-cells = <1>;
130 ranges = <0x00000000 0x80000000 0x40000000>;
131 device_type = "memory";
132 reg = <0x80000000 0x20000000>; /* 512MiB */
136 #address-cells = <1>;
140 * Move frame buffer out of IOC aperture (0x8z-0xAz).
142 frame_buffer: frame_buffer@be000000 {
143 compatible = "shared-dma-pool";
144 reg = <0xbe000000 0x2000000>;