2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 # This program is free software; you can redistribute it and/or modify
5 # it under the terms of the GNU General Public License version 2 as
6 # published by the Free Software Foundation.
12 select ARCH_HAS_DMA_COHERENT_TO_PFN
13 select ARCH_HAS_PTE_SPECIAL
14 select ARCH_HAS_SYNC_DMA_FOR_CPU
15 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
16 select ARCH_HAS_SG_CHAIN
17 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
18 select BUILDTIME_EXTABLE_SORT
19 select CLONE_BACKWARDS
22 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
23 select GENERIC_CLOCKEVENTS
24 select GENERIC_FIND_FIRST_BIT
25 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
26 select GENERIC_IRQ_SHOW
27 select GENERIC_PCI_IOMAP
28 select GENERIC_PENDING_IRQ if SMP
29 select GENERIC_SMP_IDLE_THREAD
31 select HAVE_ARCH_TRACEHOOK
32 select HAVE_DEBUG_STACKOVERFLOW
33 select HAVE_FUTEX_CMPXCHG if FUTEX
34 select HAVE_GENERIC_DMA_COHERENT
35 select HAVE_IOREMAP_PROT
36 select HAVE_KERNEL_GZIP
37 select HAVE_KERNEL_LZMA
39 select HAVE_KRETPROBES
40 select HAVE_MOD_ARCH_SPECIFIC
42 select HAVE_PERF_EVENTS
43 select HANDLE_DOMAIN_IRQ
45 select MODULES_USE_ELF_RELA
47 select OF_EARLY_FLATTREE
48 select OF_RESERVED_MEM
49 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
51 config ARCH_HAS_CACHE_LINE_SIZE
57 config TRACE_IRQFLAGS_SUPPORT
60 config LOCKDEP_SUPPORT
63 config SCHED_OMIT_FRAME_POINTER
69 config RWSEM_GENERIC_SPINLOCK
72 config ARCH_DISCONTIGMEM_ENABLE
75 config ARCH_FLATMEM_ENABLE
84 config GENERIC_CALIBRATE_DELAY
87 config GENERIC_HWEIGHT
90 config STACKTRACE_SUPPORT
94 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
98 menu "ARC Architecture Configuration"
100 menu "ARC Platform/SoC/Board"
102 source "arch/arc/plat-tb10x/Kconfig"
103 source "arch/arc/plat-axs10x/Kconfig"
104 #New platform adds here
105 source "arch/arc/plat-eznps/Kconfig"
106 source "arch/arc/plat-hsdk/Kconfig"
111 prompt "ARC Instruction Set"
112 default ISA_ARCOMPACT
116 select CPU_NO_EFFICIENT_FFS
118 The original ARC ISA of ARC600/700 cores
122 select ARC_TIMERS_64BIT
124 ISA for the Next Generation ARC-HS cores
128 menu "ARC CPU Configuration"
132 default ARC_CPU_770 if ISA_ARCOMPACT
133 default ARC_CPU_HS if ISA_ARCV2
141 Support for ARC750 core
147 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
148 This core has a bunch of cool new features:
149 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
150 Shared Address Spaces (for sharing TLB entries in MMU)
151 -Caches: New Prog Model, Region Flush
152 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
160 Support for ARC HS38x Cores based on ARCv2 ISA
161 The notable features are:
162 - SMP configurations of upto 4 core with coherency
163 - Optional L2 Cache and IO-Coherency
164 - Revised Interrupt Architecture (multiple priorites, reg banks,
165 auto stack switch, auto regfile save/restore)
166 - MMUv4 (PIPT dcache, Huge Pages)
168 * 64bit load/store: LDD, STD
169 * Hardware assisted divide/remainder: DIV, REM
170 * Function prologue/epilogue: ENTER_S, LEAVE_S
171 * IRQ enable/disable: CLRI, SETI
172 * pop count: FFS, FLS
173 * SETcc, BMSKN, XBFU...
177 config CPU_BIG_ENDIAN
178 bool "Enable Big Endian Mode"
181 Build kernel for Big Endian Mode of ARC CPU
184 bool "Symmetric Multi-Processing"
186 select ARC_MCIP if ISA_ARCV2
188 This enables support for systems with more than one CPU.
193 int "Maximum number of CPUs (2-4096)"
197 config ARC_SMP_HALT_ON_RESET
198 bool "Enable Halt-on-reset boot mode"
199 default y if ARC_UBOOT_SUPPORT
201 In SMP configuration cores can be configured as Halt-on-reset
202 or they could all start at same time. For Halt-on-reset, non
203 masters are parked until Master kicks them so they can start of
204 at designated entry point. For other case, all jump to common
205 entry point and spin wait for Master's signal.
210 bool "ARConnect Multicore IP (MCIP) Support "
214 This IP block enables SMP in ARC-HS38 cores.
215 It provides for cross-core interrupts, multi-core debug
216 hardware semaphores, shared memory,....
219 bool "Enable Cache Support"
224 config ARC_CACHE_LINE_SHIFT
225 int "Cache Line Length (as power of 2)"
229 Starting with ARC700 4.9, Cache line length is configurable,
230 This option specifies "N", with Line-len = 2 power N
231 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
232 Linux only supports same line lengths for I and D caches.
234 config ARC_HAS_ICACHE
235 bool "Use Instruction Cache"
238 config ARC_HAS_DCACHE
239 bool "Use Data Cache"
242 config ARC_CACHE_PAGES
243 bool "Per Page Cache Control"
245 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
247 This can be used to over-ride the global I/D Cache Enable on a
248 per-page basis (but only for pages accessed via MMU such as
249 Kernel Virtual address or User Virtual Address)
250 TLB entries have a per-page Cache Enable Bit.
251 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
252 Global DISABLE + Per Page ENABLE won't work
254 config ARC_CACHE_VIPT_ALIASING
255 bool "Support VIPT Aliasing D$"
256 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
264 Single Cycle RAMS to store Fast Path Code
268 int "ICCM Size in KB"
270 depends on ARC_HAS_ICCM
275 Single Cycle RAMS to store Fast Path Data
279 int "DCCM Size in KB"
281 depends on ARC_HAS_DCCM
284 hex "DCCM map address"
286 depends on ARC_HAS_DCCM
290 default ARC_MMU_V3 if ARC_CPU_770
291 default ARC_MMU_V2 if ARC_CPU_750D
292 default ARC_MMU_V4 if ARC_CPU_HS
304 Fixed the deficiency of v1 - possible thrashing in memcpy scenario
305 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
309 depends on ARC_CPU_770
311 Introduced with ARC700 4.10: New Features
312 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
313 Shared Address Spaces (SASID)
325 prompt "MMU Page Size"
326 default ARC_PAGE_SIZE_8K
328 config ARC_PAGE_SIZE_8K
331 Choose between 8k vs 16k
333 config ARC_PAGE_SIZE_16K
335 depends on ARC_MMU_V3 || ARC_MMU_V4
337 config ARC_PAGE_SIZE_4K
339 depends on ARC_MMU_V3 || ARC_MMU_V4
344 prompt "MMU Super Page Size"
345 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
346 default ARC_HUGEPAGE_2M
348 config ARC_HUGEPAGE_2M
351 config ARC_HUGEPAGE_16M
357 int "Maximum NUMA Nodes (as a power of 2)"
358 default "0" if !DISCONTIGMEM
359 default "1" if DISCONTIGMEM
360 depends on NEED_MULTIPLE_NODES
362 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
367 config ARC_COMPACT_IRQ_LEVELS
368 bool "Setup Timer IRQ as high Priority"
370 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
373 config ARC_FPU_SAVE_RESTORE
374 bool "Enable FPU state persistence across context switch"
377 Double Precision Floating Point unit had dedicated regs which
378 need to be saved/restored across context-switch.
379 Note that ARC FPU is overly simplistic, unlike say x86, which has
380 hardware pieces to allow software to conditionally save/restore,
381 based on actual usage of FPU by a task. Thus our implemn does
382 this for all tasks in system.
390 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
392 depends on !ARC_CANT_LLSC
395 bool "Insn: SWAPE (endian-swap)"
401 bool "Insn: 64bit LDD/STD"
403 Enable gcc to generate 64-bit load/store instructions
404 ISA mandates even/odd registers to allow encoding of two
405 dest operands with 2 possible source operands.
408 config ARC_HAS_DIV_REM
409 bool "Insn: div, divu, rem, remu"
412 config ARC_HAS_ACCL_REGS
413 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
416 Depending on the configuration, CPU can contain accumulator reg-pair
417 (also referred to as r58:r59). These can also be used by gcc as GPR so
418 kernel needs to save/restore per process
422 endmenu # "ARC CPU Configuration"
424 config LINUX_LINK_BASE
425 hex "Kernel link address"
428 ARC700 divides the 32 bit phy address space into two equal halves
429 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
430 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
431 Typically Linux kernel is linked at the start of untransalted addr,
432 hence the default value of 0x8zs.
433 However some customers have peripherals mapped at this addr, so
434 Linux needs to be scooted a bit.
435 If you don't know what the above means, leave this setting alone.
436 This needs to match memory start address specified in Device Tree
438 config LINUX_RAM_BASE
439 hex "RAM base address"
440 default LINUX_LINK_BASE
442 By default Linux is linked at base of RAM. However in some special
443 cases (such as HSDK), Linux can't be linked at start of DDR, hence
447 bool "High Memory Support"
448 select ARCH_DISCONTIGMEM_ENABLE
450 With ARC 2G:2G address split, only upper 2G is directly addressable by
451 kernel. Enable this to potentially allow access to rest of 2G and PAE
455 bool "Support for the 40-bit Physical Address Extension"
459 select PHYS_ADDR_T_64BIT
461 Enable access to physical memory beyond 4G, only supported on
462 ARC cores with 40 bit Physical Addressing support
464 config ARC_KVADDR_SIZE
465 int "Kernel Virtual Address Space size (MB)"
469 The kernel address space is carved out of 256MB of translated address
470 space for catering to vmalloc, modules, pkmap, fixmap. This however may
471 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
472 this to be stretched to 512 MB (by extending into the reserved
475 config ARC_CURR_IN_REG
476 bool "Dedicate Register r25 for current_task pointer"
479 This reserved Register R25 to point to Current Task in
480 kernel mode. This saves memory access for each such access
483 config ARC_EMUL_UNALIGNED
484 bool "Emulate unaligned memory access (userspace only)"
485 select SYSCTL_ARCH_UNALIGN_NO_WARN
486 select SYSCTL_ARCH_UNALIGN_ALLOW
487 depends on ISA_ARCOMPACT
489 This enables misaligned 16 & 32 bit memory access from user space.
490 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
491 potential bugs in code
494 int "Timer Frequency"
497 config ARC_METAWARE_HLINK
498 bool "Support for Metaware debugger assisted Host access"
501 This options allows a Linux userland apps to directly access
502 host file system (open/creat/read/write etc) with help from
503 Metaware Debugger. This can come in handy for Linux-host communication
504 when there is no real usable peripheral such as EMAC.
512 config ARC_DW2_UNWIND
513 bool "Enable DWARF specific kernel stack unwind"
517 Compiles the kernel with DWARF unwind information and can be used
518 to get stack backtraces.
520 If you say Y here the resulting kernel image will be slightly larger
521 but not slower, and it will give very useful debugging information.
522 If you don't debug the kernel, you can say N, but we may not be able
523 to solve problems without frame unwind information
525 config ARC_DBG_TLB_PARANOIA
526 bool "Paranoia Checks in Low Level TLB Handlers"
531 config ARC_UBOOT_SUPPORT
532 bool "Support uboot arg Handling"
535 ARC Linux by default checks for uboot provided args as pointers to
536 external cmdline or DTB. This however breaks in absence of uboot,
537 when booting from Metaware debugger directly, as the registers are
538 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
539 registers look like uboot args to kernel which then chokes.
540 So only enable the uboot arg checking/processing if users are sure
541 of uboot being in play.
543 config ARC_BUILTIN_DTB_NAME
544 string "Built in DTB"
546 Set the name of the DTB to embed in the vmlinux binary
547 Leaving it blank selects the minimal "skeleton" dtb
549 endmenu # "ARC Architecture Configuration"
551 config FORCE_MAX_ZONEORDER
552 int "Maximum zone order"
553 default "12" if ARC_HUGEPAGE_16M
559 bool "PCI support" if MIGHT_HAVE_PCI
561 PCI is the name of a bus system, i.e., the way the CPU talks to
562 the other stuff inside your box. Find out if your board/platform
565 Note: PCIe support for Synopsys Device will be available only
566 when HAPS DX is configured with PCIe RC bitmap. If you have PCI,
572 source "drivers/pci/Kconfig"
576 source "kernel/power/Kconfig"