2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 # This program is free software; you can redistribute it and/or modify
5 # it under the terms of the GNU General Public License version 2 as
6 # published by the Free Software Foundation.
11 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
12 select BUILDTIME_EXTABLE_SORT
14 select CLONE_BACKWARDS
15 select GENERIC_ATOMIC64
16 select GENERIC_CLOCKEVENTS
17 select GENERIC_FIND_FIRST_BIT
18 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
19 select GENERIC_IRQ_SHOW
20 select GENERIC_PENDING_IRQ if SMP
21 select GENERIC_SMP_IDLE_THREAD
23 select HAVE_ARCH_TRACEHOOK
24 select HAVE_FUTEX_CMPXCHG
25 select HAVE_IOREMAP_PROT
27 select HAVE_KRETPROBES
29 select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
31 select HAVE_PERF_EVENTS
33 select MODULES_USE_ELF_RELA
36 select OF_EARLY_FLATTREE
37 select PERF_USE_VMALLOC
38 select HAVE_DEBUG_STACKOVERFLOW
40 config TRACE_IRQFLAGS_SUPPORT
43 config LOCKDEP_SUPPORT
46 config SCHED_OMIT_FRAME_POINTER
52 config RWSEM_GENERIC_SPINLOCK
55 config ARCH_FLATMEM_ENABLE
64 config GENERIC_CALIBRATE_DELAY
67 config GENERIC_HWEIGHT
70 config STACKTRACE_SUPPORT
74 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
79 source "kernel/Kconfig.freezer"
81 menu "ARC Architecture Configuration"
83 menu "ARC Platform/SoC/Board"
85 source "arch/arc/plat-sim/Kconfig"
86 source "arch/arc/plat-tb10x/Kconfig"
87 source "arch/arc/plat-axs10x/Kconfig"
88 #New platform adds here
93 prompt "ARC Instruction Set"
99 The original ARC ISA of ARC600/700 cores
104 ISA for the Next Generation ARC-HS cores
108 menu "ARC CPU Configuration"
112 default ARC_CPU_770 if ISA_ARCOMPACT
113 default ARC_CPU_HS if ISA_ARCV2
121 Support for ARC750 core
127 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
128 This core has a bunch of cool new features:
129 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
130 Shared Address Spaces (for sharing TLB entires in MMU)
131 -Caches: New Prog Model, Region Flush
132 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
140 Support for ARC HS38x Cores based on ARCv2 ISA
141 The notable features are:
142 - SMP configurations of upto 4 core with coherency
143 - Optional L2 Cache and IO-Coherency
144 - Revised Interrupt Architecture (multiple priorites, reg banks,
145 auto stack switch, auto regfile save/restore)
146 - MMUv4 (PIPT dcache, Huge Pages)
148 * 64bit load/store: LDD, STD
149 * Hardware assisted divide/remainder: DIV, REM
150 * Function prologue/epilogue: ENTER_S, LEAVE_S
151 * IRQ enable/disable: CLRI, SETI
152 * pop count: FFS, FLS
153 * SETcc, BMSKN, XBFU...
157 config CPU_BIG_ENDIAN
158 bool "Enable Big Endian Mode"
161 Build kernel for Big Endian Mode of ARC CPU
164 bool "Symmetric Multi-Processing"
166 select ARC_HAS_COH_CACHES if ISA_ARCV2
167 select ARC_MCIP if ISA_ARCV2
169 This enables support for systems with more than one CPU.
173 config ARC_HAS_COH_CACHES
176 config ARC_HAS_REENTRANT_IRQ_LV2
180 bool "ARConnect Multicore IP (MCIP) Support "
183 This IP block enables SMP in ARC-HS38 cores.
184 It provides for cross-core interrupts, multi-core debug
185 hardware semaphores, shared memory,....
188 int "Maximum number of CPUs (2-4096)"
192 config ARC_SMP_HALT_ON_RESET
193 bool "Enable Halt-on-reset boot mode"
194 default y if ARC_UBOOT_SUPPORT
196 In SMP configuration cores can be configured as Halt-on-reset
197 or they could all start at same time. For Halt-on-reset, non
198 masters are parked until Master kicks them so they can start of
199 at designated entry point. For other case, all jump to common
200 entry point and spin wait for Master's signal.
205 bool "Enable Cache Support"
207 # if SMP, cache enabled ONLY if ARC implementation has cache coherency
208 depends on !SMP || ARC_HAS_COH_CACHES
212 config ARC_CACHE_LINE_SHIFT
213 int "Cache Line Length (as power of 2)"
217 Starting with ARC700 4.9, Cache line length is configurable,
218 This option specifies "N", with Line-len = 2 power N
219 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
220 Linux only supports same line lengths for I and D caches.
222 config ARC_HAS_ICACHE
223 bool "Use Instruction Cache"
226 config ARC_HAS_DCACHE
227 bool "Use Data Cache"
230 config ARC_CACHE_PAGES
231 bool "Per Page Cache Control"
233 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
235 This can be used to over-ride the global I/D Cache Enable on a
236 per-page basis (but only for pages accessed via MMU such as
237 Kernel Virtual address or User Virtual Address)
238 TLB entries have a per-page Cache Enable Bit.
239 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
240 Global DISABLE + Per Page ENABLE won't work
242 config ARC_CACHE_VIPT_ALIASING
243 bool "Support VIPT Aliasing D$"
244 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
252 Single Cycle RAMS to store Fast Path Code
256 int "ICCM Size in KB"
258 depends on ARC_HAS_ICCM
263 Single Cycle RAMS to store Fast Path Data
267 int "DCCM Size in KB"
269 depends on ARC_HAS_DCCM
272 hex "DCCM map address"
274 depends on ARC_HAS_DCCM
278 default ARC_MMU_V3 if ARC_CPU_770
279 default ARC_MMU_V2 if ARC_CPU_750D
280 default ARC_MMU_V4 if ARC_CPU_HS
292 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
293 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
297 depends on ARC_CPU_770
299 Introduced with ARC700 4.10: New Features
300 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
301 Shared Address Spaces (SASID)
313 prompt "MMU Page Size"
314 default ARC_PAGE_SIZE_8K
316 config ARC_PAGE_SIZE_8K
319 Choose between 8k vs 16k
321 config ARC_PAGE_SIZE_16K
323 depends on ARC_MMU_V3 || ARC_MMU_V4
325 config ARC_PAGE_SIZE_4K
327 depends on ARC_MMU_V3 || ARC_MMU_V4
332 prompt "MMU Super Page Size"
333 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
334 default ARC_HUGEPAGE_2M
336 config ARC_HUGEPAGE_2M
339 config ARC_HUGEPAGE_16M
346 config ARC_COMPACT_IRQ_LEVELS
347 bool "ARCompact IRQ Priorities: High(2)/Low(1)"
349 # Timer HAS to be high priority, for any other high priority config
351 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
352 depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2
354 if ARC_COMPACT_IRQ_LEVELS
365 endif #ARC_COMPACT_IRQ_LEVELS
367 config ARC_FPU_SAVE_RESTORE
368 bool "Enable FPU state persistence across context switch"
371 Double Precision Floating Point unit had dedictaed regs which
372 need to be saved/restored across context-switch.
373 Note that ARC FPU is overly simplistic, unlike say x86, which has
374 hardware pieces to allow software to conditionally save/restore,
375 based on actual usage of FPU by a task. Thus our implemn does
376 this for all tasks in system.
384 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
386 depends on !ARC_CANT_LLSC
388 config ARC_STAR_9000923308
389 bool "Workaround for llock/scond livelock"
391 depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC
394 bool "Insn: SWAPE (endian-swap)"
400 bool "Insn: 64bit LDD/STD"
402 Enable gcc to generate 64-bit load/store instructions
403 ISA mandates even/odd registers to allow encoding of two
404 dest operands with 2 possible source operands.
407 config ARC_HAS_DIV_REM
408 bool "Insn: div, divu, rem, remu"
412 bool "Local 64-bit r/o cycle counter"
417 bool "SMP synchronized 64-bit cycle counter"
421 config ARC_NUMBER_OF_INTERRUPTS
422 int "Number of interrupts"
426 This defines the number of interrupts on the ARCv2HS core.
427 It affects the size of vector table.
428 The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
429 in hardware, it keep things simple for Linux to assume they are always
434 endmenu # "ARC CPU Configuration"
436 config LINUX_LINK_BASE
437 hex "Linux Link Address"
440 ARC700 divides the 32 bit phy address space into two equal halves
441 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
442 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
443 Typically Linux kernel is linked at the start of untransalted addr,
444 hence the default value of 0x8zs.
445 However some customers have peripherals mapped at this addr, so
446 Linux needs to be scooted a bit.
447 If you don't know what the above means, leave this setting alone.
448 This needs to match memory start address specified in Device Tree
451 bool "High Memory Support"
453 With ARC 2G:2G address split, only upper 2G is directly addressable by
454 kernel. Enable this to potentially allow access to rest of 2G and PAE
458 bool "Support for the 40-bit Physical Address Extension"
463 Enable access to physical memory beyond 4G, only supported on
464 ARC cores with 40 bit Physical Addressing support
466 config ARCH_PHYS_ADDR_T_64BIT
467 def_bool ARC_HAS_PAE40
469 config ARCH_DMA_ADDR_T_64BIT
472 config ARC_CURR_IN_REG
473 bool "Dedicate Register r25 for current_task pointer"
476 This reserved Register R25 to point to Current Task in
477 kernel mode. This saves memory access for each such access
480 config ARC_EMUL_UNALIGNED
481 bool "Emulate unaligned memory access (userspace only)"
483 select SYSCTL_ARCH_UNALIGN_NO_WARN
484 select SYSCTL_ARCH_UNALIGN_ALLOW
485 depends on ISA_ARCOMPACT
487 This enables misaligned 16 & 32 bit memory access from user space.
488 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
489 potential bugs in code
492 int "Timer Frequency"
495 config ARC_METAWARE_HLINK
496 bool "Support for Metaware debugger assisted Host access"
499 This options allows a Linux userland apps to directly access
500 host file system (open/creat/read/write etc) with help from
501 Metaware Debugger. This can come in handy for Linux-host communication
502 when there is no real usable peripheral such as EMAC.
510 config ARC_DW2_UNWIND
511 bool "Enable DWARF specific kernel stack unwind"
515 Compiles the kernel with DWARF unwind information and can be used
516 to get stack backtraces.
518 If you say Y here the resulting kernel image will be slightly larger
519 but not slower, and it will give very useful debugging information.
520 If you don't debug the kernel, you can say N, but we may not be able
521 to solve problems without frame unwind information
523 config ARC_DBG_TLB_PARANOIA
524 bool "Paranoia Checks in Low Level TLB Handlers"
527 config ARC_DBG_TLB_MISS_COUNT
528 bool "Profile TLB Misses"
532 Counts number of I and D TLB Misses and exports them via Debugfs
533 The counters can be cleared via Debugfs as well
537 config ARC_UBOOT_SUPPORT
538 bool "Support uboot arg Handling"
541 ARC Linux by default checks for uboot provided args as pointers to
542 external cmdline or DTB. This however breaks in absence of uboot,
543 when booting from Metaware debugger directly, as the registers are
544 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
545 registers look like uboot args to kernel which then chokes.
546 So only enable the uboot arg checking/processing if users are sure
547 of uboot being in play.
549 config ARC_BUILTIN_DTB_NAME
550 string "Built in DTB"
552 Set the name of the DTB to embed in the vmlinux binary
553 Leaving it blank selects the minimal "skeleton" dtb
555 source "kernel/Kconfig.preempt"
557 menu "Executable file formats"
558 source "fs/Kconfig.binfmt"
561 endmenu # "ARC Architecture Configuration"
565 config FORCE_MAX_ZONEORDER
566 int "Maximum zone order"
567 default "12" if ARC_HUGEPAGE_16M
571 source "drivers/Kconfig"
573 source "arch/arc/Kconfig.debug"
574 source "security/Kconfig"
575 source "crypto/Kconfig"
577 source "kernel/power/Kconfig"