1 Device-Tree bindings for Samsung SoC display controller (FIMD)
3 FIMD (Fully Interactive Mobile Display) is the Display Controller for the
4 Samsung series of SoCs which transfers the image data from a video memory
5 buffer to an external LCD interface.
8 - compatible: value should be one of the following
9 "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
10 "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
11 "samsung,s5pv210-fimd"; /* for S5PV210 SoC */
12 "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
13 "samsung,exynos5250-fimd"; /* for Exynos5 SoCs */
15 - reg: physical base address and length of the FIMD registers set.
17 - interrupt-parent: should be the phandle of the fimd controller's
18 parent interrupt controller.
20 - interrupts: should contain a list of all FIMD IP block interrupts in the
21 order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
22 format depends on the interrupt controller used.
24 - interrupt-names: should contain the interrupt names: "fifo", "vsync",
25 "lcd_sys", in the same order as they were listed in the interrupts
28 - pinctrl-0: pin control group to be used for this controller.
30 - pinctrl-names: must contain a "default" entry.
32 - clocks: must include clock specifiers corresponding to entries in the
35 - clock-names: list of clock names sorted in the same order as the clocks
36 property. Must contain "sclk_fimd" and "fimd".
39 - samsung,power-domain: a phandle to FIMD power domain node.
40 - samsung,invert-vden: video enable signal is inverted
41 - samsung,invert-vclk: video clock signal is inverted
42 - display-timings: timing settings for FIMD, as described in document [1].
43 Can be used in case timings cannot be provided otherwise
44 or to override timings provided by the panel.
45 - samsung,sysreg: handle to syscon used to control the system registers
46 - i80-if-timings: timing configuration for lcd i80 interface support.
47 - cs-setup: clock cycles for the active period of address signal is enabled
48 until chip select is enabled.
49 If not specified, the default value(0) will be used.
50 - wr-setup: clock cycles for the active period of CS signal is enabled until
51 write signal is enabled.
52 If not specified, the default value(0) will be used.
53 - wr-active: clock cycles for the active period of CS is enabled.
54 If not specified, the default value(1) will be used.
55 - wr-hold: clock cycles for the active period of CS is disabled until write
57 If not specified, the default value(0) will be used.
59 The parameters are defined as:
61 VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
63 Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
66 Chip Select ???????????????|____________:____________:____________|??
67 | wr-setup+1 | | wr-hold+1 |
68 |<---------->| |<---------->|
69 Write Enable ????????????????????????????|____________|???????????????
72 Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--
74 The device node can contain 'port' child nodes according to the bindings defined
75 in [2]. The following are properties specific to those nodes:
76 - reg: (required) port index, can be:
80 3 - for parallel output,
81 4 - for write-back interface
83 [1]: Documentation/devicetree/bindings/video/display-timing.txt
84 [2]: Documentation/devicetree/bindings/media/video-interfaces.txt
88 SoC specific DT entry:
91 compatible = "samsung,exynos4210-fimd";
92 interrupt-parent = <&combiner>;
93 reg = <0x11c00000 0x20000>;
94 interrupt-names = "fifo", "vsync", "lcd_sys";
95 interrupts = <11 0>, <11 1>, <11 2>;
96 clocks = <&clock 140>, <&clock 283>;
97 clock-names = "sclk_fimd", "fimd";
98 samsung,power-domain = <&pd_lcd0>;
102 Board specific DT entry:
105 pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
106 pinctrl-names = "default";