1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
10 Many SPI controllers need to add properties to peripheral devices. They could
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
12 controller specific like delay in clock or data lines, etc. These properties
13 need to be defined in the peripheral node because they are per-peripheral and
14 there can be multiple peripherals attached to a controller. All those
15 properties are listed here. The controller specific properties should go in
16 their own separate schema that should be referenced from here.
19 - Pratyush Yadav <p.yadav@ti.com>
30 Chip select used by the device.
33 $ref: /schemas/types.yaml#/definitions/flag
35 The device requires 3-wire mode.
38 $ref: /schemas/types.yaml#/definitions/flag
40 The device requires shifted clock phase (CPHA) mode.
43 $ref: /schemas/types.yaml#/definitions/flag
45 The device requires inverse clock polarity (CPOL) mode.
48 $ref: /schemas/types.yaml#/definitions/flag
50 The device requires the chip select active high.
53 $ref: /schemas/types.yaml#/definitions/flag
55 The device requires the LSB first mode.
58 $ref: /schemas/types.yaml#/definitions/uint32
60 Maximum SPI clocking speed of the device in Hz.
64 Bus width to the SPI bus used for read transfers.
65 If 0 is provided, then no RX will be possible on this device.
66 $ref: /schemas/types.yaml#/definitions/uint32
72 Delay, in microseconds, after a read transfer.
75 description: SPI Rx sample delay offset, unit is nanoseconds.
76 The delay from the default sample time before the actual
77 sample of the rxd input signal occurs.
81 Bus width to the SPI bus used for write transfers.
82 If 0 is provided, then no TX will be possible on this device.
83 $ref: /schemas/types.yaml#/definitions/uint32
89 Delay, in microseconds, after a write transfer.
92 description: Several SPI memories can be wired in stacked mode.
93 This basically means that either a device features several chip
94 selects, or that different devices must be seen as a single
95 bigger chip. This basically doubles (or more) the total address
96 space with only a single additional wire, while still needing
97 to repeat the commands when crossing a chip boundary. The size of
98 each chip should be provided as members of the array.
99 $ref: /schemas/types.yaml#/definitions/uint64-array
104 description: Several SPI memories can be wired in parallel mode.
105 The devices are physically on a different buses but will always
106 act synchronously as each data word is spread across the
107 different memories (eg. even bits are stored in one memory, odd
108 bits in the other). This basically doubles the address space and
109 the throughput while greatly complexifying the wiring because as
110 many busses as devices must be wired. The size of each chip should
111 be provided as members of the array.
112 $ref: /schemas/types.yaml#/definitions/uint64-array
116 # The controller specific properties go here.
118 - $ref: cdns,qspi-nor-peripheral-props.yaml#
119 - $ref: samsung,spi-peripheral-props.yaml#
120 - $ref: nvidia,tegra210-quad-peripheral-props.yaml#
122 additionalProperties: true