1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung's Exynos USI (Universal Serial Interface) binding
10 - Sam Protsenko <semen.protsenko@linaro.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
14 USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C).
15 USI shares almost all internal circuits within each protocol, so only one
16 protocol can be chosen at a time. USI is modeled as a node with zero or more
17 child nodes, each representing a serial sub-node device. The mode setting
18 selects which particular function will be used.
22 pattern: "^usi@[0-9a-f]+$"
26 - samsung,exynos850-usi # for USIv2 (Exynos850, ExynosAutoV9)
43 $ref: /schemas/types.yaml#/definitions/phandle-array
46 - description: phandle to System Register syscon node
47 - description: offset of SW_CONF register for this USI controller
49 Should be phandle/offset pair. The phandle to System Register syscon node
50 (for the same domain where this USI controller resides) and the offset
51 of SW_CONF register for this USI controller.
54 $ref: /schemas/types.yaml#/definitions/uint32
56 Selects USI function (which serial protocol to use). Refer to
57 <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
62 Enable this property if underlying protocol requires the clock to be
63 continuously provided without automatic gating. As suggested by SoC
64 manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
65 multi-master mode. Usually this property is needed if USI mode is set
68 This property is optional.
72 $ref: /schemas/i2c/i2c-exynos5.yaml
73 description: Child node describing underlying I2C
76 $ref: /schemas/serial/samsung_uart.yaml
77 description: Child node describing underlying UART/serial
81 description: Child node describing underlying SPI
96 - samsung,exynos850-usi
105 - description: Bus (APB) clock
106 - description: Operating clock for UART/SPI/I2C protocol
123 samsung,clkreq-on: false
125 additionalProperties: false
129 #include <dt-bindings/interrupt-controller/arm-gic.h>
130 #include <dt-bindings/soc/samsung,exynos-usi.h>
133 compatible = "samsung,exynos850-usi";
134 reg = <0x138200c0 0x20>;
135 samsung,sysreg = <&sysreg_peri 0x1010>;
136 samsung,mode = <USI_V2_UART>;
137 samsung,clkreq-on; /* needed for UART mode */
138 #address-cells = <1>;
141 clocks = <&cmu_peri 32>, <&cmu_peri 31>;
142 clock-names = "pclk", "ipclk";
144 serial_0: serial@13820000 {
145 compatible = "samsung,exynos850-uart";
146 reg = <0x13820000 0xc0>;
147 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&cmu_peri 32>, <&cmu_peri 31>;
149 clock-names = "uart", "clk_uart_baud0";
153 hsi2c_0: i2c@13820000 {
154 compatible = "samsung,exynosautov9-hsi2c";
155 reg = <0x13820000 0xc0>;
156 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
157 #address-cells = <1>;
159 clocks = <&cmu_peri 31>, <&cmu_peri 32>;
160 clock-names = "hsi2c", "hsi2c_pclk";