Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 # Copyright (C) 2020 SiFive, Inc.
   3 %YAML 1.2
   4 ---
   5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: SiFive L2 Cache Controller
   9
  10 maintainers:
  11   - Sagar Kadam <sagar.kadam@sifive.com>
  12   - Yash Shah <yash.shah@sifive.com>
  13   - Paul Walmsley  <paul.walmsley@sifive.com>
  14
  15 description:
  16   The SiFive Level 2 Cache Controller is used to provide access to fast copies
  17   of memory for masters in a Core Complex. The Level 2 Cache Controller also
  18   acts as directory-based coherency manager.
  19   All the properties in ePAPR/DeviceTree specification applies for this platform.
  20
  21 allOf:
  22   - $ref: /schemas/cache-controller.yaml#
  23
  24 select:
  25   properties:
  26     compatible:
  27       items:
  28         - enum:
  29             - sifive,fu540-c000-ccache
  30             - sifive,fu740-c000-ccache
  31
  32   required:
  33     - compatible
  34
  35 properties:
  36   compatible:
  37     items:
  38       - enum:
  39           - sifive,fu540-c000-ccache
  40           - sifive,fu740-c000-ccache
  41       - const: cache
  42
  43   cache-block-size:
  44     const: 64
  45
  46   cache-level:
  47     const: 2
  48
  49   cache-sets:
  50     const: 1024
  51
  52   cache-size:
  53     const: 2097152
  54
  55   cache-unified: true
  56
  57   interrupts:
  58     minItems: 3
  59     maxItems: 4
  60     items:
  61       - description: DirError interrupt
  62       - description: DataError interrupt
  63       - description: DataFail interrupt
  64       - description: DirFail interrupt
  65
  66   reg:
  67     maxItems: 1
  68
  69   next-level-cache: true
  70
  71   memory-region:
  72     maxItems: 1
  73     description: |
  74       The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
  75       The reserved memory node should be defined as per the bindings in reserved-memory.txt.
  76
  77 if:
  78   properties:
  79     compatible:
  80       contains:
  81         const: sifive,fu540-c000-ccache
  82
  83 then:
  84   properties:
  85     interrupts:
  86       description: |
  87         Must contain entries for DirError, DataError and DataFail signals.
  88       maxItems: 3
  89
  90 else:
  91   properties:
  92     interrupts:
  93       description: |
  94         Must contain entries for DirError, DataError, DataFail, DirFail signals.
  95       minItems: 4
  96
  97 additionalProperties: false
  98
  99 required:
 100   - compatible
 101   - cache-block-size
 102   - cache-level
 103   - cache-sets
 104   - cache-size
 105   - cache-unified
 106   - interrupts
 107   - reg
 108
 109 examples:
 110   - |
 111     cache-controller@2010000 {
 112         compatible = "sifive,fu540-c000-ccache", "cache";
 113         cache-block-size = <64>;
 114         cache-level = <2>;
 115         cache-sets = <1024>;
 116         cache-size = <2097152>;
 117         cache-unified;
 118         reg = <0x2010000 0x1000>;
 119         interrupt-parent = <&plic0>;
 120         interrupts = <1>,
 121                      <2>,
 122                      <3>;
 123         next-level-cache = <&L25>;
 124         memory-region = <&l2_lim>;
 125     };