Documentation/devicetree/bindings/riscv/cpus.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: RISC-V bindings for 'cpus' DT nodes
   8
   9 maintainers:
  10   - Paul Walmsley <paul.walmsley@sifive.com>
  11   - Palmer Dabbelt <palmer@sifive.com>
  12
  13 description: |
  14   This document uses some terminology common to the RISC-V community
  15   that is not widely used, the definitions of which are listed here:
  16
  17   hart: A hardware execution context, which contains all the state
  18   mandated by the RISC-V ISA: a PC and some registers.  This
  19   terminology is designed to disambiguate software's view of execution
  20   contexts from any particular microarchitectural implementation
  21   strategy.  For example, an Intel laptop containing one socket with
  22   two cores, each of which has two hyperthreads, could be described as
  23   having four harts.
  24
  25 properties:
  26   compatible:
  27     oneOf:
  28       - items:
  29           - enum:
  30               - sifive,rocket0
  31               - sifive,bullet0
  32               - sifive,e5
  33               - sifive,e7
  34               - sifive,e71
  35               - sifive,u74-mc
  36               - sifive,u54
  37               - sifive,u74
  38               - sifive,u5
  39               - sifive,u7
  40               - canaan,k210
  41           - const: riscv
  42       - items:
  43           - enum:
  44               - sifive,e51
  45               - sifive,u54-mc
  46           - const: sifive,rocket0
  47           - const: riscv
  48       - const: riscv    # Simulator only
  49     description:
  50       Identifies that the hart uses the RISC-V instruction set
  51       and identifies the type of the hart.
  52
  53   mmu-type:
  54     description:
  55       Identifies the MMU address translation mode used on this
  56       hart.  These values originate from the RISC-V Privileged
  57       Specification document, available from
  58       https://riscv.org/specifications/
  59     $ref: "/schemas/types.yaml#/definitions/string"
  60     enum:
  61       - riscv,sv32
  62       - riscv,sv39
  63       - riscv,sv48
  64       - riscv,none
  65
  66   riscv,isa:
  67     description:
  68       Identifies the specific RISC-V instruction set architecture
  69       supported by the hart.  These are documented in the RISC-V
  70       User-Level ISA document, available from
  71       https://riscv.org/specifications/
  72
  73       While the isa strings in ISA specification are case
  74       insensitive, letters in the riscv,isa string must be all
  75       lowercase to simplify parsing.
  76     $ref: "/schemas/types.yaml#/definitions/string"
  77     enum:
  78       - rv64imac
  79       - rv64imafdc
  80
  81   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
  82   timebase-frequency: false
  83
  84   interrupt-controller:
  85     type: object
  86     description: Describes the CPU's local interrupt controller
  87
  88     properties:
  89       '#interrupt-cells':
  90         const: 1
  91
  92       compatible:
  93         const: riscv,cpu-intc
  94
  95       interrupt-controller: true
  96
  97     required:
  98       - '#interrupt-cells'
  99       - compatible
 100       - interrupt-controller
 101
 102   cpu-idle-states:
 103     $ref: '/schemas/types.yaml#/definitions/phandle-array'
 104     description: |
 105       List of phandles to idle state nodes supported
 106       by this hart (see ./idle-states.yaml).
 107
 108 required:
 109   - riscv,isa
 110   - interrupt-controller
 111
 112 additionalProperties: true
 113
 114 examples:
 115   - |
 116     // Example 1: SiFive Freedom U540G Development Kit
 117     cpus {
 118         #address-cells = <1>;
 119         #size-cells = <0>;
 120         timebase-frequency = <1000000>;
 121         cpu@0 {
 122                 clock-frequency = <0>;
 123                 compatible = "sifive,rocket0", "riscv";
 124                 device_type = "cpu";
 125                 i-cache-block-size = <64>;
 126                 i-cache-sets = <128>;
 127                 i-cache-size = <16384>;
 128                 reg = <0>;
 129                 riscv,isa = "rv64imac";
 130                 cpu_intc0: interrupt-controller {
 131                         #interrupt-cells = <1>;
 132                         compatible = "riscv,cpu-intc";
 133                         interrupt-controller;
 134                 };
 135         };
 136         cpu@1 {
 137                 clock-frequency = <0>;
 138                 compatible = "sifive,rocket0", "riscv";
 139                 d-cache-block-size = <64>;
 140                 d-cache-sets = <64>;
 141                 d-cache-size = <32768>;
 142                 d-tlb-sets = <1>;
 143                 d-tlb-size = <32>;
 144                 device_type = "cpu";
 145                 i-cache-block-size = <64>;
 146                 i-cache-sets = <64>;
 147                 i-cache-size = <32768>;
 148                 i-tlb-sets = <1>;
 149                 i-tlb-size = <32>;
 150                 mmu-type = "riscv,sv39";
 151                 reg = <1>;
 152                 riscv,isa = "rv64imafdc";
 153                 tlb-split;
 154                 cpu_intc1: interrupt-controller {
 155                         #interrupt-cells = <1>;
 156                         compatible = "riscv,cpu-intc";
 157                         interrupt-controller;
 158                 };
 159         };
 160     };
 161
 162   - |
 163     // Example 2: Spike ISA Simulator with 1 Hart
 164     cpus {
 165         #address-cells = <1>;
 166         #size-cells = <0>;
 167         cpu@0 {
 168                 device_type = "cpu";
 169                 reg = <0>;
 170                 compatible = "riscv";
 171                 riscv,isa = "rv64imafdc";
 172                 mmu-type = "riscv,sv48";
 173                 interrupt-controller {
 174                         #interrupt-cells = <1>;
 175                         interrupt-controller;
 176                         compatible = "riscv,cpu-intc";
 177                 };
 178         };
 179     };
 180 ...