Documentation/devicetree/bindings/riscv/cpus.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: RISC-V bindings for 'cpus' DT nodes
   8
   9 maintainers:
  10   - Paul Walmsley <paul.walmsley@sifive.com>
  11   - Palmer Dabbelt <palmer@sifive.com>
  12
  13 description: |
  14   This document uses some terminology common to the RISC-V community
  15   that is not widely used, the definitions of which are listed here:
  16
  17   hart: A hardware execution context, which contains all the state
  18   mandated by the RISC-V ISA: a PC and some registers.  This
  19   terminology is designed to disambiguate software's view of execution
  20   contexts from any particular microarchitectural implementation
  21   strategy.  For example, an Intel laptop containing one socket with
  22   two cores, each of which has two hyperthreads, could be described as
  23   having four harts.
  24
  25 properties:
  26   compatible:
  27     oneOf:
  28       - items:
  29           - enum:
  30               - sifive,rocket0
  31               - sifive,bullet0
  32               - sifive,e5
  33               - sifive,e7
  34               - sifive,e71
  35               - sifive,u74-mc
  36               - sifive,u54
  37               - sifive,u74
  38               - sifive,u5
  39               - sifive,u7
  40               - canaan,k210
  41           - const: riscv
  42       - items:
  43           - enum:
  44               - sifive,e51
  45               - sifive,u54-mc
  46           - const: sifive,rocket0
  47           - const: riscv
  48       - const: riscv    # Simulator only
  49     description:
  50       Identifies that the hart uses the RISC-V instruction set
  51       and identifies the type of the hart.
  52
  53   mmu-type:
  54     description:
  55       Identifies the MMU address translation mode used on this
  56       hart.  These values originate from the RISC-V Privileged
  57       Specification document, available from
  58       https://riscv.org/specifications/
  59     $ref: "/schemas/types.yaml#/definitions/string"
  60     enum:
  61       - riscv,sv32
  62       - riscv,sv39
  63       - riscv,sv48
  64       - riscv,none
  65
  66   riscv,isa:
  67     description:
  68       Identifies the specific RISC-V instruction set architecture
  69       supported by the hart.  These are documented in the RISC-V
  70       User-Level ISA document, available from
  71       https://riscv.org/specifications/
  72
  73       While the isa strings in ISA specification are case
  74       insensitive, letters in the riscv,isa string must be all
  75       lowercase to simplify parsing.
  76     $ref: "/schemas/types.yaml#/definitions/string"
  77     enum:
  78       - rv64imac
  79       - rv64imafdc
  80
  81   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
  82   timebase-frequency: false
  83
  84   interrupt-controller:
  85     type: object
  86     description: Describes the CPU's local interrupt controller
  87
  88     properties:
  89       '#interrupt-cells':
  90         const: 1
  91
  92       compatible:
  93         const: riscv,cpu-intc
  94
  95       interrupt-controller: true
  96
  97     required:
  98       - '#interrupt-cells'
  99       - compatible
 100       - interrupt-controller
 101
 102   cpu-idle-states:
 103     $ref: '/schemas/types.yaml#/definitions/phandle-array'
 104     items:
 105       maxItems: 1
 106     description: |
 107       List of phandles to idle state nodes supported
 108       by this hart (see ./idle-states.yaml).
 109
 110 required:
 111   - riscv,isa
 112   - interrupt-controller
 113
 114 additionalProperties: true
 115
 116 examples:
 117   - |
 118     // Example 1: SiFive Freedom U540G Development Kit
 119     cpus {
 120         #address-cells = <1>;
 121         #size-cells = <0>;
 122         timebase-frequency = <1000000>;
 123         cpu@0 {
 124                 clock-frequency = <0>;
 125                 compatible = "sifive,rocket0", "riscv";
 126                 device_type = "cpu";
 127                 i-cache-block-size = <64>;
 128                 i-cache-sets = <128>;
 129                 i-cache-size = <16384>;
 130                 reg = <0>;
 131                 riscv,isa = "rv64imac";
 132                 cpu_intc0: interrupt-controller {
 133                         #interrupt-cells = <1>;
 134                         compatible = "riscv,cpu-intc";
 135                         interrupt-controller;
 136                 };
 137         };
 138         cpu@1 {
 139                 clock-frequency = <0>;
 140                 compatible = "sifive,rocket0", "riscv";
 141                 d-cache-block-size = <64>;
 142                 d-cache-sets = <64>;
 143                 d-cache-size = <32768>;
 144                 d-tlb-sets = <1>;
 145                 d-tlb-size = <32>;
 146                 device_type = "cpu";
 147                 i-cache-block-size = <64>;
 148                 i-cache-sets = <64>;
 149                 i-cache-size = <32768>;
 150                 i-tlb-sets = <1>;
 151                 i-tlb-size = <32>;
 152                 mmu-type = "riscv,sv39";
 153                 reg = <1>;
 154                 riscv,isa = "rv64imafdc";
 155                 tlb-split;
 156                 cpu_intc1: interrupt-controller {
 157                         #interrupt-cells = <1>;
 158                         compatible = "riscv,cpu-intc";
 159                         interrupt-controller;
 160                 };
 161         };
 162     };
 163
 164   - |
 165     // Example 2: Spike ISA Simulator with 1 Hart
 166     cpus {
 167         #address-cells = <1>;
 168         #size-cells = <0>;
 169         cpu@0 {
 170                 device_type = "cpu";
 171                 reg = <0>;
 172                 compatible = "riscv";
 173                 riscv,isa = "rv64imafdc";
 174                 mmu-type = "riscv,sv48";
 175                 interrupt-controller {
 176                         #interrupt-cells = <1>;
 177                         interrupt-controller;
 178                         compatible = "riscv,cpu-intc";
 179                 };
 180         };
 181     };
 182 ...