1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sm8350-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8350/SM8450 Peripheral Authentication Service
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 Qualcomm SM8350/SM8450 SoC Peripheral Authentication Service loads and boots
14 firmware on the Qualcomm DSP Hexagon cores.
19 - qcom,sm8350-adsp-pas
20 - qcom,sm8350-cdsp-pas
21 - qcom,sm8350-slpi-pas
22 - qcom,sm8350-mpss-pas
23 - qcom,sm8450-adsp-pas
24 - qcom,sm8450-cdsp-pas
25 - qcom,sm8450-mpss-pas
26 - qcom,sm8450-slpi-pas
33 - description: XO clock
40 $ref: /schemas/types.yaml#/definitions/phandle
41 description: Reference to the AOSS side-channel message RAM.
47 description: Reference to the reserved-memory for the Hexagon core
50 $ref: /schemas/types.yaml#/definitions/string
51 description: Firmware name for the Hexagon core
58 - $ref: /schemas/remoteproc/qcom,pas-common.yaml#
63 - qcom,sm8350-adsp-pas
64 - qcom,sm8350-cdsp-pas
65 - qcom,sm8350-slpi-pas
66 - qcom,sm8450-adsp-pas
67 - qcom,sm8450-cdsp-pas
68 - qcom,sm8450-slpi-pas
86 - qcom,sm8350-mpss-pas
87 - qcom,sm8450-mpss-pas
92 - description: CX power domain
93 - description: MSS power domain
103 - qcom,sm8350-adsp-pas
104 - qcom,sm8350-slpi-pas
105 - qcom,sm8450-adsp-pas
106 - qcom,sm8450-slpi-pas
111 - description: LCX power domain
112 - description: LMX power domain
122 - qcom,sm8350-cdsp-pas
123 - qcom,sm8450-cdsp-pas
128 - description: CX power domain
129 - description: MXC power domain
135 unevaluatedProperties: false
139 #include <dt-bindings/clock/qcom,rpmh.h>
140 #include <dt-bindings/interrupt-controller/irq.h>
141 #include <dt-bindings/mailbox/qcom-ipcc.h>
142 #include <dt-bindings/power/qcom,rpmhpd.h>
144 remoteproc@30000000 {
145 compatible = "qcom,sm8450-adsp-pas";
146 reg = <0x030000000 0x100>;
148 clocks = <&rpmhcc RPMH_CXO_CLK>;
151 firmware-name = "qcom/sm8450/adsp.mbn";
153 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
154 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
155 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
156 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
157 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
158 interrupt-names = "wdog", "fatal", "ready",
159 "handover", "stop-ack";
161 memory-region = <&adsp_mem>;
163 power-domains = <&rpmhpd RPMHPD_LCX>,
164 <&rpmhpd RPMHPD_LMX>;
165 power-domain-names = "lcx", "lmx";
167 qcom,qmp = <&aoss_qmp>;
168 qcom,smem-states = <&smp2p_adsp_out 0>;
169 qcom,smem-state-names = "stop";
172 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
173 IPCC_MPROC_SIGNAL_GLINK_QMP
174 IRQ_TYPE_EDGE_RISING>;
175 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>;
178 qcom,remote-pid = <2>;