1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek MT8183 Pin Controller
10 - Sean Wang <sean.wang@kernel.org>
13 The MediaTek's MT8183 Pin controller is used to control SoC pins.
17 const: mediatek,mt8183-pinctrl
41 Number of cells in GPIO specifier. Since the generic GPIO
42 binding is used, the amount of cells must be specified as 2. See the below
43 mentioned gpio binding representation for description of particular cells.
49 GPIO valid number range.
51 interrupt-controller: true
60 - $ref: "pinctrl.yaml#"
72 additionalProperties: false
76 additionalProperties: false
78 A pinctrl node should contain at least one subnodes representing the
79 pinctrl groups available on the machine. Each subnode will list the
80 pins it needs, and how they should be configured, with regard to muxer
81 configuration, pullups, drive strength, input enable/disable and input
83 $ref: "/schemas/pinctrl/pincfg-node.yaml"
88 integer array, represents gpio pin number and mux setting.
89 Supported pin number and mux varies for different SoCs, and are
90 defined as macros in <soc>-pinfunc.h directly.
106 input-schmitt-enable: true
108 input-schmitt-disable: true
111 enum: [2, 4, 6, 8, 10, 12, 14, 16]
113 mediatek,drive-strength-adv:
115 Describe the specific driving setup property.
116 For I2C pins, the existing generic driving setup can only support
117 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
118 can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
119 driving setup, the existing generic setup will be disabled.
120 The specific driving setup is controlled by E1E0EN.
121 When E1=0/E0=0, the strength is 0.125mA.
122 When E1=0/E0=1, the strength is 0.25mA.
123 When E1=1/E0=0, the strength is 0.5mA.
124 When E1=1/E0=1, the strength is 1mA.
125 EN is used to enable or disable the specific driving setup.
126 Valid arguments are described as below:
127 0: (E1, E0, EN) = (0, 0, 0)
128 1: (E1, E0, EN) = (0, 0, 1)
129 2: (E1, E0, EN) = (0, 1, 0)
130 3: (E1, E0, EN) = (0, 1, 1)
131 4: (E1, E0, EN) = (1, 0, 0)
132 5: (E1, E0, EN) = (1, 0, 1)
133 6: (E1, E0, EN) = (1, 1, 0)
134 7: (E1, E0, EN) = (1, 1, 1)
135 So the valid arguments are from 0 to 7.
136 $ref: /schemas/types.yaml#/definitions/uint32
137 enum: [0, 1, 2, 3, 4, 5, 6, 7]
139 mediatek,pull-up-adv:
141 Pull up setings for 2 pull resistors, R0 and R1. User can
142 configure those special pins. Valid arguments are described as below:
143 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
144 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
145 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
146 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
147 $ref: /schemas/types.yaml#/definitions/uint32
150 mediatek,pull-down-adv:
152 Pull down settings for 2 pull resistors, R0 and R1. User can
153 configure those special pins. Valid arguments are described as below:
154 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
155 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
156 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
157 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
158 $ref: /schemas/types.yaml#/definitions/uint32
163 An integer describing the steps for output level shifter duty
164 cycle when asserted (high pulse width adjustment). Valid arguments
166 $ref: /schemas/types.yaml#/definitions/uint32
170 An integer describing the steps for input level shifter duty cycle
171 when asserted (high pulse width adjustment). Valid arguments are
173 $ref: /schemas/types.yaml#/definitions/uint32
178 additionalProperties: false
182 #include <dt-bindings/interrupt-controller/irq.h>
183 #include <dt-bindings/interrupt-controller/arm-gic.h>
184 #include <dt-bindings/pinctrl/mt8183-pinfunc.h>
187 #address-cells = <2>;
190 pio: pinctrl@10005000 {
191 compatible = "mediatek,mt8183-pinctrl";
192 reg = <0 0x10005000 0 0x1000>,
193 <0 0x11f20000 0 0x1000>,
194 <0 0x11e80000 0 0x1000>,
195 <0 0x11e70000 0 0x1000>,
196 <0 0x11e90000 0 0x1000>,
197 <0 0x11d30000 0 0x1000>,
198 <0 0x11d20000 0 0x1000>,
199 <0 0x11c50000 0 0x1000>,
200 <0 0x11f30000 0 0x1000>,
201 <0 0x1000b000 0 0x1000>;
202 reg-names = "iocfg0", "iocfg1", "iocfg2",
203 "iocfg3", "iocfg4", "iocfg5",
204 "iocfg6", "iocfg7", "iocfg8",
208 gpio-ranges = <&pio 0 0 192>;
209 interrupt-controller;
210 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
211 #interrupt-cells = <2>;
213 i2c0_pins_a: i2c0-pins {
215 pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
216 <PINMUX_GPIO49__FUNC_SDA5>;
217 mediatek,pull-up-adv = <3>;
218 mediatek,drive-strength-adv = <7>;
222 i2c1_pins_a: i2c1-pins {
224 pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
225 <PINMUX_GPIO51__FUNC_SDA3>;
226 mediatek,pull-down-adv = <2>;
227 mediatek,drive-strength-adv = <4>;