1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
16 compatible PHYs, the second cell in the PHY specifier identifies the
17 PHY id, which is interpreted as follows::
21 For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
22 'usbdrd_phy' nodes should have numbered alias in the aliases node, in the
23 form of usbdrdphyN, N = 0, 1... (depending on number of controllers).
28 - samsung,exynos5250-usbdrd-phy
29 - samsung,exynos5420-usbdrd-phy
30 - samsung,exynos5433-usbdrd-phy
31 - samsung,exynos7-usbdrd-phy
42 - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used
44 - PHY reference clock (usually crystal clock), used for PHY operations,
45 associated by phy name. It is used to determine bit values for clock
46 settings register. For Exynos5420 this is given as 'sclk_usbphy30'
53 $ref: /schemas/graph.yaml#/properties/port
55 Any connector to the data bus of this controller should be modelled using
56 the OF graph bindings specified.
62 $ref: /schemas/types.yaml#/definitions/phandle
64 Phandle to PMU system controller interface.
72 VBUS Boost 5V power source.
88 - samsung,exynos5433-usbdrd-phy
89 - samsung,exynos7-usbdrd-phy
112 additionalProperties: false
116 #include <dt-bindings/clock/exynos5420.h>
119 compatible = "samsung,exynos5420-usbdrd-phy";
120 reg = <0x12100000 0x100>;
122 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
123 clock-names = "phy", "ref";
124 samsung,pmu-syscon = <&pmu_system_controller>;
125 vbus-supply = <&usb300_vbus_reg>;