Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
   5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   6
   7 title: Cadence Torrent SD0801 PHY binding for DisplayPort
   8
   9 description:
  10   This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
  11   hardware included with the Cadence MHDP DisplayPort controller.
  12
  13 maintainers:
  14   - Swapnil Jakhade <sjakhade@cadence.com>
  15   - Yuti Amonkar <yamonkar@cadence.com>
  16
  17 properties:
  18   compatible:
  19     enum:
  20       - cdns,torrent-phy
  21       - ti,j721e-serdes-10g
  22
  23   '#address-cells':
  24     const: 1
  25
  26   '#size-cells':
  27     const: 0
  28
  29   clocks:
  30     maxItems: 1
  31     description:
  32       PHY reference clock. Must contain an entry in clock-names.
  33
  34   clock-names:
  35     const: refclk
  36
  37   reg:
  38     minItems: 1
  39     maxItems: 2
  40     items:
  41       - description: Offset of the Torrent PHY configuration registers.
  42       - description: Offset of the DPTX PHY configuration registers.
  43
  44   reg-names:
  45     minItems: 1
  46     maxItems: 2
  47     items:
  48       - const: torrent_phy
  49       - const: dptx_phy
  50
  51   resets:
  52     maxItems: 1
  53     description:
  54       Torrent PHY reset.
  55       See Documentation/devicetree/bindings/reset/reset.txt
  56
  57 patternProperties:
  58   '^phy@[0-7]+$':
  59     type: object
  60     description:
  61       Each group of PHY lanes with a single master lane should be represented as a sub-node.
  62     properties:
  63       reg:
  64         description:
  65           The master lane number. This is the lowest numbered lane in the lane group.
  66
  67       resets:
  68         minItems: 1
  69         maxItems: 4
  70         description:
  71           Contains list of resets, one per lane, to get all the link lanes out of reset.
  72
  73       "#phy-cells":
  74         const: 0
  75
  76       cdns,phy-type:
  77         description:
  78           Specifies the type of PHY for which the group of PHY lanes is used.
  79           Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
  80         allOf:
  81           - $ref: /schemas/types.yaml#/definitions/uint32
  82           - enum: [1, 2, 3, 4, 5, 6]
  83
  84       cdns,num-lanes:
  85         description:
  86           Number of DisplayPort lanes.
  87         allOf:
  88           - $ref: /schemas/types.yaml#/definitions/uint32
  89           - enum: [1, 2, 4]
  90         default: 4
  91
  92       cdns,max-bit-rate:
  93         description:
  94           Maximum DisplayPort link bit rate to use, in Mbps
  95         allOf:
  96           - $ref: /schemas/types.yaml#/definitions/uint32
  97           - enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
  98         default: 8100
  99
 100     required:
 101       - reg
 102       - resets
 103       - "#phy-cells"
 104       - cdns,phy-type
 105
 106     additionalProperties: false
 107
 108 required:
 109   - compatible
 110   - "#address-cells"
 111   - "#size-cells"
 112   - clocks
 113   - clock-names
 114   - reg
 115   - reg-names
 116   - resets
 117
 118 additionalProperties: false
 119
 120 examples:
 121   - |
 122     #include <dt-bindings/phy/phy.h>
 123     torrent_phy: torrent-phy@f0fb500000 {
 124           compatible = "cdns,torrent-phy";
 125           reg = <0xf0 0xfb500000 0x0 0x00100000>,
 126                 <0xf0 0xfb030a00 0x0 0x00000040>;
 127           reg-names = "torrent_phy", "dptx_phy";
 128           resets = <&phyrst 0>;
 129           clocks = <&ref_clk>;
 130           clock-names = "refclk";
 131           #address-cells = <1>;
 132           #size-cells = <0>;
 133           torrent_phy_dp: phy@0 {
 134                     reg = <0>;
 135                     resets = <&phyrst 1>, <&phyrst 2>,
 136                              <&phyrst 3>, <&phyrst 4>;
 137                     #phy-cells = <0>;
 138                     cdns,phy-type = <PHY_TYPE_DP>;
 139                     cdns,num-lanes = <4>;
 140                     cdns,max-bit-rate = <8100>;
 141           };
 142     };
 143 ...