1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PCIe Root Port Bridge Controller
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: microchip,pcie-host-1.0 # PolarFire
30 Fabric Interface Controllers, FICs, are the interface between the FPGA
31 fabric and the core complex on PolarFire SoC. The FICs require two clocks,
32 one from each side of the interface. The "FIC clocks" described by this
33 property are on the core complex side & communication through a FIC is not
34 possible unless it's corresponding clock is enabled. A clock must be
35 enabled for each of the interfaces the root port is connected through.
36 This could in theory be all 4 interfaces, one interface or any combination
40 - description: FIC0's clock
41 - description: FIC1's clock
42 - description: FIC2's clock
43 - description: FIC3's clock
47 As any FIC connection combination is possible, the names should match the
48 order in the clocks property and take the form "ficN" where N is a number
58 - description: PCIe host controller
59 - description: builtin MSI controller
75 description: Identifies the node as an MSI controller.
78 description: MSI controller the device is capable of using.
89 interrupt-controller: true
94 - interrupt-controller
96 additionalProperties: false
107 unevaluatedProperties: false
112 #address-cells = <2>;
114 pcie0: pcie@2030000000 {
115 compatible = "microchip,pcie-host-1.0";
116 reg = <0x0 0x70000000 0x0 0x08000000>,
117 <0x0 0x43000000 0x0 0x00010000>;
118 reg-names = "cfg", "apb";
120 #address-cells = <3>;
122 #interrupt-cells = <1>;
124 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
125 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
126 <0 0 0 2 &pcie_intc0 1>,
127 <0 0 0 3 &pcie_intc0 2>,
128 <0 0 0 4 &pcie_intc0 3>;
129 interrupt-parent = <&plic0>;
130 msi-parent = <&pcie0>;
132 bus-range = <0x00 0x7f>;
133 ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
134 pcie_intc0: interrupt-controller {
135 #address-cells = <0>;
136 #interrupt-cells = <1>;
137 interrupt-controller;