Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Microchip PCIe Root Port Bridge Controller Device Tree Bindings
   8
   9 maintainers:
  10   - Daire McNamara <daire.mcnamara@microchip.com>
  11
  12 allOf:
  13   - $ref: /schemas/pci/pci-bus.yaml#
  14   - $ref: /schemas/interrupt-controller/msi-controller.yaml#
  15
  16 properties:
  17   compatible:
  18     const: microchip,pcie-host-1.0 # PolarFire
  19
  20   reg:
  21     maxItems: 2
  22
  23   reg-names:
  24     items:
  25       - const: cfg
  26       - const: apb
  27
  28   interrupts:
  29     minItems: 1
  30     items:
  31       - description: PCIe host controller
  32       - description: builtin MSI controller
  33
  34   interrupt-names:
  35     minItems: 1
  36     items:
  37       - const: pcie
  38       - const: msi
  39
  40   ranges:
  41     maxItems: 1
  42
  43   msi-controller:
  44     description: Identifies the node as an MSI controller.
  45
  46   msi-parent:
  47     description: MSI controller the device is capable of using.
  48
  49   interrupt-controller:
  50     type: object
  51     properties:
  52       '#address-cells':
  53         const: 0
  54
  55       '#interrupt-cells':
  56         const: 1
  57
  58       interrupt-controller: true
  59
  60     required:
  61       - '#address-cells'
  62       - '#interrupt-cells'
  63       - interrupt-controller
  64
  65     additionalProperties: false
  66
  67 required:
  68   - reg
  69   - reg-names
  70   - "#interrupt-cells"
  71   - interrupts
  72   - interrupt-map-mask
  73   - interrupt-map
  74   - msi-controller
  75
  76 unevaluatedProperties: false
  77
  78 examples:
  79   - |
  80     soc {
  81             #address-cells = <2>;
  82             #size-cells = <2>;
  83             pcie0: pcie@2030000000 {
  84                     compatible = "microchip,pcie-host-1.0";
  85                     reg = <0x0 0x70000000 0x0 0x08000000>,
  86                           <0x0 0x43000000 0x0 0x00010000>;
  87                     reg-names = "cfg", "apb";
  88                     device_type = "pci";
  89                     #address-cells = <3>;
  90                     #size-cells = <2>;
  91                     #interrupt-cells = <1>;
  92                     interrupts = <119>;
  93                     interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  94                     interrupt-map = <0 0 0 1 &pcie_intc0 0>,
  95                                     <0 0 0 2 &pcie_intc0 1>,
  96                                     <0 0 0 3 &pcie_intc0 2>,
  97                                     <0 0 0 4 &pcie_intc0 3>;
  98                     interrupt-parent = <&plic0>;
  99                     msi-parent = <&pcie0>;
 100                     msi-controller;
 101                     bus-range = <0x00 0x7f>;
 102                     ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
 103                     pcie_intc0: interrupt-controller {
 104                         #address-cells = <0>;
 105                         #interrupt-cells = <1>;
 106                         interrupt-controller;
 107                     };
 108             };
 109     };