1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Gen3 PCIe controller on MediaTek SoCs
10 - Jianjun Wang <jianjun.wang@mediatek.com>
13 PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
14 and compatible with Gen2, Gen1 speed.
16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware
17 block diagram is as follows:
27 |0|1|2|3|4|5|6|7| (PCIe intc)
31 +-------+ +------+ +-----------+
33 +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
34 |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets)
35 +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
36 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
37 | | | | | | | | | | | | (MSI vectors)
38 | | | | | | | | | | | |
40 (MSI SET0) (MSI SET1) ... (MSI SET7)
42 With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
43 each set has its own address for MSI message, and supports 32 MSI vectors
44 to generate interrupt.
47 - $ref: /schemas/pci/pci-bus.yaml#
51 const: mediatek,mt8192-pcie
92 assigned-clock-parents:
105 interrupt-controller:
106 description: Interrupt controller node for handling legacy PCI interrupts.
113 interrupt-controller: true
118 - interrupt-controller
120 additionalProperties: false
130 - interrupt-controller
132 unevaluatedProperties: false
136 #include <dt-bindings/interrupt-controller/arm-gic.h>
137 #include <dt-bindings/interrupt-controller/irq.h>
140 #address-cells = <2>;
143 pcie: pcie@11230000 {
144 compatible = "mediatek,mt8192-pcie";
146 #address-cells = <3>;
148 reg = <0x00 0x11230000 0x00 0x4000>;
149 reg-names = "pcie-mac";
150 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
151 bus-range = <0x00 0xff>;
152 ranges = <0x82000000 0x00 0x12000000 0x00
153 0x12000000 0x00 0x1000000>;
154 clocks = <&infracfg 44>,
160 clock-names = "pl_250m", "tl_26m", "tl_96m",
161 "tl_32k", "peri_26m", "top_133m";
162 assigned-clocks = <&topckgen 50>;
163 assigned-clock-parents = <&topckgen 91>;
166 phy-names = "pcie-phy";
168 resets = <&infracfg_rst 2>,
170 reset-names = "phy", "mac";
172 #interrupt-cells = <1>;
173 interrupt-map-mask = <0 0 0 0x7>;
174 interrupt-map = <0 0 0 1 &pcie_intc 0>,
175 <0 0 0 2 &pcie_intc 1>,
176 <0 0 0 3 &pcie_intc 2>,
177 <0 0 0 4 &pcie_intc 3>;
178 pcie_intc: interrupt-controller {
179 #address-cells = <0>;
180 #interrupt-cells = <1>;
181 interrupt-controller;