Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller)
   8
   9 maintainers:
  10   - Grygorii Strashko <grygorii.strashko@ti.com>
  11   - Sekhar Nori <nsekhar@ti.com>
  12
  13 description:
  14   The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
  15   (one external) and provides Ethernet packet communication for the device.
  16   The TI AM642x SoC Gigabit Ethernet MAC (CPSW3G NUSS) has three ports
  17   (two external) and provides Ethernet packet communication and switching.
  18
  19   The internal Communications Port Programming Interface (CPPI5) (Host port 0).
  20   Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
  21   and one RX channels and operating by NAVSS Unified DMA  Peripheral Root
  22   Complex (UDMA-P) controller.
  23
  24   CPSWxG features
  25   updated Address Lookup Engine (ALE).
  26   priority level Quality Of Service (QOS) support (802.1p)
  27   Support for Audio/Video Bridging (P802.1Qav/D6.0)
  28   Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
  29   Flow Control (802.3x) Support
  30   Time Sensitive Network Support
  31   IEEE P902.3br/D2.0 Interspersing Express Traffic
  32   IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic
  33   Configurable number of addresses plus VLANs
  34   Configurable number of classifier/policers
  35   VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on
  36   ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
  37   RX/TX csum offload
  38   Management Data Input/Output (MDIO) interface for PHYs management
  39   RMII/RGMII Interfaces support
  40   new version of Common Platform Time Sync (CPTS)
  41
  42   The CPSWxG NUSS is integrated into
  43     device MCU domain named MCU_CPSW0 on AM654x/J721E SoC.
  44     device MAIN domain named CPSW0 on AM642x SoC.
  45
  46   Specifications can be found at
  47     https://www.ti.com/lit/pdf/spruid7
  48     https://www.ti.com/lit/zip/spruil1
  49     https://www.ti.com/lit/pdf/spruim2
  50
  51 properties:
  52   "#address-cells": true
  53   "#size-cells": true
  54
  55   compatible:
  56     enum:
  57       - ti,am654-cpsw-nuss
  58       - ti,j7200-cpswxg-nuss
  59       - ti,j721e-cpsw-nuss
  60       - ti,j721e-cpswxg-nuss
  61       - ti,am642-cpsw-nuss
  62
  63   reg:
  64     maxItems: 1
  65     description:
  66       The physical base address and size of full the CPSWxG NUSS IO range
  67
  68   reg-names:
  69     items:
  70       - const: cpsw_nuss
  71
  72   ranges: true
  73
  74   dma-coherent: true
  75
  76   clocks:
  77     maxItems: 1
  78     description: CPSWxG NUSS functional clock
  79
  80   clock-names:
  81     items:
  82       - const: fck
  83
  84   assigned-clock-parents: true
  85
  86   assigned-clocks: true
  87
  88   power-domains:
  89     maxItems: 1
  90
  91   dmas:
  92     maxItems: 9
  93
  94   dma-names:
  95     items:
  96       - const: tx0
  97       - const: tx1
  98       - const: tx2
  99       - const: tx3
 100       - const: tx4
 101       - const: tx5
 102       - const: tx6
 103       - const: tx7
 104       - const: rx
 105
 106   ethernet-ports:
 107     type: object
 108     properties:
 109       '#address-cells':
 110         const: 1
 111       '#size-cells':
 112         const: 0
 113
 114     patternProperties:
 115       "^port@[1-8]$":
 116         type: object
 117         description: CPSWxG NUSS external ports
 118
 119         $ref: ethernet-controller.yaml#
 120         unevaluatedProperties: false
 121
 122         properties:
 123           reg:
 124             minimum: 1
 125             maximum: 8
 126             description: CPSW port number
 127
 128           phys:
 129             maxItems: 1
 130             description: phandle on phy-gmii-sel PHY
 131
 132           label:
 133             description: label associated with this port
 134
 135           ti,mac-only:
 136             $ref: /schemas/types.yaml#/definitions/flag
 137             description:
 138               Specifies the port works in mac-only mode.
 139
 140           ti,syscon-efuse:
 141             $ref: /schemas/types.yaml#/definitions/phandle-array
 142             items:
 143               - items:
 144                   - description: Phandle to the system control device node which
 145                       provides access to efuse
 146                   - description: offset to efuse registers???
 147             description:
 148               Phandle to the system control device node which provides access
 149               to efuse IO range with MAC addresses
 150
 151         required:
 152           - reg
 153           - phys
 154
 155     additionalProperties: false
 156
 157 patternProperties:
 158   "^mdio@[0-9a-f]+$":
 159     type: object
 160     $ref: "ti,davinci-mdio.yaml#"
 161
 162     description:
 163       CPSW MDIO bus.
 164
 165   "^cpts@[0-9a-f]+":
 166     type: object
 167     $ref: "ti,k3-am654-cpts.yaml#"
 168     description:
 169       CPSW Common Platform Time Sync (CPTS) module.
 170
 171 required:
 172   - compatible
 173   - reg
 174   - reg-names
 175   - ranges
 176   - clocks
 177   - clock-names
 178   - power-domains
 179   - dmas
 180   - dma-names
 181   - '#address-cells'
 182   - '#size-cells'
 183
 184 allOf:
 185   - if:
 186       not:
 187         properties:
 188           compatible:
 189             contains:
 190               const: ti,j721e-cpswxg-nuss
 191     then:
 192       properties:
 193         ethernet-ports:
 194           patternProperties:
 195             "^port@[5-8]$": false
 196             "^port@[1-4]$":
 197               properties:
 198                 reg:
 199                   minimum: 1
 200                   maximum: 4
 201
 202   - if:
 203       not:
 204         properties:
 205           compatible:
 206             contains:
 207               enum:
 208                 - ti,j721e-cpswxg-nuss
 209                 - ti,j7200-cpswxg-nuss
 210     then:
 211       properties:
 212         ethernet-ports:
 213           patternProperties:
 214             "^port@[3-8]$": false
 215             "^port@[1-2]$":
 216               properties:
 217                 reg:
 218                   minimum: 1
 219                   maximum: 2
 220
 221 additionalProperties: false
 222
 223 examples:
 224   - |
 225     #include <dt-bindings/pinctrl/k3.h>
 226     #include <dt-bindings/soc/ti,sci_pm_domain.h>
 227     #include <dt-bindings/net/ti-dp83867.h>
 228     #include <dt-bindings/interrupt-controller/irq.h>
 229     #include <dt-bindings/interrupt-controller/arm-gic.h>
 230
 231     bus {
 232         #address-cells = <2>;
 233         #size-cells = <2>;
 234
 235         mcu_cpsw: ethernet@46000000 {
 236             compatible = "ti,am654-cpsw-nuss";
 237             #address-cells = <2>;
 238             #size-cells = <2>;
 239             reg = <0x0 0x46000000 0x0 0x200000>;
 240             reg-names = "cpsw_nuss";
 241             ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
 242             dma-coherent;
 243             clocks = <&k3_clks 5 10>;
 244             clock-names = "fck";
 245             power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
 246             pinctrl-names = "default";
 247             pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
 248
 249             dmas = <&mcu_udmap 0xf000>,
 250                    <&mcu_udmap 0xf001>,
 251                    <&mcu_udmap 0xf002>,
 252                    <&mcu_udmap 0xf003>,
 253                    <&mcu_udmap 0xf004>,
 254                    <&mcu_udmap 0xf005>,
 255                    <&mcu_udmap 0xf006>,
 256                    <&mcu_udmap 0xf007>,
 257                    <&mcu_udmap 0x7000>;
 258             dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
 259                         "rx";
 260
 261             ethernet-ports {
 262                 #address-cells = <1>;
 263                 #size-cells = <0>;
 264
 265                 cpsw_port1: port@1 {
 266                     reg = <1>;
 267                     ti,mac-only;
 268                     label = "port1";
 269                     ti,syscon-efuse = <&mcu_conf 0x200>;
 270                     phys = <&phy_gmii_sel 1>;
 271
 272                     phy-mode = "rgmii-rxid";
 273                     phy-handle = <&phy0>;
 274                 };
 275             };
 276
 277             davinci_mdio: mdio@f00 {
 278                 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 279                 reg = <0x0 0xf00 0x0 0x100>;
 280                 #address-cells = <1>;
 281                 #size-cells = <0>;
 282                 clocks = <&k3_clks 5 10>;
 283                 clock-names = "fck";
 284                 bus_freq = <1000000>;
 285
 286                 phy0: ethernet-phy@0 {
 287                     reg = <0>;
 288                     ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 289                     ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 290                 };
 291             };
 292         };
 293
 294         cpts@3d000 {
 295              compatible = "ti,am65-cpts";
 296              reg = <0x0 0x3d000 0x0 0x400>;
 297              clocks = <&k3_clks 18 2>;
 298              clock-names = "cpts";
 299              interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
 300              interrupt-names = "cpts";
 301              ti,cpts-ext-ts-inputs = <4>;
 302              ti,cpts-periodic-outputs = <2>;
 303         };
 304     };