1 MediaTek Frame Engine Ethernet controller
2 =========================================
4 The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
5 have dual GMAC each represented by a child node..
7 * Ethernet controller node
10 - compatible: Should be
11 "mediatek,mt2701-eth": for MT2701 SoC
12 "mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC
13 "mediatek,mt7622-eth": for MT7622 SoC
14 - reg: Address and length of the register set for the device
15 - interrupts: Should contain the three frame engines interrupts in numeric
16 order. These are fe_int0, fe_int1 and fe_int2.
17 - clocks: the clock used by the core
18 - clock-names: the names of the clock listed in the clocks property. These are
19 "ethif", "esw", "gp2", "gp1" : For MT2701 and MT7623 SoC
20 "ethif", "esw", "gp0", "gp1", "gp2", "sgmii_tx250m", "sgmii_rx250m",
21 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" : For MT7622 SoC
22 - power-domains: phandle to the power domain that the ethernet is part of
23 - resets: Should contain a phandle to the ethsys reset signal
24 - reset-names: Should contain the reset signal name "eth"
25 - mediatek,ethsys: phandle to the syscon node that handles the port setup
26 - mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup
27 which is required for those SoCs equipped with SGMII such as MT7622 SoC.
28 - mediatek,pctl: phandle to the syscon node that handles the ports slew rate
32 - interrupt-parent: Should be the phandle for the interrupt controller
33 that services interrupts for this device
37 - compatible: Should be "mediatek,eth-mac"
38 - reg: The number of the MAC
39 - phy-handle: see ethernet.txt file in the same directory and
40 the phy-mode "trgmii" required being provided when reg
41 is equal to 0 and the MAC uses fixed-link to connect
42 with internal switch such as MT7530.
46 eth: ethernet@1b100000 {
47 compatible = "mediatek,mt7623-eth";
48 reg = <0 0x1b100000 0 0x20000>;
49 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
50 <ðsys CLK_ETHSYS_ESW>,
51 <ðsys CLK_ETHSYS_GP2>,
52 <ðsys CLK_ETHSYS_GP1>;
53 clock-names = "ethif", "esw", "gp2", "gp1";
54 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
55 GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
56 GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
57 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
58 resets = <ðsys MT2701_ETHSYS_ETH_RST>;
60 mediatek,ethsys = <ðsys>;
61 mediatek,pctl = <&syscfg_pctl_a>;
66 compatible = "mediatek,eth-mac";
72 compatible = "mediatek,eth-mac";
78 phy0: ethernet-phy@0 {
83 phy1: ethernet-phy@1 {