1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/cdns,macb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence MACB/GEM Ethernet controller
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
23 - cdns,zynq-gem # Xilinx Zynq-7xxx SoC
24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
25 - const: cdns,gem # Generic
30 - xlnx,versal-gem # Xilinx Versal
31 - xlnx,zynq-gem # Xilinx Zynq-7xxx SoC
32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
33 - const: cdns,gem # Generic
37 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs
38 - cdns,sam9x60-macb # Microchip sam9x60 SoC
39 - microchip,mpfs-macb # Microchip PolarFire SoC
40 - const: cdns,macb # Generic
44 - atmel,sama5d3-macb # 10/100Mbit IP on Atmel sama5d3 SoCs
46 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs.
47 - const: cdns,macb # Generic
50 - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs
51 - atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs
52 - atmel,sama5d3-gem # Gigabit IP on Atmel sama5d3 SoCs
53 - atmel,sama5d4-gem # GEM IP (10/100) on Atmel sama5d4 SoCs
54 - cdns,np4-macb # NP4 SoC devices
55 - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface
56 - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface
57 - sifive,fu540-c000-gem # SiFive FU540-C000 SoC
65 - description: Basic register set
66 - description: GEMGXL Management block registers on SiFive FU540-C000 SoC
71 description: One interrupt per available hardware queue
80 - enum: [ ether_clk, hclk, pclk ]
81 - enum: [ hclk, pclk ]
83 - enum: [ rx_clk, tsu_clk ]
86 local-mac-address: true
98 Recommended with ZynqMP, specify reset control for this
99 controller instance with zynqmp-reset driver.
121 Node containing PHY children. If this node is not present, then PHYs will
125 "^ethernet-phy@[0-9a-f]$":
127 $ref: ethernet-phy.yaml#
135 Indicates that the hardware supports waking up via magic packet.
137 unevaluatedProperties: false
148 - $ref: ethernet-controller.yaml#
155 const: sifive,fu540-c000-gem
161 unevaluatedProperties: false
165 macb0: ethernet@fffc4000 {
166 compatible = "cdns,macb";
167 reg = <0xfffc4000 0x4000>;
170 local-mac-address = [3a 0e 03 04 05 06];
171 clock-names = "pclk", "hclk", "tx_clk";
172 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
173 #address-cells = <1>;
178 reset-gpios = <&pioE 6 1>;
183 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
184 #include <dt-bindings/power/xlnx-zynqmp-power.h>
185 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
186 #include <dt-bindings/phy/phy.h>
189 #address-cells = <2>;
191 gem1: ethernet@ff0c0000 {
192 compatible = "xlnx,zynqmp-gem", "cdns,gem";
193 interrupt-parent = <&gic>;
194 interrupts = <0 59 4>, <0 59 4>;
195 reg = <0x0 0xff0c0000 0x0 0x1000>;
196 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
197 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
198 <&zynqmp_clk GEM_TSU>;
199 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
200 #address-cells = <1>;
202 iommus = <&smmu 0x875>;
203 power-domains = <&zynqmp_firmware PD_ETH_1>;
204 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
205 reset-names = "gem1_rst";
207 phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>;