1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra124 SoC External Memory Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
15 sent from the memory controller.
19 const: nvidia,tegra124-emc
26 - description: external memory clock
32 nvidia,memory-controller:
33 $ref: /schemas/types.yaml#/definitions/phandle
35 phandle of the memory controller node
38 "^emc-timings-[0-9]+$":
42 $ref: /schemas/types.yaml#/definitions/uint32
44 value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
45 this timing set is used for
53 external memory clock rate in Hz
57 nvidia,emc-auto-cal-config:
58 $ref: /schemas/types.yaml#/definitions/uint32
60 value of the EMC_AUTO_CAL_CONFIG register for this set of
63 nvidia,emc-auto-cal-config2:
64 $ref: /schemas/types.yaml#/definitions/uint32
66 value of the EMC_AUTO_CAL_CONFIG2 register for this set of
69 nvidia,emc-auto-cal-config3:
70 $ref: /schemas/types.yaml#/definitions/uint32
72 value of the EMC_AUTO_CAL_CONFIG3 register for this set of
75 nvidia,emc-auto-cal-interval:
77 - $ref: /schemas/types.yaml#/definitions/uint32
79 pad calibration interval in microseconds
83 nvidia,emc-bgbias-ctl0:
84 $ref: /schemas/types.yaml#/definitions/uint32
86 value of the EMC_BGBIAS_CTL0 register for this set of timings
89 $ref: /schemas/types.yaml#/definitions/uint32
91 value of the EMC_CFG register for this set of timings
94 $ref: /schemas/types.yaml#/definitions/uint32
96 value of the EMC_CFG_2 register for this set of timings
98 nvidia,emc-ctt-term-ctrl:
99 $ref: /schemas/types.yaml#/definitions/uint32
101 value of the EMC_CTT_TERM_CTRL register for this set of timings
104 $ref: /schemas/types.yaml#/definitions/uint32
106 value of the EMC_MRW register for this set of timings
109 $ref: /schemas/types.yaml#/definitions/uint32
111 value of the EMC_MRW2 register for this set of timings
114 $ref: /schemas/types.yaml#/definitions/uint32
116 value of the EMC_MRW4 register for this set of timings
118 nvidia,emc-mode-reset:
119 $ref: /schemas/types.yaml#/definitions/uint32
121 reset value of the EMC_MRS register for this set of timings
123 nvidia,emc-mrs-wait-cnt:
124 $ref: /schemas/types.yaml#/definitions/uint32
126 value of the EMR_MRS_WAIT_CNT register for this set of timings
128 nvidia,emc-sel-dpd-ctrl:
129 $ref: /schemas/types.yaml#/definitions/uint32
131 value of the EMC_SEL_DPD_CTRL register for this set of timings
133 nvidia,emc-xm2dqspadctrl2:
134 $ref: /schemas/types.yaml#/definitions/uint32
136 value of the EMC_XM2DQSPADCTRL2 register for this set of timings
138 nvidia,emc-zcal-cnt-long:
140 - $ref: /schemas/types.yaml#/definitions/uint32
142 number of EMC clocks to wait before issuing any commands after
147 nvidia,emc-zcal-interval:
148 $ref: /schemas/types.yaml#/definitions/uint32
150 value of the EMC_ZCAL_INTERVAL register for this set of timings
152 nvidia,emc-configuration:
154 - $ref: /schemas/types.yaml#/definitions/uint32-array
156 EMC timing characterization data. These are the registers (see
157 section "15.6.2 EMC Registers" in the TRM) whose values need to
158 be specified, according to the board documentation.
160 - description: EMC_RC
161 - description: EMC_RFC
162 - description: EMC_RFC_SLR
163 - description: EMC_RAS
164 - description: EMC_RP
165 - description: EMC_R2W
166 - description: EMC_W2R
167 - description: EMC_R2P
168 - description: EMC_W2P
169 - description: EMC_RD_RCD
170 - description: EMC_WR_RCD
171 - description: EMC_RRD
172 - description: EMC_REXT
173 - description: EMC_WEXT
174 - description: EMC_WDV
175 - description: EMC_WDV_MASK
176 - description: EMC_QUSE
177 - description: EMC_QUSE_WIDTH
178 - description: EMC_IBDLY
179 - description: EMC_EINPUT
180 - description: EMC_EINPUT_DURATION
181 - description: EMC_PUTERM_EXTRA
182 - description: EMC_PUTERM_WIDTH
183 - description: EMC_PUTERM_ADJ
184 - description: EMC_CDB_CNTL_1
185 - description: EMC_CDB_CNTL_2
186 - description: EMC_CDB_CNTL_3
187 - description: EMC_QRST
188 - description: EMC_QSAFE
189 - description: EMC_RDV
190 - description: EMC_RDV_MASK
191 - description: EMC_REFRESH
192 - description: EMC_BURST_REFRESH_NUM
193 - description: EMC_PRE_REFRESH_REQ_CNT
194 - description: EMC_PDEX2WR
195 - description: EMC_PDEX2RD
196 - description: EMC_PCHG2PDEN
197 - description: EMC_ACT2PDEN
198 - description: EMC_AR2PDEN
199 - description: EMC_RW2PDEN
200 - description: EMC_TXSR
201 - description: EMC_TXSRDLL
202 - description: EMC_TCKE
203 - description: EMC_TCKESR
204 - description: EMC_TPD
205 - description: EMC_TFAW
206 - description: EMC_TRPAB
207 - description: EMC_TCLKSTABLE
208 - description: EMC_TCLKSTOP
209 - description: EMC_TREFBW
210 - description: EMC_FBIO_CFG6
211 - description: EMC_ODT_WRITE
212 - description: EMC_ODT_READ
213 - description: EMC_FBIO_CFG5
214 - description: EMC_CFG_DIG_DLL
215 - description: EMC_CFG_DIG_DLL_PERIOD
216 - description: EMC_DLL_XFORM_DQS0
217 - description: EMC_DLL_XFORM_DQS1
218 - description: EMC_DLL_XFORM_DQS2
219 - description: EMC_DLL_XFORM_DQS3
220 - description: EMC_DLL_XFORM_DQS4
221 - description: EMC_DLL_XFORM_DQS5
222 - description: EMC_DLL_XFORM_DQS6
223 - description: EMC_DLL_XFORM_DQS7
224 - description: EMC_DLL_XFORM_DQS8
225 - description: EMC_DLL_XFORM_DQS9
226 - description: EMC_DLL_XFORM_DQS10
227 - description: EMC_DLL_XFORM_DQS11
228 - description: EMC_DLL_XFORM_DQS12
229 - description: EMC_DLL_XFORM_DQS13
230 - description: EMC_DLL_XFORM_DQS14
231 - description: EMC_DLL_XFORM_DQS15
232 - description: EMC_DLL_XFORM_QUSE0
233 - description: EMC_DLL_XFORM_QUSE1
234 - description: EMC_DLL_XFORM_QUSE2
235 - description: EMC_DLL_XFORM_QUSE3
236 - description: EMC_DLL_XFORM_QUSE4
237 - description: EMC_DLL_XFORM_QUSE5
238 - description: EMC_DLL_XFORM_QUSE6
239 - description: EMC_DLL_XFORM_QUSE7
240 - description: EMC_DLL_XFORM_ADDR0
241 - description: EMC_DLL_XFORM_ADDR1
242 - description: EMC_DLL_XFORM_ADDR2
243 - description: EMC_DLL_XFORM_ADDR3
244 - description: EMC_DLL_XFORM_ADDR4
245 - description: EMC_DLL_XFORM_ADDR5
246 - description: EMC_DLL_XFORM_QUSE8
247 - description: EMC_DLL_XFORM_QUSE9
248 - description: EMC_DLL_XFORM_QUSE10
249 - description: EMC_DLL_XFORM_QUSE11
250 - description: EMC_DLL_XFORM_QUSE12
251 - description: EMC_DLL_XFORM_QUSE13
252 - description: EMC_DLL_XFORM_QUSE14
253 - description: EMC_DLL_XFORM_QUSE15
254 - description: EMC_DLI_TRIM_TXDQS0
255 - description: EMC_DLI_TRIM_TXDQS1
256 - description: EMC_DLI_TRIM_TXDQS2
257 - description: EMC_DLI_TRIM_TXDQS3
258 - description: EMC_DLI_TRIM_TXDQS4
259 - description: EMC_DLI_TRIM_TXDQS5
260 - description: EMC_DLI_TRIM_TXDQS6
261 - description: EMC_DLI_TRIM_TXDQS7
262 - description: EMC_DLI_TRIM_TXDQS8
263 - description: EMC_DLI_TRIM_TXDQS9
264 - description: EMC_DLI_TRIM_TXDQS10
265 - description: EMC_DLI_TRIM_TXDQS11
266 - description: EMC_DLI_TRIM_TXDQS12
267 - description: EMC_DLI_TRIM_TXDQS13
268 - description: EMC_DLI_TRIM_TXDQS14
269 - description: EMC_DLI_TRIM_TXDQS15
270 - description: EMC_DLL_XFORM_DQ0
271 - description: EMC_DLL_XFORM_DQ1
272 - description: EMC_DLL_XFORM_DQ2
273 - description: EMC_DLL_XFORM_DQ3
274 - description: EMC_DLL_XFORM_DQ4
275 - description: EMC_DLL_XFORM_DQ5
276 - description: EMC_DLL_XFORM_DQ6
277 - description: EMC_DLL_XFORM_DQ7
278 - description: EMC_XM2CMDPADCTRL
279 - description: EMC_XM2CMDPADCTRL4
280 - description: EMC_XM2CMDPADCTRL5
281 - description: EMC_XM2DQPADCTRL2
282 - description: EMC_XM2DQPADCTRL3
283 - description: EMC_XM2CLKPADCTRL
284 - description: EMC_XM2CLKPADCTRL2
285 - description: EMC_XM2COMPPADCTRL
286 - description: EMC_XM2VTTGENPADCTRL
287 - description: EMC_XM2VTTGENPADCTRL2
288 - description: EMC_XM2VTTGENPADCTRL3
289 - description: EMC_XM2DQSPADCTRL3
290 - description: EMC_XM2DQSPADCTRL4
291 - description: EMC_XM2DQSPADCTRL5
292 - description: EMC_XM2DQSPADCTRL6
293 - description: EMC_DSR_VTTGEN_DRV
294 - description: EMC_TXDSRVTTGEN
295 - description: EMC_FBIO_SPARE
296 - description: EMC_ZCAL_WAIT_CNT
297 - description: EMC_MRS_WAIT_CNT2
298 - description: EMC_CTT
299 - description: EMC_CTT_DURATION
300 - description: EMC_CFG_PIPE
301 - description: EMC_DYN_SELF_REF_CONTROL
302 - description: EMC_QPOP
306 - nvidia,emc-auto-cal-config
307 - nvidia,emc-auto-cal-config2
308 - nvidia,emc-auto-cal-config3
309 - nvidia,emc-auto-cal-interval
310 - nvidia,emc-bgbias-ctl0
313 - nvidia,emc-ctt-term-ctrl
317 - nvidia,emc-mode-reset
318 - nvidia,emc-mrs-wait-cnt
319 - nvidia,emc-sel-dpd-ctrl
320 - nvidia,emc-xm2dqspadctrl2
321 - nvidia,emc-zcal-cnt-long
322 - nvidia,emc-zcal-interval
323 - nvidia,emc-configuration
325 additionalProperties: false
332 - nvidia,memory-controller
334 additionalProperties: false
338 #include <dt-bindings/clock/tegra124-car.h>
339 #include <dt-bindings/interrupt-controller/arm-gic.h>
341 mc: memory-controller@70019000 {
342 compatible = "nvidia,tegra124-mc";
343 reg = <0x0 0x70019000 0x0 0x1000>;
344 clocks = <&tegra_car TEGRA124_CLK_MC>;
347 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
353 external-memory-controller@7001b000 {
354 compatible = "nvidia,tegra124-emc";
355 reg = <0x0 0x7001b000 0x0 0x1000>;
356 clocks = <&car TEGRA124_CLK_EMC>;
359 nvidia,memory-controller = <&mc>;
362 nvidia,ram-code = <3>;
365 clock-frequency = <12750000>;
367 nvidia,emc-auto-cal-config = <0xa1430000>;
368 nvidia,emc-auto-cal-config2 = <0x00000000>;
369 nvidia,emc-auto-cal-config3 = <0x00000000>;
370 nvidia,emc-auto-cal-interval = <0x001fffff>;
371 nvidia,emc-bgbias-ctl0 = <0x00000008>;
372 nvidia,emc-cfg = <0x73240000>;
373 nvidia,emc-cfg-2 = <0x000008c5>;
374 nvidia,emc-ctt-term-ctrl = <0x00000802>;
375 nvidia,emc-mode-1 = <0x80100003>;
376 nvidia,emc-mode-2 = <0x80200008>;
377 nvidia,emc-mode-4 = <0x00000000>;
378 nvidia,emc-mode-reset = <0x80001221>;
379 nvidia,emc-mrs-wait-cnt = <0x000e000e>;
380 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
381 nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
382 nvidia,emc-zcal-cnt-long = <0x00000042>;
383 nvidia,emc-zcal-interval = <0x00000000>;
385 nvidia,emc-configuration = <
386 0x00000000 /* EMC_RC */
387 0x00000003 /* EMC_RFC */
388 0x00000000 /* EMC_RFC_SLR */
389 0x00000000 /* EMC_RAS */
390 0x00000000 /* EMC_RP */
391 0x00000004 /* EMC_R2W */
392 0x0000000a /* EMC_W2R */
393 0x00000003 /* EMC_R2P */
394 0x0000000b /* EMC_W2P */
395 0x00000000 /* EMC_RD_RCD */
396 0x00000000 /* EMC_WR_RCD */
397 0x00000003 /* EMC_RRD */
398 0x00000003 /* EMC_REXT */
399 0x00000000 /* EMC_WEXT */
400 0x00000006 /* EMC_WDV */
401 0x00000006 /* EMC_WDV_MASK */
402 0x00000006 /* EMC_QUSE */
403 0x00000002 /* EMC_QUSE_WIDTH */
404 0x00000000 /* EMC_IBDLY */
405 0x00000005 /* EMC_EINPUT */
406 0x00000005 /* EMC_EINPUT_DURATION */
407 0x00010000 /* EMC_PUTERM_EXTRA */
408 0x00000003 /* EMC_PUTERM_WIDTH */
409 0x00000000 /* EMC_PUTERM_ADJ */
410 0x00000000 /* EMC_CDB_CNTL_1 */
411 0x00000000 /* EMC_CDB_CNTL_2 */
412 0x00000000 /* EMC_CDB_CNTL_3 */
413 0x00000004 /* EMC_QRST */
414 0x0000000c /* EMC_QSAFE */
415 0x0000000d /* EMC_RDV */
416 0x0000000f /* EMC_RDV_MASK */
417 0x00000060 /* EMC_REFRESH */
418 0x00000000 /* EMC_BURST_REFRESH_NUM */
419 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
420 0x00000002 /* EMC_PDEX2WR */
421 0x00000002 /* EMC_PDEX2RD */
422 0x00000001 /* EMC_PCHG2PDEN */
423 0x00000000 /* EMC_ACT2PDEN */
424 0x00000007 /* EMC_AR2PDEN */
425 0x0000000f /* EMC_RW2PDEN */
426 0x00000005 /* EMC_TXSR */
427 0x00000005 /* EMC_TXSRDLL */
428 0x00000004 /* EMC_TCKE */
429 0x00000005 /* EMC_TCKESR */
430 0x00000004 /* EMC_TPD */
431 0x00000000 /* EMC_TFAW */
432 0x00000000 /* EMC_TRPAB */
433 0x00000005 /* EMC_TCLKSTABLE */
434 0x00000005 /* EMC_TCLKSTOP */
435 0x00000064 /* EMC_TREFBW */
436 0x00000000 /* EMC_FBIO_CFG6 */
437 0x00000000 /* EMC_ODT_WRITE */
438 0x00000000 /* EMC_ODT_READ */
439 0x106aa298 /* EMC_FBIO_CFG5 */
440 0x002c00a0 /* EMC_CFG_DIG_DLL */
441 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
442 0x00064000 /* EMC_DLL_XFORM_DQS0 */
443 0x00064000 /* EMC_DLL_XFORM_DQS1 */
444 0x00064000 /* EMC_DLL_XFORM_DQS2 */
445 0x00064000 /* EMC_DLL_XFORM_DQS3 */
446 0x00064000 /* EMC_DLL_XFORM_DQS4 */
447 0x00064000 /* EMC_DLL_XFORM_DQS5 */
448 0x00064000 /* EMC_DLL_XFORM_DQS6 */
449 0x00064000 /* EMC_DLL_XFORM_DQS7 */
450 0x00064000 /* EMC_DLL_XFORM_DQS8 */
451 0x00064000 /* EMC_DLL_XFORM_DQS9 */
452 0x00064000 /* EMC_DLL_XFORM_DQS10 */
453 0x00064000 /* EMC_DLL_XFORM_DQS11 */
454 0x00064000 /* EMC_DLL_XFORM_DQS12 */
455 0x00064000 /* EMC_DLL_XFORM_DQS13 */
456 0x00064000 /* EMC_DLL_XFORM_DQS14 */
457 0x00064000 /* EMC_DLL_XFORM_DQS15 */
458 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
459 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
460 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
461 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
462 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
463 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
464 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
465 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
466 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
467 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
468 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
469 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
470 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
471 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
472 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
473 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
474 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
475 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
476 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
477 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
478 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
479 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
480 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
481 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
482 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
483 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
484 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
485 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
486 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
487 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
488 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
489 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
490 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
491 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
492 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
493 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
494 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
495 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
496 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
497 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
498 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
499 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
500 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
501 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
502 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
503 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
504 0x10000280 /* EMC_XM2CMDPADCTRL */
505 0x00000000 /* EMC_XM2CMDPADCTRL4 */
506 0x00111111 /* EMC_XM2CMDPADCTRL5 */
507 0x00000000 /* EMC_XM2DQPADCTRL2 */
508 0x00000000 /* EMC_XM2DQPADCTRL3 */
509 0x77ffc081 /* EMC_XM2CLKPADCTRL */
510 0x00000e0e /* EMC_XM2CLKPADCTRL2 */
511 0x81f1f108 /* EMC_XM2COMPPADCTRL */
512 0x07070004 /* EMC_XM2VTTGENPADCTRL */
513 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
514 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
515 0x51451400 /* EMC_XM2DQSPADCTRL3 */
516 0x00514514 /* EMC_XM2DQSPADCTRL4 */
517 0x00514514 /* EMC_XM2DQSPADCTRL5 */
518 0x51451400 /* EMC_XM2DQSPADCTRL6 */
519 0x0000003f /* EMC_DSR_VTTGEN_DRV */
520 0x00000007 /* EMC_TXDSRVTTGEN */
521 0x00000000 /* EMC_FBIO_SPARE */
522 0x00000042 /* EMC_ZCAL_WAIT_CNT */
523 0x000e000e /* EMC_MRS_WAIT_CNT2 */
524 0x00000000 /* EMC_CTT */
525 0x00000003 /* EMC_CTT_DURATION */
526 0x0000f2f3 /* EMC_CFG_PIPE */
527 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
528 0x0000000a /* EMC_QPOP */