1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM System MMU Architecture Implementation
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
14 ARM SoCs may contain an implementation of the ARM System Memory
15 Management Unit Architecture, which can be used to provide 1 or 2 stages
16 of address translation to bus masters external to the CPU.
18 The SMMU may also raise interrupts in response to various fault
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
38 - qcom,qcm2290-smmu-500
39 - qcom,qdu1000-smmu-500
40 - qcom,sa8775p-smmu-500
41 - qcom,sc7180-smmu-500
42 - qcom,sc7280-smmu-500
43 - qcom,sc8180x-smmu-500
44 - qcom,sc8280xp-smmu-500
45 - qcom,sdm670-smmu-500
46 - qcom,sdm845-smmu-500
50 - qcom,sm6115-smmu-500
51 - qcom,sm6125-smmu-500
52 - qcom,sm6350-smmu-500
53 - qcom,sm6375-smmu-500
54 - qcom,sm8150-smmu-500
55 - qcom,sm8250-smmu-500
56 - qcom,sm8350-smmu-500
57 - qcom,sm8450-smmu-500
58 - qcom,sm8550-smmu-500
59 - const: qcom,smmu-500
62 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
65 # Do not add additional SoC to this list. Instead use two previous lists.
67 - qcom,qcm2290-smmu-500
68 - qcom,sc7180-smmu-500
69 - qcom,sc7280-smmu-500
70 - qcom,sc8180x-smmu-500
71 - qcom,sc8280xp-smmu-500
72 - qcom,sdm845-smmu-500
73 - qcom,sm6115-smmu-500
74 - qcom,sm6350-smmu-500
75 - qcom,sm6375-smmu-500
76 - qcom,sm8150-smmu-500
77 - qcom,sm8250-smmu-500
78 - qcom,sm8350-smmu-500
79 - qcom,sm8450-smmu-500
81 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
84 - qcom,sa8775p-smmu-500
85 - qcom,sc7280-smmu-500
86 - qcom,sc8280xp-smmu-500
87 - qcom,sm6115-smmu-500
88 - qcom,sm6125-smmu-500
89 - qcom,sm8150-smmu-500
90 - qcom,sm8250-smmu-500
91 - qcom,sm8350-smmu-500
92 - const: qcom,adreno-smmu
93 - const: qcom,smmu-500
95 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
98 # Do not add additional SoC to this list. Instead use previous list.
100 - qcom,sc7280-smmu-500
101 - qcom,sm8150-smmu-500
102 - qcom,sm8250-smmu-500
103 - const: qcom,adreno-smmu
105 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
108 - qcom,msm8996-smmu-v2
109 - qcom,sc7180-smmu-v2
110 - qcom,sdm630-smmu-v2
111 - qcom,sdm845-smmu-v2
112 - qcom,sm6350-smmu-v2
113 - const: qcom,adreno-smmu
114 - const: qcom,smmu-v2
115 - description: Qcom Adreno GPUs on Google Cheza platform
117 - const: qcom,sdm845-smmu-v2
118 - const: qcom,smmu-v2
119 - description: Marvell SoCs implementing "arm,mmu-500"
121 - const: marvell,ap806-smmu-500
123 - description: NVIDIA SoCs that require memory controller interaction
124 and may program multiple ARM MMU-500s identically with the memory
125 controller interleaving translations between multiple instances
126 for improved performance.
129 - nvidia,tegra186-smmu
130 - nvidia,tegra194-smmu
131 - nvidia,tegra234-smmu
132 - const: nvidia,smmu-500
153 '#global-interrupts':
154 description: The number of global interrupts exposed by the device.
155 $ref: /schemas/types.yaml#/definitions/uint32
157 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
162 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
163 value of 1, each IOMMU specifier represents a distinct stream ID emitted
164 by that device into the relevant SMMU.
166 SMMUs with stream matching support and complex masters may use a value of
167 2, where the second cell of the IOMMU specifier represents an SMR mask to
168 combine with the ID in the first cell. Care must be taken to ensure the
169 set of matched IDs does not result in conflicts.
173 maxItems: 388 # 260 plus 128 contexts
175 Interrupt list, with the first #global-interrupts entries corresponding to
176 the global interrupts and any following entries corresponding to context
177 interrupts, specified in order of their indexing by the SMMU.
179 For SMMUv2 implementations, there must be exactly one interrupt per
180 context bank. In the case of a single, combined interrupt, it must be
181 listed multiple times.
185 Present if page table walks made by the SMMU are cache coherent with the
188 NOTE: this only applies to the SMMU itself, not masters connected
189 upstream of the SMMU.
191 calxeda,smmu-secure-config-access:
194 Enable proper handling of buggy implementations that always use secure
195 access to SMMU configuration registers. In this case non-secure aliases of
196 secure registers have to be used during SMMU configuration.
199 $ref: /schemas/types.yaml#/definitions/uint32
201 For SMMUs supporting stream matching and using #iommu-cells = <1>,
202 specifies a mask of bits to ignore when matching stream IDs (e.g. this may
203 be programmed into the SMRn.MASK field of every stream match register
204 used). For cases where it is desirable to ignore some portion of every
205 Stream ID (e.g. for certain MMU-500 configurations given globally unique
206 input IDs). This property is not valid for SMMUs using stream indexing, or
207 using stream matching with #iommu-cells = <2>, and may be ignored if
208 present in such cases.
222 nvidia,memory-controller:
224 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
225 The memory controller needs to be programmed with a mapping of memory
226 client IDs to ARM SMMU stream IDs.
228 If this property is absent, the mapping programmed by early firmware
229 will be used and it is not guaranteed that IOMMU translations will be
230 enabled for any given device.
231 $ref: /schemas/types.yaml#/definitions/phandle
236 - '#global-interrupts'
240 additionalProperties: false
248 - nvidia,tegra186-smmu
249 - nvidia,tegra194-smmu
250 - nvidia,tegra234-smmu
257 # The reference to the memory controller is required to ensure that the
258 # memory client to stream ID mapping can be done synchronously with the
261 - nvidia,memory-controller
272 - qcom,msm8998-smmu-v2
273 - qcom,sdm630-smmu-v2
282 - description: bus clock required for downstream bus access and for
292 - description: interface clock required to access smmu's registers
293 through the TCU's programming interface.
294 - description: bus clock required for memory access
295 - description: bus clock required for GPU memory access
304 - description: interface clock required to access mnoc's registers
305 through the TCU's programming interface.
306 - description: interface clock required to access smmu's registers
307 through the TCU's programming interface.
308 - description: bus clock required for the smmu ptw
315 - qcom,sm6375-smmu-v2
324 - description: bus clock required for downstream bus access and for
334 - description: interface clock required to access smmu's registers
335 through the TCU's programming interface.
336 - description: bus clock required for memory access
337 - description: bus clock required for GPU memory access
347 - description: interface clock required to access mnoc's registers
348 through the TCU's programming interface.
349 - description: interface clock required to access smmu's registers
350 through the TCU's programming interface.
351 - description: bus clock required for downstream bus access
352 - description: bus clock required for the smmu ptw
359 - qcom,msm8996-smmu-v2
360 - qcom,sc7180-smmu-v2
361 - qcom,sdm845-smmu-v2
371 - description: bus clock required for downstream bus access and for
373 - description: interface clock required to access smmu's registers
374 through the TCU's programming interface.
381 - qcom,sa8775p-smmu-500
382 - qcom,sc7280-smmu-500
383 - qcom,sc8280xp-smmu-500
388 - const: gcc_gpu_memnoc_gfx_clk
389 - const: gcc_gpu_snoc_dvm_gfx_clk
390 - const: gpu_cc_ahb_clk
391 - const: gpu_cc_hlos1_vote_gpu_smmu_clk
392 - const: gpu_cc_cx_gmu_clk
393 - const: gpu_cc_hub_cx_int_clk
394 - const: gpu_cc_hub_aon_clk
398 - description: GPU memnoc_gfx clock
399 - description: GPU snoc_dvm_gfx clock
400 - description: GPU ahb clock
401 - description: GPU hlos1_vote_GPU smmu clock
402 - description: GPU cx_gmu clock
403 - description: GPU hub_cx_int clock
404 - description: GPU hub_aon clock
411 - qcom,sm6350-smmu-v2
412 - qcom,sm8150-smmu-500
413 - qcom,sm8250-smmu-500
424 - description: bus clock required for AHB bus access
425 - description: bus clock required for downstream bus access and for
427 - description: interface clock required to access smmu's registers
428 through the TCU's programming interface.
435 - qcom,sm6115-smmu-500
436 - qcom,sm6125-smmu-500
437 - const: qcom,adreno-smmu
438 - const: qcom,smmu-500
450 - description: GPU memory bus clock
451 - description: Voter clock required for HLOS SMMU access
452 - description: Interface clock required for register access
454 # Disallow clocks for all other platforms with specific compatibles
461 - marvell,ap806-smmu-500
463 - qcom,qcm2290-smmu-500
464 - qcom,qdu1000-smmu-500
465 - qcom,sc7180-smmu-500
466 - qcom,sc8180x-smmu-500
467 - qcom,sdm670-smmu-500
468 - qcom,sdm845-smmu-500
469 - qcom,sdx55-smmu-500
470 - qcom,sdx65-smmu-500
471 - qcom,sm6350-smmu-500
472 - qcom,sm6375-smmu-500
473 - qcom,sm8350-smmu-500
474 - qcom,sm8450-smmu-500
475 - qcom,sm8550-smmu-500
485 const: qcom,sm6375-smmu-500
490 - description: SNoC MMU TBU RT GDSC
491 - description: SNoC MMU TBU NRT GDSC
492 - description: SNoC TURING MMU TBU0 GDSC
503 /* SMMU with stream matching or stream indexing */
504 smmu1: iommu@ba5e0000 {
505 compatible = "arm,smmu-v1";
506 reg = <0xba5e0000 0x10000>;
507 #global-interrupts = <2>;
508 interrupts = <0 32 4>,
510 <0 34 4>, /* This is the first context interrupt */
517 /* device with two stream IDs, 0 and 7 */
524 /* SMMU with stream matching */
525 smmu2: iommu@ba5f0000 {
526 compatible = "arm,smmu-v1";
527 reg = <0xba5f0000 0x10000>;
528 #global-interrupts = <2>;
529 interrupts = <0 38 4>,
531 <0 40 4>, /* This is the first context interrupt */
538 /* device with stream IDs 0 and 7 */
540 iommus = <&smmu2 0 0>,
544 /* device with stream IDs 1, 17, 33 and 49 */
546 iommus = <&smmu2 1 0x30>;
550 /* ARM MMU-500 with 10-bit stream ID input configuration */
551 smmu3: iommu@ba600000 {
552 compatible = "arm,mmu-500", "arm,smmu-v2";
553 reg = <0xba600000 0x10000>;
554 #global-interrupts = <2>;
555 interrupts = <0 44 4>,
557 <0 46 4>, /* This is the first context interrupt */
562 /* always ignore appended 5-bit TBU number */
563 stream-match-mask = <0x7c00>;
567 /* bus whose child devices emit one unique 10-bit stream
568 ID each, but may master through multiple SMMU TBUs */
569 iommu-map = <0 &smmu3 0 0x400>;
575 /* Qcom's arm,smmu-v2 implementation */
576 #include <dt-bindings/interrupt-controller/arm-gic.h>
577 #include <dt-bindings/interrupt-controller/irq.h>
578 smmu4: iommu@d00000 {
579 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
580 reg = <0xd00000 0x10000>;
582 #global-interrupts = <1>;
583 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
587 power-domains = <&mmcc 0>;
589 clocks = <&mmcc 123>,
591 clock-names = "bus", "iface";