1 ZTE VOU Display Controller
3 This is a display controller found on ZTE ZX296718 SoC. It includes multiple
4 Graphic Layer (GL) and Video Layer (VL), two Mixers/Channels, and a few blocks
5 handling scaling, color space conversion etc. VOU also integrates the support
6 for typical output devices, like HDMI, TV Encoder, VGA, and RGB LCD.
10 It must be the parent node of all the sub-device nodes.
13 - compatible: should be "zte,zx296718-vou"
14 - #address-cells: should be <1>
15 - #size-cells: should be <1>
16 - ranges: list of address translations between VOU and sub-devices
21 - compatible: should be "zte,zx296718-dpc"
22 - reg: Physical base address and length of DPC register regions, one for each
24 - reg-names: The names of register regions. The following regions are required:
30 - interrupts: VOU DPC interrupt number to CPU
31 - clocks: A list of phandle + clock-specifier pairs, one for each entry
33 - clock-names: A list of clock names. The following clocks are required:
42 - compatible: should be "zte,zx296718-hdmi"
43 - reg: Physical base address and length of the HDMI device IO region
44 - interrupts : HDMI interrupt number to CPU
45 - clocks: A list of phandle + clock-specifier pairs, one for each entry
47 - clock-names: A list of clock names. The following clocks are required:
55 compatible = "zte,zx296718-vou";
58 ranges = <0 0x1440000 0x10000>;
61 compatible = "zte,zx296718-dpc";
62 reg = <0x0000 0x1000>, <0x1000 0x1000>,
63 <0x5000 0x1000>, <0x6000 0x1000>,
65 reg-names = "osd", "timing_ctrl",
68 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
69 clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
70 <&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
71 clock-names = "aclk", "ppu_wclk",
72 "main_wclk", "aux_wclk";
76 compatible = "zte,zx296718-hdmi";
77 reg = <0xc000 0x4000>;
78 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
79 clocks = <&topcrm HDMI_OSC_CEC>,
80 <&topcrm HDMI_OSC_CLK>,
82 clock-names = "osc_cec", "osc_clk", "xclk";