1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC HDMI
10 - Inki Dae <inki.dae@samsung.com>
11 - Joonyoung Shim <jy0922.shim@samsung.com>
12 - Seung-Woo Kim <sw0312.kim@samsung.com>
13 - Kyungmin Park <kyungmin.park@samsung.com>
14 - Krzysztof Kozlowski <krzk@kernel.org>
19 - samsung,exynos4210-hdmi
20 - samsung,exynos4212-hdmi
21 - samsung,exynos5420-hdmi
22 - samsung,exynos5433-hdmi
33 $ref: /schemas/types.yaml#/definitions/phandle
35 Phandle to the HDMI DDC node.
39 Provides voltage source for DCC lines available on HDMI connector. When
40 there is no power provided for DDC epprom, some TV-sets do not pulls up
41 HPD (hot plug detect) line, what causes HDMI block to stay turned off.
42 When provided, the regulator allows TV-set correctly signal HPD event.
47 A GPIO line connected to HPD
53 $ref: /schemas/types.yaml#/definitions/phandle
54 description: Phandle to the HDMI PHY node.
57 $ref: /schemas/graph.yaml#/properties/ports
59 Contains a port which is connected to mic node.
67 samsung,syscon-phandle:
68 $ref: /schemas/types.yaml#/definitions/phandle
70 Phandle to the PMU system controller node.
72 samsung,sysreg-phandle:
73 $ref: /schemas/types.yaml#/definitions/phandle
75 Phandle to DISP system controller interface.
101 - samsung,syscon-phandle
112 const: samsung,exynos5433-hdmi
117 - description: Gate of HDMI IP APB bus.
118 - description: Gate of HDMI-PHY IP APB bus.
119 - description: Gate of HDMI TMDS clock.
120 - description: Gate of HDMI pixel clock.
121 - description: TMDS clock generated by HDMI-PHY.
122 - description: MUX used to switch between oscclk and tmds_clko,
123 respectively if HDMI-PHY is off and operational.
124 - description: Pixel clock generated by HDMI-PHY.
125 - description: MUX used to switch between oscclk and pixel_clko,
126 respectively if HDMI-PHY is off and operational.
127 - description: Oscillator clock, used as parent of following *_user
128 clocks in case HDMI-PHY is not operational.
129 - description: Gate of HDMI SPDIF clock.
137 - const: tmds_clko_user
139 - const: pixel_clko_user
143 - samsung,sysreg-phandle
148 - description: Gate of HDMI IP bus clock.
149 - description: Gate of HDMI special clock.
150 - description: Pixel special clock, one of the two possible inputs
152 - description: HDMI PHY clock output, one of two possible inputs of
154 - description: It is required by the driver to switch between the 2
155 parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is stable
156 after configuration, parent is set to sclk_hdmiphy else
163 - const: sclk_hdmiphy
166 additionalProperties: false
170 #include <dt-bindings/clock/exynos5433.h>
171 #include <dt-bindings/gpio/gpio.h>
172 #include <dt-bindings/interrupt-controller/arm-gic.h>
175 compatible = "samsung,exynos5433-hdmi";
176 reg = <0x13970000 0x70000>;
177 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&cmu_disp CLK_PCLK_HDMI>,
179 <&cmu_disp CLK_PCLK_HDMIPHY>,
180 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
181 <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
182 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
183 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
184 <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
185 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
187 <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
188 clock-names = "hdmi_pclk",
200 samsung,syscon-phandle = <&pmu_system_controller>;
201 samsung,sysreg-phandle = <&syscon_disp>;
202 #sound-dai-cells = <0>;
204 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>;
205 vdd-supply = <&ldo6_reg>;
206 vdd_osc-supply = <&ldo7_reg>;
207 vdd_pll-supply = <&ldo6_reg>;
210 #address-cells = <1>;
215 hdmi_to_tv: endpoint {
216 remote-endpoint = <&tv_to_hdmi>;
222 hdmi_to_mhl: endpoint {
223 remote-endpoint = <&mhl_to_hdmi>;