Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SM8450 Display MDSS
   8
   9 maintainers:
  10   - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  11
  12 description:
  13   SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
  14   DPU display controller, DSI and DP interfaces etc.
  15
  16 $ref: /schemas/display/msm/mdss-common.yaml#
  17
  18 properties:
  19   compatible:
  20     const: qcom,sm8450-mdss
  21
  22   clocks:
  23     items:
  24       - description: Display AHB
  25       - description: Display hf AXI
  26       - description: Display sf AXI
  27       - description: Display core
  28
  29   iommus:
  30     maxItems: 1
  31
  32   interconnects:
  33     maxItems: 2
  34
  35   interconnect-names:
  36     maxItems: 2
  37
  38 patternProperties:
  39   "^display-controller@[0-9a-f]+$":
  40     type: object
  41     properties:
  42       compatible:
  43         const: qcom,sm8450-dpu
  44
  45   "^dsi@[0-9a-f]+$":
  46     type: object
  47     properties:
  48       compatible:
  49         items:
  50           - const: qcom,sm8450-dsi-ctrl
  51           - const: qcom,mdss-dsi-ctrl
  52
  53   "^phy@[0-9a-f]+$":
  54     type: object
  55     properties:
  56       compatible:
  57         const: qcom,sm8450-dsi-phy-5nm
  58
  59 required:
  60   - compatible
  61
  62 unevaluatedProperties: false
  63
  64 examples:
  65   - |
  66     #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
  67     #include <dt-bindings/clock/qcom,gcc-sm8450.h>
  68     #include <dt-bindings/clock/qcom,rpmh.h>
  69     #include <dt-bindings/interrupt-controller/arm-gic.h>
  70     #include <dt-bindings/interconnect/qcom,sm8450.h>
  71     #include <dt-bindings/power/qcom-rpmpd.h>
  72
  73     display-subsystem@ae00000 {
  74         compatible = "qcom,sm8450-mdss";
  75         reg = <0x0ae00000 0x1000>;
  76         reg-names = "mdss";
  77
  78         interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
  79                         <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>;
  80         interconnect-names = "mdp0-mem", "mdp1-mem";
  81
  82         resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
  83
  84         power-domains = <&dispcc MDSS_GDSC>;
  85
  86         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
  87                  <&gcc GCC_DISP_HF_AXI_CLK>,
  88                  <&gcc GCC_DISP_SF_AXI_CLK>,
  89                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
  90         clock-names = "iface", "bus", "nrt_bus", "core";
  91
  92         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  93         interrupt-controller;
  94         #interrupt-cells = <1>;
  95
  96         iommus = <&apps_smmu 0x2800 0x402>;
  97
  98         #address-cells = <1>;
  99         #size-cells = <1>;
 100         ranges;
 101
 102         display-controller@ae01000 {
 103             compatible = "qcom,sm8450-dpu";
 104             reg = <0x0ae01000 0x8f000>,
 105                   <0x0aeb0000 0x2008>;
 106             reg-names = "mdp", "vbif";
 107
 108             clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
 109                     <&gcc GCC_DISP_SF_AXI_CLK>,
 110                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
 111                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
 112                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
 113                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 114             clock-names = "bus",
 115                           "nrt_bus",
 116                           "iface",
 117                           "lut",
 118                           "core",
 119                           "vsync";
 120
 121             assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 122             assigned-clock-rates = <19200000>;
 123
 124             operating-points-v2 = <&mdp_opp_table>;
 125             power-domains = <&rpmhpd SM8450_MMCX>;
 126
 127             interrupt-parent = <&mdss>;
 128             interrupts = <0>;
 129
 130             ports {
 131                 #address-cells = <1>;
 132                 #size-cells = <0>;
 133
 134                 port@0 {
 135                     reg = <0>;
 136                     dpu_intf1_out: endpoint {
 137                         remote-endpoint = <&dsi0_in>;
 138                     };
 139                 };
 140
 141                 port@1 {
 142                     reg = <1>;
 143                     dpu_intf2_out: endpoint {
 144                         remote-endpoint = <&dsi1_in>;
 145                     };
 146                 };
 147             };
 148
 149             mdp_opp_table: opp-table {
 150                 compatible = "operating-points-v2";
 151
 152                 opp-172000000{
 153                     opp-hz = /bits/ 64 <172000000>;
 154                     required-opps = <&rpmhpd_opp_low_svs_d1>;
 155                 };
 156
 157                 opp-200000000 {
 158                     opp-hz = /bits/ 64 <200000000>;
 159                     required-opps = <&rpmhpd_opp_low_svs>;
 160                 };
 161
 162                 opp-325000000 {
 163                     opp-hz = /bits/ 64 <325000000>;
 164                     required-opps = <&rpmhpd_opp_svs>;
 165                 };
 166
 167                 opp-375000000 {
 168                     opp-hz = /bits/ 64 <375000000>;
 169                     required-opps = <&rpmhpd_opp_svs_l1>;
 170                 };
 171
 172                 opp-500000000 {
 173                     opp-hz = /bits/ 64 <500000000>;
 174                     required-opps = <&rpmhpd_opp_nom>;
 175                 };
 176             };
 177         };
 178
 179         dsi@ae94000 {
 180             compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 181             reg = <0x0ae94000 0x400>;
 182             reg-names = "dsi_ctrl";
 183
 184             interrupt-parent = <&mdss>;
 185             interrupts = <4>;
 186
 187             clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
 188                      <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
 189                      <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
 190                      <&dispcc DISP_CC_MDSS_ESC0_CLK>,
 191                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 192                      <&gcc GCC_DISP_HF_AXI_CLK>;
 193             clock-names = "byte",
 194                           "byte_intf",
 195                           "pixel",
 196                           "core",
 197                           "iface",
 198                           "bus";
 199
 200             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
 201                               <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
 202             assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
 203
 204             operating-points-v2 = <&dsi_opp_table>;
 205             power-domains = <&rpmhpd SM8450_MMCX>;
 206
 207             phys = <&dsi0_phy>;
 208             phy-names = "dsi";
 209
 210             #address-cells = <1>;
 211             #size-cells = <0>;
 212
 213             ports {
 214                 #address-cells = <1>;
 215                 #size-cells = <0>;
 216
 217                 port@0 {
 218                     reg = <0>;
 219                     dsi0_in: endpoint {
 220                         remote-endpoint = <&dpu_intf1_out>;
 221                     };
 222                 };
 223
 224                 port@1 {
 225                     reg = <1>;
 226                     dsi0_out: endpoint {
 227                     };
 228                 };
 229             };
 230
 231             dsi_opp_table: opp-table {
 232                 compatible = "operating-points-v2";
 233
 234                 opp-160310000{
 235                     opp-hz = /bits/ 64 <160310000>;
 236                     required-opps = <&rpmhpd_opp_low_svs_d1>;
 237                 };
 238
 239                 opp-187500000 {
 240                     opp-hz = /bits/ 64 <187500000>;
 241                     required-opps = <&rpmhpd_opp_low_svs>;
 242                 };
 243
 244                 opp-300000000 {
 245                     opp-hz = /bits/ 64 <300000000>;
 246                     required-opps = <&rpmhpd_opp_svs>;
 247                 };
 248
 249                 opp-358000000 {
 250                     opp-hz = /bits/ 64 <358000000>;
 251                     required-opps = <&rpmhpd_opp_svs_l1>;
 252                 };
 253             };
 254         };
 255
 256         dsi0_phy: phy@ae94400 {
 257             compatible = "qcom,sm8450-dsi-phy-5nm";
 258             reg = <0x0ae94400 0x200>,
 259                   <0x0ae94600 0x280>,
 260                   <0x0ae94900 0x260>;
 261             reg-names = "dsi_phy",
 262                         "dsi_phy_lane",
 263                         "dsi_pll";
 264
 265             #clock-cells = <1>;
 266             #phy-cells = <0>;
 267
 268             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 269                      <&rpmhcc RPMH_CXO_CLK>;
 270             clock-names = "iface", "ref";
 271             vdds-supply = <&vreg_dsi_phy>;
 272         };
 273
 274         dsi@ae96000 {
 275             compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 276             reg = <0x0ae96000 0x400>;
 277             reg-names = "dsi_ctrl";
 278
 279             interrupt-parent = <&mdss>;
 280             interrupts = <5>;
 281
 282             clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
 283                      <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
 284                      <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
 285                      <&dispcc DISP_CC_MDSS_ESC1_CLK>,
 286                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 287                      <&gcc GCC_DISP_HF_AXI_CLK>;
 288             clock-names = "byte",
 289                           "byte_intf",
 290                           "pixel",
 291                           "core",
 292                           "iface",
 293                           "bus";
 294
 295             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
 296                               <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
 297             assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
 298
 299             operating-points-v2 = <&dsi_opp_table>;
 300             power-domains = <&rpmhpd SM8450_MMCX>;
 301
 302             phys = <&dsi1_phy>;
 303             phy-names = "dsi";
 304
 305             #address-cells = <1>;
 306             #size-cells = <0>;
 307
 308             ports {
 309                 #address-cells = <1>;
 310                 #size-cells = <0>;
 311
 312                 port@0 {
 313                     reg = <0>;
 314                     dsi1_in: endpoint {
 315                         remote-endpoint = <&dpu_intf2_out>;
 316                     };
 317                 };
 318
 319                 port@1 {
 320                     reg = <1>;
 321                     dsi1_out: endpoint {
 322                     };
 323                 };
 324             };
 325         };
 326
 327         dsi1_phy: phy@ae96400 {
 328             compatible = "qcom,sm8450-dsi-phy-5nm";
 329             reg = <0x0ae96400 0x200>,
 330                   <0x0ae96600 0x280>,
 331                   <0x0ae96900 0x260>;
 332             reg-names = "dsi_phy",
 333                         "dsi_phy_lane",
 334                         "dsi_pll";
 335
 336             #clock-cells = <1>;
 337             #phy-cells = <0>;
 338
 339             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 340                      <&rpmhcc RPMH_CXO_CLK>;
 341             clock-names = "iface", "ref";
 342             vdds-supply = <&vreg_dsi_phy>;
 343         };
 344     };
 345 ...