1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/qcom,mdp5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Adreno/Snapdragon Mobile Display controller (MDP5)
10 MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994
14 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
15 - Rob Clark <robdclark@gmail.com>
38 pattern: '^display-controller@[0-9a-f]+$'
65 # MSM8996 has additional iommu clock
76 - description: Interconnect path from mdp0 (or a single mdp) port to the data bus
77 - description: Interconnect path from mdp1 port to the data bus
78 - description: Interconnect path from rotator port to the data bus
89 - description: apps SMMU with the Stream-ID mask for Hard-Fail port0
94 operating-points-v2: true
99 $ref: /schemas/graph.yaml#/properties/ports
101 Contains the list of output ports from DPU device. These ports
102 connect to interfaces that are external to the DPU hardware,
103 such as DSI, DP etc. MDP5 devices support up to 4 ports:
104 one or two DSI ports, HDMI and eDP.
108 $ref: /schemas/graph.yaml#/properties/port
110 # at least one port is required
122 additionalProperties: false
126 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
127 #include <dt-bindings/interrupt-controller/arm-gic.h>
128 display-controller@1a01000 {
129 compatible = "qcom,mdp5";
130 reg = <0x1a01000 0x90000>;
131 reg-names = "mdp_phys";
133 interrupt-parent = <&mdss>;
136 clocks = <&gcc GCC_MDSS_AHB_CLK>,
137 <&gcc GCC_MDSS_AXI_CLK>,
138 <&gcc GCC_MDSS_MDP_CLK>,
139 <&gcc GCC_MDSS_VSYNC_CLK>;
140 clock-names = "iface",
146 #address-cells = <1>;
152 remote-endpoint = <&dsi0_in>;