Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Display DSI 7nm PHY
   8
   9 maintainers:
  10   - Jonathan Marek <jonathan@marek.ca>
  11
  12 allOf:
  13   - $ref: dsi-phy-common.yaml#
  14
  15 properties:
  16   compatible:
  17     enum:
  18       - qcom,dsi-phy-7nm
  19       - qcom,dsi-phy-7nm-8150
  20       - qcom,sc7280-dsi-phy-7nm
  21       - qcom,sm6375-dsi-phy-7nm
  22       - qcom,sm8350-dsi-phy-5nm
  23       - qcom,sm8450-dsi-phy-5nm
  24       - qcom,sm8550-dsi-phy-4nm
  25
  26   reg:
  27     items:
  28       - description: dsi phy register set
  29       - description: dsi phy lane register set
  30       - description: dsi pll register set
  31
  32   reg-names:
  33     items:
  34       - const: dsi_phy
  35       - const: dsi_phy_lane
  36       - const: dsi_pll
  37
  38   vdds-supply:
  39     description: |
  40       Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150)
  41
  42   phy-type:
  43     description: D-PHY (default) or C-PHY mode
  44     enum: [ 10, 11 ]
  45     default: 10
  46
  47 required:
  48   - compatible
  49   - reg
  50   - reg-names
  51
  52 unevaluatedProperties: false
  53
  54 examples:
  55   - |
  56      #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
  57      #include <dt-bindings/clock/qcom,rpmh.h>
  58
  59      dsi-phy@ae94400 {
  60          compatible = "qcom,dsi-phy-7nm";
  61          reg = <0x0ae94400 0x200>,
  62                <0x0ae94600 0x280>,
  63                <0x0ae94900 0x260>;
  64          reg-names = "dsi_phy",
  65                      "dsi_phy_lane",
  66                      "dsi_pll";
  67
  68          #clock-cells = <1>;
  69          #phy-cells = <0>;
  70
  71          vdds-supply = <&vreg_l5a_0p88>;
  72          clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
  73                   <&rpmhcc RPMH_CXO_CLK>;
  74          clock-names = "iface", "ref";
  75      };