Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Display Clock & Reset Controller for SM8550
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11   - Neil Armstrong <neil.armstrong@linaro.org>
  12
  13 description: |
  14   Qualcomm display clock control module provides the clocks, resets and power
  15   domains on SM8550.
  16
  17   See also:
  18   - include/dt-bindings/clock/qcom,sm8550-dispcc.h
  19   - include/dt-bindings/clock/qcom,sm8650-dispcc.h
  20
  21 properties:
  22   compatible:
  23     enum:
  24       - qcom,sm8550-dispcc
  25       - qcom,sm8650-dispcc
  26
  27   clocks:
  28     items:
  29       - description: Board XO source
  30       - description: Board Always On XO source
  31       - description: Display's AHB clock
  32       - description: sleep clock
  33       - description: Byte clock from DSI PHY0
  34       - description: Pixel clock from DSI PHY0
  35       - description: Byte clock from DSI PHY1
  36       - description: Pixel clock from DSI PHY1
  37       - description: Link clock from DP PHY0
  38       - description: VCO DIV clock from DP PHY0
  39       - description: Link clock from DP PHY1
  40       - description: VCO DIV clock from DP PHY1
  41       - description: Link clock from DP PHY2
  42       - description: VCO DIV clock from DP PHY2
  43       - description: Link clock from DP PHY3
  44       - description: VCO DIV clock from DP PHY3
  45
  46   '#clock-cells':
  47     const: 1
  48
  49   '#reset-cells':
  50     const: 1
  51
  52   '#power-domain-cells':
  53     const: 1
  54
  55   reg:
  56     maxItems: 1
  57
  58   power-domains:
  59     description:
  60       A phandle and PM domain specifier for the MMCX power domain.
  61     maxItems: 1
  62
  63   required-opps:
  64     description:
  65       A phandle to an OPP node describing required MMCX performance point.
  66     maxItems: 1
  67
  68 required:
  69   - compatible
  70   - reg
  71   - clocks
  72   - '#clock-cells'
  73   - '#reset-cells'
  74   - '#power-domain-cells'
  75
  76 additionalProperties: false
  77
  78 examples:
  79   - |
  80     #include <dt-bindings/clock/qcom,sm8550-gcc.h>
  81     #include <dt-bindings/clock/qcom,rpmh.h>
  82     #include <dt-bindings/power/qcom,rpmhpd.h>
  83     clock-controller@af00000 {
  84       compatible = "qcom,sm8550-dispcc";
  85       reg = <0x0af00000 0x10000>;
  86       clocks = <&rpmhcc RPMH_CXO_CLK>,
  87                <&rpmhcc RPMH_CXO_CLK_A>,
  88                <&gcc GCC_DISP_AHB_CLK>,
  89                <&sleep_clk>,
  90                <&dsi0_phy 0>,
  91                <&dsi0_phy 1>,
  92                <&dsi1_phy 0>,
  93                <&dsi1_phy 1>,
  94                <&dp0_phy 0>,
  95                <&dp0_phy 1>,
  96                <&dp1_phy 0>,
  97                <&dp1_phy 1>,
  98                <&dp2_phy 0>,
  99                <&dp2_phy 1>,
 100                <&dp3_phy 0>,
 101                <&dp3_phy 1>;
 102       #clock-cells = <1>;
 103       #reset-cells = <1>;
 104       #power-domain-cells = <1>;
 105       power-domains = <&rpmhpd RPMHPD_MMCX>;
 106       required-opps = <&rpmhpd_opp_low_svs>;
 107     };
 108 ...