1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Multimedia Clock & Reset Controller Binding
10 - Jeffrey Hugo <quic_jhugo@quicinc.com>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm multimedia clock control module which supports the clocks, resets and
47 '#power-domain-cells':
55 Protected clock specifier list as per common clock binding
59 Regulator supply for the GPU_GX GDSC
66 - '#power-domain-cells'
68 additionalProperties: false
89 const: qcom,mmcc-msm8994
94 - description: Board XO source
95 - description: Global PLL 0 clock
96 - description: MMSS NoC AHB clock
97 - description: GFX3D clock
98 - description: DSI phy instance 0 dsi clock
99 - description: DSI phy instance 0 byte clock
100 - description: DSI phy instance 1 dsi clock
101 - description: DSI phy instance 1 byte clock
102 - description: HDMI phy PLL clock
109 - const: oxili_gfx3d_clk_src
120 const: qcom,mmcc-msm8998
125 - description: Board XO source
126 - description: Global PLL 0 clock
127 - description: DSI phy instance 0 dsi clock
128 - description: DSI phy instance 0 byte clock
129 - description: DSI phy instance 1 dsi clock
130 - description: DSI phy instance 1 byte clock
131 - description: HDMI phy PLL clock
132 - description: DisplayPort phy PLL link clock
133 - description: DisplayPort phy PLL vco clock
134 - description: Test clock
147 - const: core_bi_pll_test_se
160 - description: Board XO source
161 - description: Board sleep source
162 - description: Global PLL 0 clock
163 - description: Global PLL 0 DIV clock
164 - description: DSI phy instance 0 dsi clock
165 - description: DSI phy instance 0 byte clock
166 - description: DSI phy instance 1 dsi clock
167 - description: DSI phy instance 1 byte clock
168 - description: DisplayPort phy PLL link clock
169 - description: DisplayPort phy PLL vco clock
181 - const: dp_link_2x_clk_divsel_five
182 - const: dp_vco_divided_clk_src_mux
185 # Example for MMCC for MSM8960:
187 clock-controller@4000000 {
188 compatible = "qcom,mmcc-msm8960";
189 reg = <0x4000000 0x1000>;
192 #power-domain-cells = <1>;