1 Device Tree Clock bindings for arch-at91
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "atmel,at91sam9x5-sckc" or
11 at91 SCKC (Slow Clock Controller)
12 This node contains the slow clock definitions.
14 "atmel,at91sam9x5-clk-slow-osc":
17 "atmel,at91sam9x5-clk-slow-rc-osc":
18 at91 internal slow RC oscillator
20 "atmel,at91rm9200-pmc" or
21 "atmel,at91sam9g45-pmc" or
22 "atmel,at91sam9n12-pmc" or
23 "atmel,at91sam9x5-pmc" or
25 at91 PMC (Power Management Controller)
26 All at91 specific clocks (clocks defined below) must be child
29 "atmel,at91sam9x5-clk-slow" (under sckc node)
31 "atmel,at91sam9260-clk-slow" (under pmc node):
34 "atmel,at91rm9200-clk-main-osc"
35 "atmel,at91sam9x5-clk-main-rc-osc"
38 "atmel,at91sam9x5-clk-main"
39 "atmel,at91rm9200-clk-main":
42 "atmel,at91rm9200-clk-master" or
43 "atmel,at91sam9x5-clk-master":
46 "atmel,at91sam9x5-clk-peripheral" or
47 "atmel,at91rm9200-clk-peripheral":
48 at91 peripheral clocks
50 "atmel,at91rm9200-clk-pll" or
51 "atmel,at91sam9g45-clk-pll" or
52 "atmel,at91sam9g20-clk-pllb" or
53 "atmel,sama5d3-clk-pll":
56 "atmel,at91sam9x5-clk-plldiv":
59 "atmel,at91rm9200-clk-programmable" or
60 "atmel,at91sam9g45-clk-programmable" or
61 "atmel,at91sam9x5-clk-programmable":
62 at91 programmable clocks
64 "atmel,at91sam9x5-clk-smd":
65 at91 SMD (Soft Modem) clock
67 "atmel,at91rm9200-clk-system":
70 "atmel,at91rm9200-clk-usb" or
71 "atmel,at91sam9x5-clk-usb" or
72 "atmel,at91sam9n12-clk-usb":
75 "atmel,at91sam9x5-clk-utmi":
78 "atmel,sama5d4-clk-h32mx":
81 "atmel,sama5d2-clk-generated":
84 "atmel,sama5d2-clk-audio-pll-frac":
85 at91 audio fractional pll
87 "atmel,sama5d2-clk-audio-pll-pad":
88 at91 audio pll CLK_AUDIO output pin
90 "atmel,sama5d2-clk-audio-pll-pmc"
91 at91 audio pll output on AUDIOPLLCLK that feeds the PMC
92 and can be used by peripheral clock or generic clock
94 Required properties for SCKC node:
95 - reg : defines the IO memory reserved for the SCKC.
96 - #size-cells : shall be 0 (reg is used to encode clk id).
97 - #address-cells : shall be 1 (reg is used to encode clk id).
101 sckc: sckc@fffffe50 {
102 compatible = "atmel,sama5d3-pmc";
103 reg = <0xfffffe50 0x4>
105 #address-cells = <1>;
107 /* put at91 slow clocks here */
111 Required properties for internal slow RC oscillator:
112 - #clock-cells : from common clock binding; shall be set to 0.
113 - clock-frequency : define the internal RC oscillator frequency.
116 - clock-accuracy : define the internal RC oscillator accuracy.
119 slow_rc_osc: slow_rc_osc {
120 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
121 clock-frequency = <32768>;
122 clock-accuracy = <50000000>;
125 Required properties for slow oscillator:
126 - #clock-cells : from common clock binding; shall be set to 0.
127 - clocks : shall encode the main osc source clk sources (see atmel datasheet).
130 - atmel,osc-bypass : boolean property. Set this when a clock signal is directly
135 compatible = "atmel,at91rm9200-clk-slow-osc";
137 clocks = <&slow_xtal>;
140 Required properties for slow clock:
141 - #clock-cells : from common clock binding; shall be set to 0.
142 - clocks : shall encode the slow clk sources (see atmel datasheet).
146 compatible = "atmel,at91sam9x5-clk-slow";
148 clocks = <&slow_rc_osc &slow_osc>;
151 Required properties for PMC node:
152 - reg : defines the IO memory reserved for the PMC.
153 - #size-cells : shall be 0 (reg is used to encode clk id).
154 - #address-cells : shall be 1 (reg is used to encode clk id).
155 - interrupts : shall be set to PMC interrupt line.
156 - interrupt-controller : tell that the PMC is an interrupt controller.
157 - #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
158 and reflect the bit position in the PMC_ER/DR/SR registers.
159 You can use the dt macros defined in dt-bindings/clock/at91.h.
160 0 (AT91_PMC_MOSCS) -> main oscillator ready
161 1 (AT91_PMC_LOCKA) -> PLL A ready
162 2 (AT91_PMC_LOCKB) -> PLL B ready
163 3 (AT91_PMC_MCKRDY) -> master clock ready
164 6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready
165 8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready
166 16 (AT91_PMC_MOSCSELS) -> main oscillator selected
167 17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized
168 18 (AT91_PMC_CFDEV) -> clock failure detected
172 compatible = "atmel,sama5d3-pmc";
173 interrupts = <1 4 7>;
174 interrupt-controller;
175 #interrupt-cells = <2>;
177 #address-cells = <1>;
179 /* put at91 clocks here */
182 Required properties for main clock internal RC oscillator:
183 - interrupts : shall be set to "<0>".
184 - clock-frequency : define the internal RC oscillator frequency.
187 - clock-accuracy : define the internal RC oscillator accuracy.
190 main_rc_osc: main_rc_osc {
191 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
192 interrupt-parent = <&pmc>;
194 clock-frequency = <12000000>;
195 clock-accuracy = <50000000>;
198 Required properties for main clock oscillator:
199 - interrupts : shall be set to "<0>".
200 - #clock-cells : from common clock binding; shall be set to 0.
201 - clocks : shall encode the main osc source clk sources (see atmel datasheet).
204 - atmel,osc-bypass : boolean property. Specified if a clock signal is provided
207 clock signal is directly provided on XIN pin.
211 compatible = "atmel,at91rm9200-clk-main-osc";
212 interrupt-parent = <&pmc>;
215 clocks = <&main_xtal>;
218 Required properties for main clock:
219 - interrupts : shall be set to "<0>".
220 - #clock-cells : from common clock binding; shall be set to 0.
221 - clocks : shall encode the main clk sources (see atmel datasheet).
225 compatible = "atmel,at91sam9x5-clk-main";
226 interrupt-parent = <&pmc>;
229 clocks = <&main_rc_osc &main_osc>;
232 Required properties for master clock:
233 - interrupts : shall be set to "<3>".
234 - #clock-cells : from common clock binding; shall be set to 0.
235 - clocks : shall be the master clock sources (see atmel datasheet) phandles.
236 e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>".
237 - atmel,clk-output-range : minimum and maximum clock frequency (two u32
239 e.g. output = <0 133000000>; <=> 0 to 133MHz.
240 - atmel,clk-divisors : master clock divisors table (four u32 fields).
241 0 <=> reserved value.
242 e.g. divisors = <1 2 4 6>;
243 - atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the
244 PRES field as CLOCK_DIV3 (e.g sam9x5).
248 compatible = "atmel,at91rm9200-clk-master";
249 interrupt-parent = <&pmc>;
252 atmel,clk-output-range = <0 133000000>;
253 atmel,clk-divisors = <1 2 4 0>;
256 Required properties for peripheral clocks:
257 - #size-cells : shall be 0 (reg is used to encode clk id).
258 - #address-cells : shall be 1 (reg is used to encode clk id).
259 - clocks : shall be the master clock phandle.
260 e.g. clocks = <&mck>;
261 - name: device tree node describing a specific peripheral clock.
262 * #clock-cells : from common clock binding; shall be set to 0.
263 * reg: peripheral id. See Atmel's datasheets to get a full
264 list of peripheral ids.
265 * atmel,clk-output-range : minimum and maximum clock frequency
266 (two u32 fields). Only valid on at91sam9x5-clk-peripheral
271 compatible = "atmel,at91sam9x5-clk-peripheral";
273 #address-cells = <1>;
279 atmel,clk-output-range = <0 133000000>;
285 atmel,clk-output-range = <0 66000000>;
290 Required properties for pll clocks:
291 - interrupts : shall be set to "<1>".
292 - #clock-cells : from common clock binding; shall be set to 0.
293 - clocks : shall be the main clock phandle.
297 - atmel,clk-input-range : minimum and maximum source clock frequency (two u32
299 e.g. input = <1 32000000>; <=> 1 to 32MHz.
300 - #atmel,pll-clk-output-range-cells : number of cells reserved for pll output
301 range description. Sould be set to 2, 3
303 * 1st and 2nd cells represent the frequency range (min-max).
304 * 3rd cell is optional and represents the OUT field value for the given
306 * 4th cell is optional and represents the ICPLL field (PLLICPR
308 - atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter
309 depending on #atmel,pll-output-range-cells
314 compatible = "atmel,at91sam9g45-clk-pll";
315 interrupt-parent = <&pmc>;
320 atmel,clk-input-range = <2000000 32000000>;
321 #atmel,pll-clk-output-range-cells = <4>;
322 atmel,pll-clk-output-ranges = <74500000 800000000 0 0
323 69500000 750000000 1 0
324 64500000 700000000 2 0
325 59500000 650000000 3 0
326 54500000 600000000 0 1
327 49500000 550000000 1 1
328 44500000 500000000 2 1
329 40000000 450000000 3 1>;
332 Required properties for plldiv clocks (plldiv = pll / 2):
333 - #clock-cells : from common clock binding; shall be set to 0.
334 - clocks : shall be the plla clock phandle.
336 The pll divisor is equal to 2 and cannot be changed.
340 compatible = "atmel,at91sam9x5-clk-plldiv";
345 Required properties for programmable clocks:
346 - #size-cells : shall be 0 (reg is used to encode clk id).
347 - #address-cells : shall be 1 (reg is used to encode clk id).
348 - clocks : shall be the programmable clock source phandles.
349 e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
350 - name: device tree node describing a specific prog clock.
351 * #clock-cells : from common clock binding; shall be set to 0.
352 * reg : programmable clock id (register offset from PCKx
354 * interrupts : shall be set to "<(8 + id)>".
358 compatible = "atmel,at91sam9g45-clk-programmable";
360 #address-cells = <1>;
361 interrupt-parent = <&pmc>;
362 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
378 Required properties for smd clock:
379 - #clock-cells : from common clock binding; shall be set to 0.
380 - clocks : shall be the smd clock source phandles.
381 e.g. clocks = <&plladiv>, <&utmi>;
385 compatible = "atmel,at91sam9x5-clk-smd";
387 clocks = <&plladiv>, <&utmi>;
390 Required properties for system clocks:
391 - #size-cells : shall be 0 (reg is used to encode clk id).
392 - #address-cells : shall be 1 (reg is used to encode clk id).
393 - name: device tree node describing a specific system clock.
394 * #clock-cells : from common clock binding; shall be set to 0.
395 * reg: system clock id (bit position in SCER/SCDR/SCSR registers).
396 See Atmel's datasheet to get a full list of system clock ids.
400 compatible = "atmel,at91rm9200-clk-system";
401 #address-cells = <1>;
424 Required properties for usb clock:
425 - #clock-cells : from common clock binding; shall be set to 0.
426 - clocks : shall be the smd clock source phandles.
427 e.g. clocks = <&pllb>;
428 - atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"):
429 usb clock divisor table.
430 e.g. divisors = <1 2 4 0>;
434 compatible = "atmel,at91sam9x5-clk-usb";
436 clocks = <&plladiv>, <&utmi>;
440 compatible = "atmel,at91rm9200-clk-usb";
443 atmel,clk-divisors = <1 2 4 0>;
447 Required properties for utmi clock:
448 - interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>".
449 - #clock-cells : from common clock binding; shall be set to 0.
450 - clocks : shall be the main clock source phandle.
454 compatible = "atmel,at91sam9x5-clk-utmi";
455 interrupt-parent = <&pmc>;
456 interrupts = <AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>;
461 Required properties for 32 bits bus Matrix clock (h32mx clock):
462 - #clock-cells : from common clock binding; shall be set to 0.
463 - clocks : shall be the master clock source phandle.
468 compatible = "atmel,sama5d4-clk-h32mx";
472 Required properties for generated clocks:
473 - #size-cells : shall be 0 (reg is used to encode clk id).
474 - #address-cells : shall be 1 (reg is used to encode clk id).
475 - clocks : shall be the generated clock source phandles.
476 e.g. clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
477 - name: device tree node describing a specific generated clock.
478 * #clock-cells : from common clock binding; shall be set to 0.
479 * reg: peripheral id. See Atmel's datasheets to get a full
480 list of peripheral ids.
481 * atmel,clk-output-range : minimum and maximum clock frequency
486 compatible = "atmel,sama5d2-clk-generated";
487 #address-cells = <1>;
489 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
491 tcb0_gclk: tcb0_gclk {
494 atmel,clk-output-range = <0 83000000>;
500 atmel,clk-output-range = <0 83000000>;