1 Device Tree Clock bindings for arch-at91
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "atmel,at91sam9x5-sckc" or
11 at91 SCKC (Slow Clock Controller)
12 This node contains the slow clock definitions.
14 "atmel,at91sam9x5-clk-slow-osc":
17 "atmel,at91sam9x5-clk-slow-rc-osc":
18 at91 internal slow RC oscillator
20 "atmel,at91rm9200-pmc" or
21 "atmel,at91sam9g45-pmc" or
22 "atmel,at91sam9n12-pmc" or
23 "atmel,at91sam9x5-pmc" or
25 at91 PMC (Power Management Controller)
26 All at91 specific clocks (clocks defined below) must be child
29 "atmel,at91sam9x5-clk-slow" (under sckc node)
31 "atmel,at91sam9260-clk-slow" (under pmc node):
34 "atmel,at91rm9200-clk-main-osc"
35 "atmel,at91sam9x5-clk-main-rc-osc"
38 "atmel,at91sam9x5-clk-main"
39 "atmel,at91rm9200-clk-main":
42 "atmel,at91rm9200-clk-master" or
43 "atmel,at91sam9x5-clk-master":
46 "atmel,at91sam9x5-clk-peripheral" or
47 "atmel,at91rm9200-clk-peripheral":
48 at91 peripheral clocks
50 "atmel,at91rm9200-clk-pll" or
51 "atmel,at91sam9g45-clk-pll" or
52 "atmel,at91sam9g20-clk-pllb" or
53 "atmel,sama5d3-clk-pll":
56 "atmel,at91sam9x5-clk-plldiv":
59 "atmel,at91rm9200-clk-programmable" or
60 "atmel,at91sam9g45-clk-programmable" or
61 "atmel,at91sam9x5-clk-programmable":
62 at91 programmable clocks
64 "atmel,at91sam9x5-clk-smd":
65 at91 SMD (Soft Modem) clock
67 "atmel,at91rm9200-clk-system":
70 "atmel,at91rm9200-clk-usb" or
71 "atmel,at91sam9x5-clk-usb" or
72 "atmel,at91sam9n12-clk-usb":
75 "atmel,at91sam9x5-clk-utmi":
78 "atmel,sama5d4-clk-h32mx":
81 "atmel,sama5d2-clk-generated":
84 "atmel,sama5d2-clk-audio-pll-frac":
85 at91 audio fractional pll
87 "atmel,sama5d2-clk-audio-pll-pad":
88 at91 audio pll CLK_AUDIO output pin
90 "atmel,sama5d2-clk-audio-pll-pmc"
91 at91 audio pll output on AUDIOPLLCLK that feeds the PMC
92 and can be used by peripheral clock or generic clock
94 "atmel,sama5d2-clk-i2s-mux" (under pmc node):
95 at91 I2S clock source selection
97 Required properties for SCKC node:
98 - reg : defines the IO memory reserved for the SCKC.
99 - #size-cells : shall be 0 (reg is used to encode clk id).
100 - #address-cells : shall be 1 (reg is used to encode clk id).
104 sckc: sckc@fffffe50 {
105 compatible = "atmel,sama5d3-pmc";
106 reg = <0xfffffe50 0x4>
108 #address-cells = <1>;
110 /* put at91 slow clocks here */
114 Required properties for internal slow RC oscillator:
115 - #clock-cells : from common clock binding; shall be set to 0.
116 - clock-frequency : define the internal RC oscillator frequency.
119 - clock-accuracy : define the internal RC oscillator accuracy.
122 slow_rc_osc: slow_rc_osc {
123 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
124 clock-frequency = <32768>;
125 clock-accuracy = <50000000>;
128 Required properties for slow oscillator:
129 - #clock-cells : from common clock binding; shall be set to 0.
130 - clocks : shall encode the main osc source clk sources (see atmel datasheet).
133 - atmel,osc-bypass : boolean property. Set this when a clock signal is directly
138 compatible = "atmel,at91rm9200-clk-slow-osc";
140 clocks = <&slow_xtal>;
143 Required properties for slow clock:
144 - #clock-cells : from common clock binding; shall be set to 0.
145 - clocks : shall encode the slow clk sources (see atmel datasheet).
149 compatible = "atmel,at91sam9x5-clk-slow";
151 clocks = <&slow_rc_osc &slow_osc>;
154 Required properties for PMC node:
155 - reg : defines the IO memory reserved for the PMC.
156 - #size-cells : shall be 0 (reg is used to encode clk id).
157 - #address-cells : shall be 1 (reg is used to encode clk id).
158 - interrupts : shall be set to PMC interrupt line.
159 - interrupt-controller : tell that the PMC is an interrupt controller.
160 - #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
161 and reflect the bit position in the PMC_ER/DR/SR registers.
162 You can use the dt macros defined in dt-bindings/clock/at91.h.
163 0 (AT91_PMC_MOSCS) -> main oscillator ready
164 1 (AT91_PMC_LOCKA) -> PLL A ready
165 2 (AT91_PMC_LOCKB) -> PLL B ready
166 3 (AT91_PMC_MCKRDY) -> master clock ready
167 6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready
168 8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready
169 16 (AT91_PMC_MOSCSELS) -> main oscillator selected
170 17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized
171 18 (AT91_PMC_CFDEV) -> clock failure detected
175 compatible = "atmel,sama5d3-pmc";
176 interrupts = <1 4 7>;
177 interrupt-controller;
178 #interrupt-cells = <2>;
180 #address-cells = <1>;
182 /* put at91 clocks here */
185 Required properties for main clock internal RC oscillator:
186 - interrupts : shall be set to "<0>".
187 - clock-frequency : define the internal RC oscillator frequency.
190 - clock-accuracy : define the internal RC oscillator accuracy.
193 main_rc_osc: main_rc_osc {
194 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
195 interrupt-parent = <&pmc>;
197 clock-frequency = <12000000>;
198 clock-accuracy = <50000000>;
201 Required properties for main clock oscillator:
202 - interrupts : shall be set to "<0>".
203 - #clock-cells : from common clock binding; shall be set to 0.
204 - clocks : shall encode the main osc source clk sources (see atmel datasheet).
207 - atmel,osc-bypass : boolean property. Specified if a clock signal is provided
210 clock signal is directly provided on XIN pin.
214 compatible = "atmel,at91rm9200-clk-main-osc";
215 interrupt-parent = <&pmc>;
218 clocks = <&main_xtal>;
221 Required properties for main clock:
222 - interrupts : shall be set to "<0>".
223 - #clock-cells : from common clock binding; shall be set to 0.
224 - clocks : shall encode the main clk sources (see atmel datasheet).
228 compatible = "atmel,at91sam9x5-clk-main";
229 interrupt-parent = <&pmc>;
232 clocks = <&main_rc_osc &main_osc>;
235 Required properties for master clock:
236 - interrupts : shall be set to "<3>".
237 - #clock-cells : from common clock binding; shall be set to 0.
238 - clocks : shall be the master clock sources (see atmel datasheet) phandles.
239 e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>".
240 - atmel,clk-output-range : minimum and maximum clock frequency (two u32
242 e.g. output = <0 133000000>; <=> 0 to 133MHz.
243 - atmel,clk-divisors : master clock divisors table (four u32 fields).
244 0 <=> reserved value.
245 e.g. divisors = <1 2 4 6>;
246 - atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the
247 PRES field as CLOCK_DIV3 (e.g sam9x5).
251 compatible = "atmel,at91rm9200-clk-master";
252 interrupt-parent = <&pmc>;
255 atmel,clk-output-range = <0 133000000>;
256 atmel,clk-divisors = <1 2 4 0>;
259 Required properties for peripheral clocks:
260 - #size-cells : shall be 0 (reg is used to encode clk id).
261 - #address-cells : shall be 1 (reg is used to encode clk id).
262 - clocks : shall be the master clock phandle.
263 e.g. clocks = <&mck>;
264 - name: device tree node describing a specific peripheral clock.
265 * #clock-cells : from common clock binding; shall be set to 0.
266 * reg: peripheral id. See Atmel's datasheets to get a full
267 list of peripheral ids.
268 * atmel,clk-output-range : minimum and maximum clock frequency
269 (two u32 fields). Only valid on at91sam9x5-clk-peripheral
274 compatible = "atmel,at91sam9x5-clk-peripheral";
276 #address-cells = <1>;
282 atmel,clk-output-range = <0 133000000>;
288 atmel,clk-output-range = <0 66000000>;
293 Required properties for pll clocks:
294 - interrupts : shall be set to "<1>".
295 - #clock-cells : from common clock binding; shall be set to 0.
296 - clocks : shall be the main clock phandle.
300 - atmel,clk-input-range : minimum and maximum source clock frequency (two u32
302 e.g. input = <1 32000000>; <=> 1 to 32MHz.
303 - #atmel,pll-clk-output-range-cells : number of cells reserved for pll output
304 range description. Sould be set to 2, 3
306 * 1st and 2nd cells represent the frequency range (min-max).
307 * 3rd cell is optional and represents the OUT field value for the given
309 * 4th cell is optional and represents the ICPLL field (PLLICPR
311 - atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter
312 depending on #atmel,pll-output-range-cells
317 compatible = "atmel,at91sam9g45-clk-pll";
318 interrupt-parent = <&pmc>;
323 atmel,clk-input-range = <2000000 32000000>;
324 #atmel,pll-clk-output-range-cells = <4>;
325 atmel,pll-clk-output-ranges = <74500000 800000000 0 0
326 69500000 750000000 1 0
327 64500000 700000000 2 0
328 59500000 650000000 3 0
329 54500000 600000000 0 1
330 49500000 550000000 1 1
331 44500000 500000000 2 1
332 40000000 450000000 3 1>;
335 Required properties for plldiv clocks (plldiv = pll / 2):
336 - #clock-cells : from common clock binding; shall be set to 0.
337 - clocks : shall be the plla clock phandle.
339 The pll divisor is equal to 2 and cannot be changed.
343 compatible = "atmel,at91sam9x5-clk-plldiv";
348 Required properties for programmable clocks:
349 - #size-cells : shall be 0 (reg is used to encode clk id).
350 - #address-cells : shall be 1 (reg is used to encode clk id).
351 - clocks : shall be the programmable clock source phandles.
352 e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
353 - name: device tree node describing a specific prog clock.
354 * #clock-cells : from common clock binding; shall be set to 0.
355 * reg : programmable clock id (register offset from PCKx
357 * interrupts : shall be set to "<(8 + id)>".
361 compatible = "atmel,at91sam9g45-clk-programmable";
363 #address-cells = <1>;
364 interrupt-parent = <&pmc>;
365 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
381 Required properties for smd clock:
382 - #clock-cells : from common clock binding; shall be set to 0.
383 - clocks : shall be the smd clock source phandles.
384 e.g. clocks = <&plladiv>, <&utmi>;
388 compatible = "atmel,at91sam9x5-clk-smd";
390 clocks = <&plladiv>, <&utmi>;
393 Required properties for system clocks:
394 - #size-cells : shall be 0 (reg is used to encode clk id).
395 - #address-cells : shall be 1 (reg is used to encode clk id).
396 - name: device tree node describing a specific system clock.
397 * #clock-cells : from common clock binding; shall be set to 0.
398 * reg: system clock id (bit position in SCER/SCDR/SCSR registers).
399 See Atmel's datasheet to get a full list of system clock ids.
403 compatible = "atmel,at91rm9200-clk-system";
404 #address-cells = <1>;
427 Required properties for usb clock:
428 - #clock-cells : from common clock binding; shall be set to 0.
429 - clocks : shall be the smd clock source phandles.
430 e.g. clocks = <&pllb>;
431 - atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"):
432 usb clock divisor table.
433 e.g. divisors = <1 2 4 0>;
437 compatible = "atmel,at91sam9x5-clk-usb";
439 clocks = <&plladiv>, <&utmi>;
443 compatible = "atmel,at91rm9200-clk-usb";
446 atmel,clk-divisors = <1 2 4 0>;
450 Required properties for utmi clock:
451 - interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>".
452 - #clock-cells : from common clock binding; shall be set to 0.
453 - clocks : shall be the main clock source phandle.
457 compatible = "atmel,at91sam9x5-clk-utmi";
458 interrupt-parent = <&pmc>;
459 interrupts = <AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>;
464 Required properties for 32 bits bus Matrix clock (h32mx clock):
465 - #clock-cells : from common clock binding; shall be set to 0.
466 - clocks : shall be the master clock source phandle.
471 compatible = "atmel,sama5d4-clk-h32mx";
475 Required properties for generated clocks:
476 - #size-cells : shall be 0 (reg is used to encode clk id).
477 - #address-cells : shall be 1 (reg is used to encode clk id).
478 - clocks : shall be the generated clock source phandles.
479 e.g. clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
480 - name: device tree node describing a specific generated clock.
481 * #clock-cells : from common clock binding; shall be set to 0.
482 * reg: peripheral id. See Atmel's datasheets to get a full
483 list of peripheral ids.
484 * atmel,clk-output-range : minimum and maximum clock frequency
489 compatible = "atmel,sama5d2-clk-generated";
490 #address-cells = <1>;
492 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
494 tcb0_gclk: tcb0_gclk {
497 atmel,clk-output-range = <0 83000000>;
503 atmel,clk-output-range = <0 83000000>;
507 Required properties for I2S mux clocks:
508 - #size-cells : shall be 0 (reg is used to encode I2S bus id).
509 - #address-cells : shall be 1 (reg is used to encode I2S bus id).
510 - name: device tree node describing a specific mux clock.
511 * #clock-cells : from common clock binding; shall be set to 0.
512 * clocks : shall be the mux clock parent phandles; shall be 2 phandles:
513 peripheral and generated clock; the first phandle shall belong to the
514 peripheral clock and the second one shall belong to the generated
515 clock; "clock-indices" property can be user to specify
517 * reg: I2S bus id of the corresponding mux clock.
518 e.g. reg = <0>; for i2s0, reg = <1>; for i2s1
522 compatible = "atmel,sama5d2-clk-i2s-mux";
523 #address-cells = <1>;
526 i2s0muxck: i2s0_muxclk {
527 clocks = <&i2s0_clk>, <&i2s0_gclk>;
532 i2s1muxck: i2s1_muxclk {
533 clocks = <&i2s1_clk>, <&i2s1_gclk>;