1 NXP i.MX System Controller Firmware (SCFW)
2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
6 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
7 (QM, QP), and i.MX8QX (QXP, DX).
9 The AP communicates with the SC using a multi-ported MU module found
10 in the LSIO subsystem. The current definition of this MU module provides
11 5 remote AP connections to the SC to support up to 5 execution environments
12 (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
13 with the LSIO DSC IP bus. The SC firmware will communicate with this MU
16 System Controller Device Node:
17 ============================================================
19 The scu node with the following properties shall be under the /firmware/ node.
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
25 "rx0", "rx1", "rx2", "rx3";
26 include "gip3" if want to support general MU interrupt.
27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
28 rx, and 1 optional MU channel for general interrupt.
29 All MU channels must be in the same MU instance.
30 Cross instances are not allowed. The MU instance can only
31 be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
32 to make sure use the one which is not conflict with other
33 execution environments. e.g. ATF.
35 Channel 0 must be "tx0" or "rx0".
36 Channel 1 must be "tx1" or "rx1".
37 Channel 2 must be "tx2" or "rx2".
38 Channel 3 must be "tx3" or "rx3".
39 General interrupt rx channel must be "gip3".
41 mboxes = <&lsio_mu1 0 0
50 See Documentation/devicetree/bindings/mailbox/fsl,mu.txt
51 for detailed mailbox binding.
53 Note: Each mu which supports general interrupt should have an alias correctly
54 numbered in "aliases" node.
60 i.MX SCU Client Device Node:
61 ============================================================
63 Client nodes are maintained as children of the relevant IMX-SCU device node.
65 Power domain bindings based on SCU Message Protocol
66 ------------------------------------------------------------
68 This binding for the SCU power domain providers uses the generic power
72 - compatible: Should be one of:
75 followed by "fsl,scu-pd"
77 - #power-domain-cells: Must be 1. Contains the Resource ID used by
79 See detailed Resource ID list from:
80 include/dt-bindings/firmware/imx/rsrc.h
82 Clock bindings based on SCU Message Protocol
83 ------------------------------------------------------------
85 This binding uses the common clock binding[1].
88 - compatible: Should be one of:
91 followed by "fsl,scu-clk"
92 - #clock-cells: Should be 1. Contains the Clock ID value.
93 - clocks: List of clock specifiers, must contain an entry for
94 each required entry in clock-names
95 - clock-names: Should include entries "xtal_32KHz", "xtal_24MHz"
97 The clock consumer should specify the desired clock by having the clock
98 ID in its "clocks" phandle cell.
100 See the full list of clock IDs from:
101 include/dt-bindings/clock/imx8qxp-clock.h
103 Pinctrl bindings based on SCU Message Protocol
104 ------------------------------------------------------------
106 This binding uses the i.MX common pinctrl binding[3].
109 - compatible: Should be one of:
111 "fsl,imx8qxp-iomuxc".
113 Required properties for Pinctrl sub nodes:
114 - fsl,pins: Each entry consists of 3 integers which represents
115 the mux and config setting for one pin. The first 2
116 integers <pin_id mux_mode> are specified using a
117 PIN_FUNC_ID macro, which can be found in
118 <dt-bindings/pinctrl/pads-imx8qm.h>,
119 <dt-bindings/pinctrl/pads-imx8qxp.h>.
120 The last integer CONFIG is the pad setting value like
123 Please refer to i.MX8QXP Reference Manual for detailed
126 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
127 [2] Documentation/devicetree/bindings/power/power_domain.txt
128 [3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
130 RTC bindings based on SCU Message Protocol
131 ------------------------------------------------------------
134 - compatible: should be "fsl,imx8qxp-sc-rtc";
136 Watchdog bindings based on SCU Message Protocol
137 ------------------------------------------------------------
140 - compatible: should be:
142 followed by "fsl,imx-sc-wdt";
144 - timeout-sec: contains the watchdog timeout in seconds.
152 lsio_mu1: mailbox@5d1c0000 {
159 compatible = "fsl,imx-scu";
160 mbox-names = "tx0", "tx1", "tx2", "tx3",
161 "rx0", "rx1", "rx2", "rx3",
163 mboxes = <&lsio_mu1 0 0
174 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
179 compatible = "fsl,imx8qxp-iomuxc";
181 pinctrl_lpuart0: lpuart0grp {
183 SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
184 SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
191 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
192 #power-domain-cells = <1>;
196 compatible = "fsl,imx8qxp-sc-rtc";
200 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_lpuart0>;
210 clocks = <&clk IMX8QXP_UART0_CLK>,
211 <&clk IMX8QXP_UART0_IPG_CLK>;
212 clock-names = "per", "ipg";
213 power-domains = <&pd IMX_SC_R_UART_0>;